W-angler wrote:
Current implementation is based on the
comment(https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36#issuecomment-1867859642),
not the RFC. @dtcxzyw
https://github.com/llvm/llvm-project/pull/76357
___
cfe-commits
@@ -0,0 +1,112 @@
+// RUN: %clang -### -c %s 2>&1 -march=rvi20u32 | FileCheck
-check-prefix=RVI20U32 %s
+// RVI20U32: "-target-cpu" "generic-rv32"
+// RVI20U32: "-target-feature" "-a"
+// RVI20U32: "-target-feature" "-c"
+// RVI20U32: "-target-feature" "-d"
+// RVI20U32:
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From f4ca1ac0dedf5af0d9ddf05f7a67f30091b296ee Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option
This PR
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 806babf92282735c364b7ac88faa5256d04f2742 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option
This PR
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 48f36c6e742e743e33f931536c653bf4e23568fb
f9d4a2be0f1e1b8815d2feaebdc918d501c776da --
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/76357
This PR implements the draft
https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36.
Currently, we replace specified profile in `-march` with standard
arch string.
We may need to pass it to
