https://github.com/topperc updated
https://github.com/llvm/llvm-project/pull/83896
>From f22a5cd30f77b2043f9c1f7f4482fad87fb79250 Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH 1/9] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
quic-garvgupt wrote:
Thanks for the prompt reply and latest patchset.
1. Do we need to add documentation in RISCVUsage.rst file for xsfcease?
2. Also, as we are adding cease instruction in this PR, can we rename the PR to
include the cease instruction as well?
https://github.com/topperc updated
https://github.com/llvm/llvm-project/pull/83896
>From f22a5cd30f77b2043f9c1f7f4482fad87fb79250 Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH 1/8] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
topperc wrote:
> Thanks for clearing the confusion around whether rs1 would be optional or
> not. Can we also add lit tests for the aliases?
I already addded tests
https://github.com/llvm/llvm-project/pull/83896/commits/f6f43e9f8ffa8b58d63178d28c826d0009de2f3b
quic-garvgupt wrote:
Thanks for clearing the confusion around whether rs1 would be optional or not.
Can we also add lit tests for the aliases?
https://github.com/llvm/llvm-project/pull/83896
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://github.com/DataCorrupted updated
https://github.com/llvm/llvm-project/pull/83896
>From f22a5cd30f77b2043f9c1f7f4482fad87fb79250 Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH 1/7] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff f1ca2a09671e4d4acc2bea362b39268ed7883b6d
c31b2fd3cb923bc306cf9d086bb7723e4c7004cd --
https://github.com/topperc updated
https://github.com/llvm/llvm-project/pull/83896
>From f22a5cd30f77b2043f9c1f7f4482fad87fb79250 Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH 1/6] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
https://github.com/topperc updated
https://github.com/llvm/llvm-project/pull/83896
>From f22a5cd30f77b2043f9c1f7f4482fad87fb79250 Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH 1/5] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
https://github.com/topperc updated
https://github.com/llvm/llvm-project/pull/83896
>From 9434f834c4d48559aeec94403c927f48b15763e3 Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH 1/5] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
topperc wrote:
> > > Hi @topperc, can you add instruction alias for cflush and cdiscard
> > > instructions when the rs1 is X0 to `sf.cflush.d.l1` and `sf.cflush.d.l1`
> > > respectively, as this register is optional according to spec?
> >
> >
> > x0 has special meaning, but the spec never
quic-garvgupt wrote:
> > Also, I think we might need to update the extensions in the
> > `RISCVProcessors.td` file under SIFIVE_S76 microcontroller?
>
> This is a M-mode only extension, and we haven't historically been adding M or
> S mode extensions to the -mcpu lists. Except for
quic-garvgupt wrote:
> > Hi @topperc, can you add instruction alias for cflush and cdiscard
> > instructions when the rs1 is X0 to `sf.cflush.d.l1` and `sf.cflush.d.l1`
> > respectively, as this register is optional according to spec?
>
> x0 has special meaning, but the spec never says it is
topperc wrote:
> Also, I think we might need to update the extensions in the
> `RISCVProcessors.td` file under SIFIVE_S76 microcontroller?
This is a M-mode only extension, and we haven't historically been adding M or S
mode extensions to the -mcpu lists. Except for `xiangshan-nanhu` having
topperc wrote:
> Hi @topperc, can you add instruction alias for cflush and cdiscard
> instructions when the rs1 is X0 to `sf.cflush.d.l1` and `sf.cflush.d.l1`
> respectively, as this register is optional according to spec?
x0 has special meaning, but the spec never says it is "optional".
quic-garvgupt wrote:
Also, I think we might need to update the extensions in the
`RISCVProcessors.td` file under SIFIVE_S76 microcontroller?
https://github.com/llvm/llvm-project/pull/83896
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
quic-garvgupt wrote:
Hi @topperc, can you add instruction alias for cflush and cdiscard instructions
when the rs1 is X0 to `sf.cflush.d.l1` and `sf.cflush.d.l1` respectively, as
this register is optional according to spec?
https://github.com/llvm/llvm-project/pull/83896
apazos wrote:
Also, @topperc, we should add the new extensions to the list of vendor
extensions in the specs:
ttps://github.com/riscv-non-isa/riscv-toolchain-conventions/tree/master?tab=readme-ov-file#list-of-vendor-extensions
https://github.com/llvm/llvm-project/pull/83896
apazos wrote:
@topperc , how about the CEASE instruction? Can you add it in this patch?
https://github.com/llvm/llvm-project/pull/83896
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/jrtc27 dismissed
https://github.com/llvm/llvm-project/pull/83896
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
jrtc27 wrote:
> @jrtc27 does this look better now?
Yes; thanks
https://github.com/llvm/llvm-project/pull/83896
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
topperc wrote:
@jrtc27 does this look better now?
https://github.com/llvm/llvm-project/pull/83896
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
sunshaoce wrote:
> > > By the way, is there any plan to support `CFLUSH.I.L1` in the future?
> >
> >
> > Flushing the instruction cache doesn't make sense given it can never be
> > dirty. Invalidating/discarding does, but that's just what fence.i is doing?
>
> A cflush.i.l1 did appear in
topperc wrote:
> > By the way, is there any plan to support `CFLUSH.I.L1` in the future?
>
> Flushing the instruction cache doesn't make sense given it can never be
> dirty. Invalidating/discarding does, but that's just what fence.i is doing?
A cflush.i.l1 did appear in some SiFive manual at
jrtc27 wrote:
> By the way, is there any plan to support `CFLUSH.I.L1` in the future?
Flushing the instruction cache doesn't make sense given it can never be dirty.
Invalidating/discarding does, but that's just what fence.i is doing?
https://github.com/llvm/llvm-project/pull/83896
sunshaoce wrote:
By the way, is there any plan to support `CFLUSH.I.L1` in the future?
https://github.com/llvm/llvm-project/pull/83896
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/topperc updated
https://github.com/llvm/llvm-project/pull/83896
>From 9434f834c4d48559aeec94403c927f48b15763e3 Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH 1/4] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
https://github.com/jrtc27 requested changes to this pull request.
These need the vendor "sf." prefix
https://github.com/llvm/llvm-project/pull/83896
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://github.com/topperc updated
https://github.com/llvm/llvm-project/pull/83896
>From 9434f834c4d48559aeec94403c927f48b15763e3 Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH 1/3] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
https://github.com/topperc updated
https://github.com/llvm/llvm-project/pull/83896
>From 9434f834c4d48559aeec94403c927f48b15763e3 Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH 1/2] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
@@ -60,6 +60,8 @@
// CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
// CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
// CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}}
+// CHECK-NOT: __riscv_sifivecdiscarddlone {{.*$}}
+// CHECK-NOT: __riscv_sifivecflushdlone {{.*$}}
dtcxzyw
llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
@llvm/pr-subscribers-clang
Author: Craig Topper (topperc)
Changes
These were in LLVM 17 but removed from LLVM 18 due to an incorrect extension
name being used.
This restores them with new extension names that match SiFive's downstream
https://github.com/topperc created
https://github.com/llvm/llvm-project/pull/83896
These were in LLVM 17 but removed from LLVM 18 due to an incorrect extension
name being used.
This restores them with new extension names that match SiFive's downstream
compiler. The extension name has been
33 matches
Mail list logo
