[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)

https://github.com/Khao7342 updated https://github.com/llvm/llvm-project/pull/89359 >From e51498e67409836b099fa892b17d71e44a7d403b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E9=83=9D=E5=BA=B7=E8=BE=BE?= Date: Fri, 19 Apr 2024 17:18:10 +0800 Subject: [PATCH] [RISCV] Add processor definition for

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)

@@ -378,3 +378,30 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>;

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)

@@ -378,3 +378,30 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>;

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)

Khao7342 wrote: > Has the target architecture been finalized? (As in what it should be, not > necessarily the rtl) > > Just yesterday, there was a significant change in vector execution units: > >

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)

Khao7342 wrote: > Has KunMingHu's RTL been finalized (IIRC, we have vector unit under > development)? And can we have different doc for different generations of > XiangShan? Thanks for your attention to Xiangshan. KunMingHu's RTL has not been finalized yet. The development work on vectors is

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)

camel-cdr wrote: Has the target architecture been finalized? (As in what it should be, not necessarily the rtl) Just yesterday, there was a significant change in vector execution units:

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)

wangpc-pp wrote: Has KunMingHu's RTl been finalized (IIRC, we have developing vector unit)? And can we have different doc for different generations of XiangShan? https://github.com/llvm/llvm-project/pull/89359 ___ cfe-commits mailing list

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)

llvmbot wrote: @llvm/pr-subscribers-clang-driver Author: None (Khao7342) Changes This pull request adds definitions for the XiangShan-KunMingHu processor. "XiangShan" is a high-performance open-source RISC-V processor project, and "KunMingHu" architecture is its third generation.

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)

llvmbot wrote: @llvm/pr-subscribers-backend-risc-v Author: None (Khao7342) Changes This pull request adds definitions for the XiangShan-KunMingHu processor. "XiangShan" is a high-performance open-source RISC-V processor project, and "KunMingHu" architecture is its third generation.

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)

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[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)

https://github.com/Khao7342 created https://github.com/llvm/llvm-project/pull/89359 This pull request adds definitions for the XiangShan-KunMingHu processor. "XiangShan" is a high-performance open-source RISC-V processor project, and "KunMingHu" architecture is its third generation. Official