https://github.com/wangpc-pp closed
https://github.com/llvm/llvm-project/pull/76357
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>From 28000eb88b54b02993107d4f222acc5d733c623f Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH 1/3] [RISCV] Support RISC-V Profiles in -march option
This PR
https://github.com/topperc approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/76357
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 28000eb88b54b02993107d4f222acc5d733c623f Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH 1/2] [RISCV] Support RISC-V Profiles in -march option
This PR
@@ -244,6 +249,42 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
};
// clang-format on
+static const RISCVProfile SupportedProfiles[] = {
topperc wrote:
`const` -> `constexpr` to be sure the StringLiteral constexpr constructor
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 28000eb88b54b02993107d4f222acc5d733c623f Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RISCV] Support RISC-V Profiles in -march option
This PR implements
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
preames wrote:
You
https://github.com/preames edited
https://github.com/llvm/llvm-project/pull/76357
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https://github.com/preames commented:
After this was discussed at the sync-up call today, I believe we're in
agreement on direction here. This is close to being ready and is just pending
some code cleanup.
https://github.com/llvm/llvm-project/pull/76357
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 8dc42f5c90ba369a145868f8c1a9a8cb3e988cb0 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH 1/3] [RISCV] Support RISC-V Profiles in -march option
This PR
@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 8dc42f5c90ba369a145868f8c1a9a8cb3e988cb0 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH 1/2] [RISCV] Support RISC-V Profiles in -march option
This PR
@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
@@ -36,6 +36,11 @@ struct RISCVSupportedExtension {
}
};
+struct RISCVProfile {
4vtomat wrote:
Very minor too, if you use std::pair, could you add the comments describing
what the fields represent?
https://github.com/llvm/llvm-project/pull/76357
@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
@@ -36,6 +36,11 @@ struct RISCVSupportedExtension {
}
};
+struct RISCVProfile {
preames wrote:
Very minor, but I believe you can use std::pair here instead.
https://github.com/llvm/llvm-project/pull/76357
___
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 8dc42f5c90ba369a145868f8c1a9a8cb3e988cb0 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RISCV] Support RISC-V Profiles in -march option
This PR implements
@@ -0,0 +1,189 @@
+//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -0,0 +1,189 @@
+//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -0,0 +1,189 @@
+//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -138,6 +150,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
/// initializeProperties().
RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
+ RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; }
topperc wrote:
@@ -0,0 +1,189 @@
+//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -138,6 +150,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
/// initializeProperties().
RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
+ RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; }
wangpc-pp
@@ -0,0 +1,189 @@
+//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From a54f47f8055e898b6452183663863f6df01e98e1 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH 1/2] [RFC][RISCV] Support RISC-V Profiles in -march option
This PR
@@ -840,6 +886,33 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
@@ -0,0 +1,189 @@
+//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -138,6 +150,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
/// initializeProperties().
RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
+ RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; }
topperc wrote:
wangpc-pp wrote:
Ping.
https://github.com/llvm/llvm-project/pull/76357
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>From a54f47f8055e898b6452183663863f6df01e98e1 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option
This PR
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From bd9b759d853d8196ae893a90442a3c3e7e5fa74d Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option
This PR
@@ -839,6 +860,33 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
@@ -839,6 +860,33 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
wangpc-pp wrote:
Ping.
https://github.com/llvm/llvm-project/pull/76357
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https://github.com/llvm/llvm-project/pull/76357
>From c7f2589692c4d310d4e61ebcbbceb3602b0ef227 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH 1/2] [RFC][RISCV] Support RISC-V Profiles in -march option
This PR
@@ -138,6 +150,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
/// initializeProperties().
RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
+ RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; }
wangpc-pp
@@ -138,6 +150,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
/// initializeProperties().
RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
+ RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; }
topperc wrote:
@@ -240,6 +245,17 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
};
// clang-format on
+static const RISCVProfile SupportedProfiles[] = {
+{"rvi20u32", "rv32i"},
+{"rvi20u64", "rv64i"},
+{"rva20u64", "rv64imafdc_zicsr"},
@@ -839,6 +860,36 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
@@ -0,0 +1,70 @@
+//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -96,12 +97,13 @@ class RISCVISAInfo {
private:
RISCVISAInfo(unsigned XLen)
- : XLen(XLen), FLen(0), MinVLen(0), MaxELen(0), MaxELenFp(0) {}
+ : XLen(XLen), FLen(0), MinVLen(0), MaxELen(0), MaxELenFp(0), Profile() {}
topperc wrote:
No need to
@@ -80,6 +80,7 @@ class RISCVISAInfo {
unsigned getMaxVLen() const { return 65536; }
unsigned getMaxELen() const { return MaxELen; }
unsigned getMaxELenFp() const { return MaxELenFp; }
+ std::string getProfile() const { return Profile; }
topperc wrote:
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/76357
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>From c7f2589692c4d310d4e61ebcbbceb3602b0ef227 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option
This PR
llvmbot wrote:
@llvm/pr-subscribers-llvm-support
@llvm/pr-subscribers-clang
@llvm/pr-subscribers-backend-risc-v
Author: Wang Pengcheng (wangpc-pp)
Changes
This PR implements the draft
https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36.
Currently, we replace specified
https://github.com/wangpc-pp ready_for_review
https://github.com/llvm/llvm-project/pull/76357
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