https://github.com/ChuanqiXu9 updated
https://github.com/llvm/llvm-project/pull/91914
>From 8ec79e4a7fdf0d75030e81d713ac9fe629ee97eb Mon Sep 17 00:00:00 2001
From: Chuanqi Xu
Date: Fri, 10 May 2024 15:36:31 +0800
Subject: [PATCH] [serialization] no transitive decl change
---
https://github.com/ChuanqiXu9 edited
https://github.com/llvm/llvm-project/pull/91914
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https://github.com/ChuanqiXu9 edited
https://github.com/llvm/llvm-project/pull/91914
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Author: Chuanqi Xu (ChuanqiXu9)
Changes
Following of https://github.com/llvm/llvm-project/pull/86912
Motivation Example
The motivation of the patch series is that, for a module interface unit `X`,
when the dependent modules of `X`
https://github.com/ChuanqiXu9 ready_for_review
https://github.com/llvm/llvm-project/pull/91914
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https://github.com/ChuanqiXu9 created
https://github.com/llvm/llvm-project/pull/91914
Following of https://github.com/llvm/llvm-project/pull/86912
Motivation Example
The motivation of the patch series is that, for a module interface unit `X`,
when the dependent modules of `X` changes,