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=?utf-8?q?Björn_Schäpers?= ,Mehdi Amini
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,Fabian Mora ,Kazushi Marukawa
,Jonas Devlieghere ,Jan Svoboda
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,Jan Svoboda ,Jan Svoboda
,Jan Svoboda ,Jan Svoboda
,Jan Svoboda
=?utf-8?q?Björn_Schäpers?= ,Mehdi Amini
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,Vitaly Buka ,Mehdi Amini
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,Fabian Mora ,Kazushi Marukawa
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=?utf-8?q?Björn_Schäpers?= ,Mehdi Amini
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=?utf-8?q?Björn_Schäpers?= ,Mehdi Amini
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,Jan Svoboda
=?utf-8?q?Björn_Schäpers?= ,Mehdi Amini
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,Shilei Tian ,"Kazushi (Jam) Marukawa"
,Fabian Mora ,Kazushi Marukawa
,Jonas Devlieghere ,Jan Svoboda
,Jan Svoboda ,Alex Brachet
,Jan Svoboda ,Jan Svoboda
,Jan Svoboda ,Jan Svoboda
,Jan Svoboda
=?utf-8?q?Björn_Schäpers?= ,Mehdi Amini
,Vitaly Buka ,Vitaly Buka
,Vitaly Buka ,Mehdi Amini
,Shilei Tian ,"Kazushi (Jam) Marukawa"
,Fabian Mora ,Kazushi Marukawa
,Jonas Devlieghere ,Jan Svoboda
,Jan Svoboda ,Alex Brachet
,Jan Svoboda ,Jan Svoboda
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@@ -1660,29 +1660,29 @@ let HasMasked = false, MaskedPolicyScheme = NonePolicy
in {
defm vmsbc : RVVIntMaskOutBuiltinSet;
}
-// 12.5. Vector Bitwise Logical Instructions
+// 11.5. Vector Bitwise Logical Instructions
let UnMaskedPolicyScheme = HasPassthruOperand in {
defm
@@ -2262,11 +2262,11 @@ defm vmfgt : RVVFloatingMaskOutBuiltinSet;
defm vmfge : RVVFloatingMaskOutBuiltinSet;
}
-// 14.14. Vector Floating-Point Classify Instruction
+// 13.14. Vector Floating-Point Classify Instruction
let Name = "vfclass_v", UnMaskedPolicyScheme =
@@ -1660,29 +1660,29 @@ let HasMasked = false, MaskedPolicyScheme = NonePolicy
in {
defm vmsbc : RVVIntMaskOutBuiltinSet;
}
-// 12.5. Vector Bitwise Logical Instructions
+// 11.5. Vector Bitwise Logical Instructions
let UnMaskedPolicyScheme = HasPassthruOperand in {
defm
https://github.com/dtcxzyw approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/65944
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>From 9bb817aa40dd9bc1bbb18b4cf4bc079145c8ecaa Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 03:58:02 +0800
Subject: [PATCH] [ValueTracking] Simplify uaddo pattern
---
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65910
>From 9bb817aa40dd9bc1bbb18b4cf4bc079145c8ecaa Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 03:58:02 +0800
Subject: [PATCH] [ValueTracking] Simplify uaddo pattern
---
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65905
>From f178af6d47ce6d982c6568ba6e0db517de124291 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 02:01:12 +0800
Subject: [PATCH] [InstSimplify] Simplify `icmp X & C1, X & C2` when `(C1 & C2)
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>From f178af6d47ce6d982c6568ba6e0db517de124291 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 02:01:12 +0800
Subject: [PATCH 1/2] [InstSimplify] Simplify `icmp X & C1, X & C2` when `(C1 &
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>From f178af6d47ce6d982c6568ba6e0db517de124291 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 02:01:12 +0800
Subject: [PATCH] [InstSimplify] Simplify `icmp X & C1, X & C2` when `(C1 & C2)
https://github.com/dtcxzyw edited
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>From 91af70acd72c8e889f542ba6dfff6401b89b2dc5 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 16:47:24 +0800
Subject: [PATCH 1/2] [InstCombine] Fix transforms of select (~a | c), a, b and
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65845
>From 91af70acd72c8e889f542ba6dfff6401b89b2dc5 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 16:47:24 +0800
Subject: [PATCH 1/2] [InstCombine] Fix transforms of select (~a | c), a, b and
https://github.com/dtcxzyw updated
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>From 91af70acd72c8e889f542ba6dfff6401b89b2dc5 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 16:47:24 +0800
Subject: [PATCH] [InstCombine] Fix transforms of select (~a | c), a, b and
select
https://github.com/dtcxzyw updated
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>From 91af70acd72c8e889f542ba6dfff6401b89b2dc5 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 16:47:24 +0800
Subject: [PATCH] [InstCombine] Fix transforms of select (~a | c), a, b and
select
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dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/65934
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https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/69252
This patch handles formatting of real and imaginary parts of complex lvalue.
Fixes #69218.
>From 8f0ebe5b5cfed069c8274c0761559d6595d4dea8 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/70232
[XiangShan](https://github.com/OpenXiangShan/XiangShan) is an open-source
high-performance RISC-V processor.
This PR adds the schedule model for XiangShan-NanHu, the 2nd Gen core of the
XiangShan processor
@@ -302,7 +302,7 @@ def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>;
} // Predicates = [HasStdExtF]
foreach Ext = FExts in {
- let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in {
+ let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32Addend] in {
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/70294
This PR adds the processor definition for XiangShan-NanHu, an open-source
high-performance RISC-V processor.
According to the official
[documentation](https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch/),
dtcxzyw wrote:
> Can you separate out the basic processor definition (using NoSchedModel), and
> a patch which adds the scheduling model? We can at least get the processor
> definition landed while we iterate on the scheduling related pieces.
>
> edit: For clarity, I'm requesting that the
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/70294
>From 1222b8bda348af58f4921a45d8cddca726875bb9 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Thu, 26 Oct 2023 13:47:39 +0800
Subject: [PATCH 1/2] [RISCV] Add processor definition for XiangShan-NanHu
dtcxzyw wrote:
Ping. @preames Any more comments?
https://github.com/llvm/llvm-project/pull/70294
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https://github.com/dtcxzyw approved this pull request.
LGTM. Thanks!
We can improve the compile time by adding `nneg` flag during the zext creation
(e.g., `cttz(zext(x)) -> zext nneg(cttz(x))`).
https://github.com/llvm/llvm-project/pull/71534
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dtcxzyw wrote:
Please also update existing uses in `lldb`.
Buildbot failure: https://lab.llvm.org/buildbot/#/builders/68/builds/63101
https://github.com/llvm/llvm-project/pull/71029
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>From a4e46c81c5235754bf7b4e0b3dd3ff8805b3e56d Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Thu, 26 Oct 2023 13:47:39 +0800
Subject: [PATCH 1/2] [RISCV] Add processor definition for XiangShan-NanHu
dtcxzyw wrote:
> LGTM in general, except one question: will zicbom and zicboz be in the final
> RTL?
You can find the full implementation of `zicbom` and `zicboz` here:
https://github.com/OpenXiangShan/XiangShan/commit/ca18a0b47b0e4089fd0dd1c085091cb90bf98f25.
cc @poemonsense
@@ -20,6 +20,17 @@
// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature"
"+zifencei"
// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu |
FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
dtcxzyw wrote:
Any more questions about XiangShan? If there is no question, I will merge this
PR tomorrow.
https://github.com/llvm/llvm-project/pull/70294
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dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/65934
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>From b34055dca42c23682bb9f0e9e022f17e9dbf2aca Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 28 Oct 2023 20:46:37 +0800
Subject: [PATCH] [RISCV] Add sched model for XiangShan-NanHu
Co-authored-by:
dtcxzyw wrote:
Rebased on top of #70241.
https://github.com/llvm/llvm-project/pull/70232
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dtcxzyw wrote:
To avoid backend regressions, I will merge this PR after #66793.
https://github.com/llvm/llvm-project/pull/66740
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>From 85f7911dfe0f1e9112881a9f503bcd68edfde580 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 19 Sep 2023 10:19:46 +0800
Subject: [PATCH 1/3] [InstCombine] Canonicalize `and(zext(A), B)` into `select
dtcxzyw wrote:
> You might want to check whether this also fixes #66740 and if so add a test.
Confirmed. I have added a pre-commit test for 66733 in
1a73a6b80b54cd23ee8380c6fa3304847e5cb5d1.
https://github.com/llvm/llvm-project/pull/66740
___
dtcxzyw wrote:
> You might want to check whether this also fixes #66740 and if so add a test.
Confirmed. I have added a pre-commit test for 66733 in
1a73a6b80b54cd23ee8380c6fa3304847e5cb5d1.
https://github.com/llvm/llvm-project/pull/66740
___
@@ -1964,18 +1964,78 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst
) {
break;
}
case Intrinsic::ptrmask: {
+KnownBits Known(DL.getPointerTypeSizeInBits(II->getType()));
+if (SimplifyDemandedInstructionBits(*II, Known))
+ return II;
+
+Value
@@ -8291,6 +8291,29 @@ static std::optional isImpliedCondICmps(const
ICmpInst *LHS,
if (L0 == R0 && match(L1, m_APInt(LC)) && match(R1, m_APInt(RC)))
return isImpliedCondCommonOperandWithConstants(LPred, *LC, RPred, *RC);
+ // L0 = R0 = L1 + R1, L0 >=u L1 implies R0
@@ -8291,6 +8291,29 @@ static std::optional isImpliedCondICmps(const
ICmpInst *LHS,
if (L0 == R0 && match(L1, m_APInt(LC)) && match(R1, m_APInt(RC)))
return isImpliedCondCommonOperandWithConstants(LPred, *LC, RPred, *RC);
+ // L0 = R0 = L1 + R1, L0 >=u L1 implies R0
https://github.com/dtcxzyw resolved
https://github.com/llvm/llvm-project/pull/65910
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>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/7] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
@@ -8291,6 +8291,29 @@ static std::optional isImpliedCondICmps(const
ICmpInst *LHS,
if (L0 == R0 && match(L1, m_APInt(LC)) && match(R1, m_APInt(RC)))
return isImpliedCondCommonOperandWithConstants(LPred, *LC, RPred, *RC);
+ // L0 = R0 = L1 + R1, L0 >=u L1 implies R0
https://github.com/dtcxzyw resolved
https://github.com/llvm/llvm-project/pull/65910
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>From 9bb817aa40dd9bc1bbb18b4cf4bc079145c8ecaa Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 03:58:02 +0800
Subject: [PATCH 1/2] [ValueTracking] Simplify uaddo pattern
---
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65910
>From 9bb817aa40dd9bc1bbb18b4cf4bc079145c8ecaa Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 03:58:02 +0800
Subject: [PATCH 1/2] [ValueTracking] Simplify uaddo pattern
---
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/7] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
https://github.com/dtcxzyw resolved
https://github.com/llvm/llvm-project/pull/65852
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>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/8] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
https://github.com/dtcxzyw resolved
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>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/8] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
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dtcxzyw wrote:
> LGTM, but please cleanup commits.
GitHub will squash commits into a single commit.
https://github.com/llvm/llvm-project/pull/65905
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>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/2] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
https://github.com/dtcxzyw resolved
https://github.com/llvm/llvm-project/pull/65852
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>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/3] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
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