ali hagigat wrote:
So devicetree.cb files are written by hand and the compilation
process does not use them? They are just some information for the
developers?
Of course not, that would be redundant. As Kerry pointed out, they
are very much part of the build process. You can also see this very
She, Kerry wrote:
I have made a little bit cleanup from the patches originally made
by Bao Zheng,
This sb800 code is derived from sb700 implementation.
Release this patch is NOT to confusing people, but make other
patches based on this implementation also works.
So this patch don’t
Hi Alec,
Neo The User wrote:
I have attached the somewhat working port as a patch
(ma785gm-us2h.patch)
Cool!
I hope the patch format is correct!
Well, I'd say no. It is impossible to review this patch because it
duplicates (nearly) all code for another board.
It would be very good if you
Hello! New patch :) Sorry about that, I have little to no experience with
subversion. Also I found out that the rebooting loop wasn't caused by the AHCI
SATA being off, but rather the console level for serial output was below 7 in
the coreboot config file... I found it very strange.
Anyway,
On Fri, Dec 31, 2010 at 07:57:34AM +0100, Stefan Reinauer wrote:
On 12/30/10 10:48 PM, Nils wrote:
- {0x,{0x, 0x}},
+ {0x,{0x, 0x}},
I don't think we should capitalize hexadecimal
Author: uwe
Date: Tue Jan 4 18:36:55 2011
New Revision: 6240
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6240
Log:
CK804: Cosmetic fixes, switch to u8 et al.
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
Acked-by: Uwe Hermann u...@hermann-uwe.de
Modified:
On Sat, Jan 1, 2011 at 1:38 PM, Darmawan Salihun
darmawan.sali...@gmail.com wrote:
On 1/2/11, Darmawan Salihun darmawan.sali...@gmail.com wrote:
Hi guys,
I'm looking for the support code for the IDE controller in CS5536
southbridge.
I checked-out Coreboot source code but only saw Flash
Author: uwe
Date: Tue Jan 4 20:51:33 2011
New Revision: 6241
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6241
Log:
MCP55: Cosmetic fixes, switch to u8 et al.
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
Acked-by: Uwe Hermann u...@hermann-uwe.de
Modified:
Thanks Crisit for getting back to me. I have indeed flashed it with flashrom
in Ubuntu. I will see what I can do about details of the northbridge.
On Mon, Jan 3, 2011 at 12:07 PM, Cristi Magherusan
cristi.magheru...@net.utcluj.ro wrote:
În Dum, Ianuarie 2, 2011 4:31, Brandon White a scris:
Hi Mark,
On 1/5/11, Marc Jones marcj...@gmail.com wrote:
On Sat, Jan 1, 2011 at 1:38 PM, Darmawan Salihun
darmawan.sali...@gmail.com wrote:
On 1/2/11, Darmawan Salihun darmawan.sali...@gmail.com wrote:
Hi guys,
I'm looking for the support code for the IDE controller in CS5536
southbridge.
* Peter Stuge pe...@stuge.se [110104 12:21]:
She, Kerry wrote:
Thanks! I think this is a nice addition. Maybe we should add a
Kconfig option to choose between cimx and non-cimx?
I think we should, once we actually hit a use case.
--
coreboot mailing list: coreboot@coreboot.org
Stefan Reinauer wrote:
Maybe we should add a Kconfig option to choose between cimx and
non-cimx?
I think we should, once we actually hit a use case.
Um? This is the case right here. I say add it now and get the patch
commited, then can remove in future if not used.
//Peter
--
coreboot
* Peter Stuge pe...@stuge.se [110104 22:18]:
Stefan Reinauer wrote:
Maybe we should add a Kconfig option to choose between cimx and
non-cimx?
I think we should, once we actually hit a use case.
Um? This is the case right here.
Oh? Which board? I thought the patch said for reference
Auf 04.01.2011 22:21, Stefan Reinauer schrieb:
* Peter Stuge pe...@stuge.se [110104 22:18]:
Stefan Reinauer wrote:
Maybe we should add a Kconfig option to choose between cimx and
non-cimx?
I think we should, once we actually hit a use case.
Um? This is the case
* Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net [110105 00:05]:
Still, having the code checked in is IMHO better than having it on the
list. If there are any CIMx integration issues later, we still have the
alternative code (and as a nice benefit, we can actually touch that code
Author: stepan
Date: Wed Jan 5 02:37:48 2011
New Revision: 6242
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6242
Log:
fix make clean
Signed-off-by: Stefan Reinauer ste...@coreboot.org
Acked-by: Stefan Reinauer ste...@coreboot.org
Modified:
trunk/Makefile
Modified:
Author: stepan
Date: Wed Jan 5 03:10:50 2011
New Revision: 6243
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6243
Log:
fix compilation of mconf on some systems.
Signed-off-by: Stefan Reinauer ste...@coreboot.org
Acked-by: Stefan Reinauer ste...@coreboot.org
Modified:
Author: stepan
Date: Wed Jan 5 03:27:53 2011
New Revision: 6244
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6244
Log:
move single options out of main menu and remove stray options
Signed-off-by: Stefan Reinauer ste...@coreboot.org
Acked-by: Stefan Reinauer ste...@coreboot.org
Author: stepan
Date: Wed Jan 5 03:40:53 2011
New Revision: 6245
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6245
Log:
uart_init is only used in romstage.
Signed-off-by: Stefan Reinauer ste...@coreboot.org
Acked-by: Stefan Reinauer ste...@coreboot.org
Modified:
I am looking for the data sheet and programming reference manual of a
super I/O chip by ITE, IT8703F.
I will be much appreciated if anybody can email it for me.
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
On Tue, Jan 4, 2011 at 10:43 PM, ali hagigat hagigat...@gmail.com wrote:
I am looking for the data sheet and programming reference manual of a
super I/O chip by ITE, IT8703F.
I will be much appreciated if anybody can email it for me.
Looks like google can't find it, you're going to have to
You can run superiotool to find out the logical device number (LDN) of
each device. That is the way if we don't have the datasheet.
Zheng
-Original Message-
From: coreboot-boun...@coreboot.org
[mailto:coreboot-boun...@coreboot.org]
On Behalf Of ali hagigat
Sent: Wednesday, January
Hi,
Answering the following questions from the FAQ, I have the following:
Board Vendor: Asus
Board Product Name: M2N-SLI Deluxe
CPU Model: AMD Athlon 64FX, Socket AM2
Northbridge: Nvidia nForce 570 SLI
Southbridge: Nvidia MCP55
Link to specifications:
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