A more portable solution to the "big toolchain" problem is to store
the toolchain outside the coreboot tree. Something like
$ util/crossgcc/buildgcc -D $HOME/.xgcc
Then add $HOME/.xgcc/bin to your PATH.
Regards,
Patrick
2016-11-13 21:34 GMT+01:00 Charlotte Plusplus
Hello
Here is the current status of my W520:
- native video init gives a garbled image (picture available upon request
lol). it may be due to the resolution of the screen being hardcoded
somewhere, or more likely me using the wrong information since the W520
uses 1980x1080
- non native video
Hi Federico,
You guys seem to have successfully built a usable coreboot image for
x220. Could you share its revision and config file? I have never built
such usable image till now.
Besides, is script file me_cleaner.py downloadable somewhere?
Persmule.
在 2016年11月12日 22:41, Federico Amedeo Izzo
True, but quality security is about planning for the theoretical and not
just closing the barn door after the animals have left already.
I am sure there are quite a lot of things that the public doesn't know
about, kept secret by the shady people and organizations of the world
On 11/13/2016
On 14.11.2016 00:06, taii...@gmx.com wrote:
> Shouldn't we be using sha256 or sha512? I am not a crypto expert but
> AFIAK couldn't sha1 collisions could be easily generated with the type
> of resources available to someone who would want to attack coreboot?
AFAIK, there is no known attack on
Shouldn't we be using sha256 or sha512? I am not a crypto expert but
AFIAK couldn't sha1 collisions could be easily generated with the type
of resources available to someone who would want to attack coreboot?
On 11/06/2016 07:15 PM, Iru Cai wrote:
buildgcc can verify the SHA1 sum of the
Hi Nico and Martin,
thank you for your clarifications and the pointer to the documentation.
On Sun, 13 Nov 2016 22:46:48 +0100
Nico Huber wrote:
> what do you mean by `actual config`? how did you set it? If you edi-
> ted .config manually, it's intended behavior. MAX_CPUS
Hi Daniel,
On 13.11.2016 19:22, Daniel Kulesz via coreboot wrote:
> Hi folks,
>
> after several hours of trial & error I finally realized why the quadcore
> CPU in my T500 does not get recognized: No matter what you set for
> MAX_CPUS in .config, it gets overwritten during the build with a value
Hello
With the cross compiling tool chain, coreboot takes 1G. If you are a bit
short on space, or if you want to save writes to your SSD, instead of
having multiple copies of the coreboot source folder, I have found out
overlayfs is very practical.
If you have done git clone in
Hi folks,
after several hours of trial & error I finally realized why the quadcore CPU in
my T500 does not get recognized: No matter what you set for MAX_CPUS in
.config, it gets overwritten during the build with a value coming from
src/mainboard/lenovo/t400
where the following is defined:
Hi,
You can use Bolton datasheets, should be same/similar.
http://support.amd.com/TechDocs/51192_Bolton_FCH_RRG.pdf
The said register access is forcing to use overriden EFUSE values, so I would
say you have to check how their are programmed. Maybe you are trying to enable
the EC without EC
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