Re: [coreboot] call on AMD to release src+specs+datasheets for ryzen

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 Hi Ron, On 03/03/17 23:26, ron minnich wrote: > We could target putting a meeting with AMD together at the Denver > meeting or the one in the fall. ron Yes, this is what I'm banking on. If coreboot can arrange that, and get AMD in its meetings

Re: [coreboot] Reminder: The maiing list vs forum poll closes in just under 24 hours.

Wasn't Martin suggesting to add the results to the poll anonymously, without revealing the originator's identity? Come on, guys, Google is a major contributor and benefactor of coreboot, give it some slack! ;) --vb On Fri, Mar 3, 2017 at 2:38 PM, wrote: > I would

Re: [coreboot] Reminder: The maiing list vs forum poll closes in just under 24 hours.

On 03/03/2017 05:38 PM, i1w5d7gf38...@tutanota.com wrote: I would also really prefer a non-google poll. Taiidan wrote "I also do not like contributing to machine learning or advertising databases." You wrote "If people want to just email me responses, I can fill them into the form on their

Re: [coreboot] call on AMD to release src+specs+datasheets for ryzen

On 03/03/2017 02:25 PM, Leah Rowe wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA256 Hi all, https://libreboot.org/amd-libre/ We call on coreboot to join us in our campaign to convince AMD to start cooperating with the libre hardware community again. Are there people in coreboot already

Re: [coreboot] call on AMD to release src+specs+datasheets for ryzen

So, first, I admire and agree with your enthusiasm for making this happen. I hope it works. That said, having gotten vendors to break open this kind of information, with a number of vendors a number of times, and having both failed and succeeded, my experience is that a broadcast call like this

Re: [coreboot] Reminder: The maiing list vs forum poll closes in just under 24 hours.

I would also really prefer a non-google poll. Taiidan wrote "I also do not like contributing to machine learning or advertising databases." You wrote "If people want to just email me responses, I can fill them into the form on their behalf." Thats exactly what he didnt want. He didnt want to

[coreboot] coreboot only takes 260 ms on Lenovo 430s!

Dear coreboot folks, Kamyl pushed the board status for the Lenovo 430s, and I am excited looking at the time stamps! Gone in 260 ms! Awesome. (RAM training results are cached.) ``` $ more lenovo/t430s/4.5-1105-gd55ea7b/2017-03-03T18_41_49Z/coreboot_timestamps.txt 21 entries total: 0:1st

Re: [coreboot] How to improve the boot time of the Asus KGPE-D16?

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 03/03/2017 04:14 PM, Paul Menzel via coreboot wrote: > Dear Daniel, > > > Am Freitag, den 03.03.2017, 10:52 +0100 schrieb Daniel Kulesz: > >>> I think most of the time is spent in RAM initialization. >>> >>>1. Do board owners with similar

Re: [coreboot] How to improve the boot time of the Asus KGPE-D16?

Dear Daniel, Am Freitag, den 03.03.2017, 10:52 +0100 schrieb Daniel Kulesz: > > I think most of the time is spent in RAM initialization. > > > >1. Do board owners with similar amount of memory (independent of the > > board) have similar numbers? > >2. What are the ways to improve

Re: [coreboot] Reminder: The maiing list vs forum poll closes in just under 24 hours.

Hey Talidan, If someone wants to suggest a different site for doing polls, I'd be glad to take a look, but I'm probably not going to change away from Google forms unless we find something comparable. It's easy to make the forms, easy to take the poll, and easy to collect, analyze, and view the

Re: [coreboot] Reminder: The maiing list vs forum poll closes in just under 24 hours.

I don't want to skew the poll by releasing the data before it closes. Martin On Fri, Mar 3, 2017 at 12:22 AM, Zoran Stojsavljevic < zoran.stojsavlje...@gmail.com> wrote: > Hello Martin, > > The current/up to date poll results would be also nice to have... I > guess, I am asking for too much,

[coreboot] call on AMD to release src+specs+datasheets for ryzen

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 Hi all, https://libreboot.org/amd-libre/ We call on coreboot to join us in our campaign to convince AMD to start cooperating with the libre hardware community again. Are there people in coreboot already doing this? - -- Leah Rowe Libreboot

Re: [coreboot] Some errors by compiling romstage (I am a newbie)

On Fri, Mar 3, 2017 at 11:23 AM, Maxim Gusev wrote: > Yes, Aaron. I tried to figure it all out. > Some option doesn't works correctly. But the compiler and the linker are > supporting these options. > There is a log of "readelf -e imd_cbmem.o": http://pastebin.com/G5y36uU4

Re: [coreboot] Some errors by compiling romstage (I am a newbie)

Yes, Aaron. I tried to figure it all out. Some option doesn't works correctly. But the compiler and the linker are supporting these options. There is a log of "readelf -e imd_cbmem.o": http://pastebin.com/G5y36uU4 I also have a warning: cannot find entry symbol start; defaulting to

[coreboot] PCI BAR attacks on SMM at RECon Brussels

Intel ATR presented "Baring the system: New vulnerabilities in SMM of coreboot and UEFI based systems" at RECon Brussels last month: https://recon.cx/2017/brussels/talks/baring_the_system.html The slides are online now:

[coreboot] Inteal Leafhill : Linux SATA driver fails when used with coreboot+grub

Hi Experts, I am trying to boot Linux 4.1 with coreboot and grub but SATA drive fails with error "ata1: SATA link down (SStatus 4 SControl 300)". It is interesting that GRUB2 can use the SATA drive without issue and able to load kernel from SATA disk. If I use same SATA Drive with Coreboot+UEFI

Re: [coreboot] Some errors by compiling romstage (I am a newbie)

On Fri, Mar 3, 2017 at 8:37 AM, Maxim Gusev wrote: > It doesn't work any case. > As I understood these options remove the unreferenced symbols, but I have > referenced symbols (the error is undefined reference). > The definition of the used functions is in the file that is

Re: [coreboot] coreboot+filo

when i see filo.elf with readelf -a : ELF Header: Magic: 7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00 Class: ELF32 Data: 2's complement, little endian Version: 1 (current) OS/ABI:

Re: [coreboot] Some errors by compiling romstage (I am a newbie)

On Fri, Mar 3, 2017 at 6:41 AM, Maxim Gusev wrote: > These options are supported. > But the option -fno-pie is not supported (Don’t produce a position > independent executable). > Is it the reason of the fault? I wouldn't think so. If you remove that option does it

Re: [coreboot] Reminder: The maiing list vs forum poll closes in just under 24 hours.

On 03/03/2017 01:45 AM, Martin Roth wrote: As brought up in the previous coreboot community meeting, the coreboot project is discussing the idea of switching from the mailing list to a forum. This idea did not originate with the coreboot leadership, but from a request by members of the

Re: [coreboot] How to improve the boot time of the Asus KGPE-D16?

Hi Paul, > > I think most of the time is spent in RAM initialization. > >1. Do board owners with similar amount of memory (independent of the > board) have similar numbers? >2. What are the ways to improve that? Is it possible? For example, can > the modules be probed in

[coreboot] coreboot+filo

Hi all, - i use this config: 582 CONFIG_PAYLOAD_FILO=y 589 CONFIG_FILO_MASTER=y 590 CONFIG_PAYLOAD_FILE="payloads/external/FILO/filo/build/filo.elf" 591 CONFIG_PAYLOAD_OPTIONS="" My logs: BS: BS_WRITE_TABLES times (us): entry 166670 run 767112 exit 0 POST: 0x7a CBFS: 'Master

Re: [coreboot] The ECC 2017 web page

It depends on the browser if it uses hardware accerlation but I am gonna fix that for you. I will add some idle js which stops the video if not focused. Best Regards Zaolin On 03/03/2017 06:11 AM, ron minnich wrote: > That one web page, while not even visible, eats up 25% of the cpu on > one