[coreboot] Re: PCIe Hotplug for Thunderbolt and U.2

Here is the patch: https://review.coreboot.org/c/coreboot/+/35946 -- Jeremy Soller System76 Engineering Manager jer...@system76.com On Wed, Oct 9, 2019, at 8:00 PM, Jeremy Soller wrote: > Thanks, I will probably have a patch sometime tomorrow. > > -- > Jeremy Soller > System76 >

[coreboot] Re: PCIe Hotplug for Thunderbolt and U.2

Thanks, I will probably have a patch sometime tomorrow. -- Jeremy Soller System76 Engineering Manager jer...@system76.com On Wed, Oct 9, 2019, at 4:43 PM, Aaron Durbin wrote: > > > On Wed, Oct 9, 2019 at 3:07 PM Jeremy Soller wrote: >> __ >> Will do. Any relevant emails I should CC

[coreboot] Re: PCIe Hotplug for Thunderbolt and U.2

On Wed, Oct 9, 2019 at 3:07 PM Jeremy Soller wrote: > Will do. Any relevant emails I should CC when I have something? > I'm not sure about Intel, but you can include mine, Duncan's, and Furquan's. Should be autocomplete in gerrit. > > -- > Jeremy Soller > System76 > Engineering Manager >

[coreboot] Re: PCIe Hotplug for Thunderbolt and U.2

Will do. Any relevant emails I should CC when I have something? -- Jeremy Soller System76 Engineering Manager jer...@system76.com On Wed, Oct 9, 2019, at 1:29 PM, Aaron Durbin wrote: > Please include intel and google on your patches because we'll be needing this > support in the near

[coreboot] Re: PCIe Hotplug for Thunderbolt and U.2

Please include intel and google on your patches because we'll be needing this support in the near future as well. The allocator limitations are known, and Kyosti and I have talked about improving things here. As for the children comment you need to reserve a sufficiently large mmio space and in

[coreboot] PCIe Hotplug for Thunderbolt and U.2

This is to continue the discussion from the coreboot leadership meeting. Thunderbolt devices are not correctly initialized by Coreboot such that the OS can boot without kernel parameters and allow for Thunderbolt hotplugging. Additional bus numbers and memory must be allocated. I will be

[coreboot] Re: SATA link 1 is not enabled

Hi all, I've found the sata1 is muxed with the eMMC through the GPIO86. By default, it's initialized to use the eMMC. Changing this the sata1 is detected flawlessly. Thanks! ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an