[coreboot] Re: IRQ routing: how to do the mainboard_picr_data/_intr_data structures?

2020-11-10 Thread Nico Huber
Hi Mike, On 10.11.20 19:22, Mike Banon wrote: > Thank you very much for your advice, dear Naresh, I will try matching > the UEFI routing. I wouldn't expect too much. If things are configurable in the chipset (they usually are these days) it's possible that coreboot configures them differently

[coreboot] Re: IRQ routing: how to do the mainboard_picr_data/_intr_data structures?

2020-11-10 Thread Mike Banon
Thank you very much for your advice, dear Naresh, I will try matching the UEFI routing. Dear Elyes, huge thanks to you for telling me about "getpir" utility - never heard about it before! > this old "getpir" utility may help you ;) > You may have to run: > coreboot/util$ git revert

[coreboot] Re: Deprecating spurious PCI bus master enabling (was Re: Planning the next coreboot release)

2020-11-10 Thread Angel Pons
Hi Werner, Ron, Nico, list, While it would be great to not have to implement Bus Master workarounds in coreboot, I guess it's sometimes unavoidable because of external constraints. I would much prefer to have the actual problem fixed instead (code assuming Bus Master is enabled by default), but

[coreboot] Re: Deprecating spurious PCI bus master enabling

2020-11-10 Thread Paul Menzel
Dear coreboot folks, Am 10.11.20 um 16:23 schrieb werner@siemens.com: We could introduce a Kconfig switch per driver and let the driver handle the bit. Everything else could be removed. This would make it easier to track the usages. It would be nice if we could agree on a naming scheme so

[coreboot] Re: Flashing coreboot and Intel Flash Descriptor Erase Issue

2020-11-10 Thread Balaji Sivakumar
Hi Naresh and David, I see that SPI BIOS_CTRL.LE bit is set. It can be set by either Coreboot or FSP. I guess it might be getting set by FSP. Can you add printk in file "src/soc/intel/denverton_ns/chip.c" at the line 46 before & after fsp_silicon_init to print bios control reg. This will help in

[coreboot] Re: Flashing coreboot and Intel Flash Descriptor Erase Issue

2020-11-10 Thread Naresh G. Solanki
Hi Balaji, I see that SPI BIOS_CTRL.LE bit is set. It can be set by either Coreboot or FSP. I guess it might be getting set by FSP. Can you add printk in file "src/soc/intel/denverton_ns/chip.c" at the line 46 before & after fsp_silicon_init to print bios control reg. This will help in

[coreboot] Re: Deprecating spurious PCI bus master enabling (was Re: Planning the next coreboot release)

2020-11-10 Thread werner....@siemens.com
We could introduce a Kconfig switch per driver and let the driver handle the bit. Everything else could be removed. This would make it easier to track the usages. It would be nice if we could agree on a naming scheme so that all switches are named similar which would make it easier to track the

[coreboot] Re: Deprecating spurious PCI bus master enabling (was Re: Planning the next coreboot release)

2020-11-10 Thread ron minnich
nice idea! On Tue, Nov 10, 2020 at 7:13 AM Nico Huber wrote: > > On 10.11.20 16:06, Nico Huber wrote: > > If anybody knows or discovers more cases where it needs to be enabled > > in advance by coreboot, please mention it here. > > We just discussed on IRC cases where unfixable OS drivers might

[coreboot] Re: Deprecating spurious PCI bus master enabling (was Re: Planning the next coreboot release)

2020-11-10 Thread Nico Huber
On 10.11.20 16:06, Nico Huber wrote: > If anybody knows or discovers more cases where it needs to be enabled > in advance by coreboot, please mention it here. We just discussed on IRC cases where unfixable OS drivers might need it. For such cases, it would probably be best to add individual

[coreboot] Deprecating spurious PCI bus master enabling (was Re: Planning the next coreboot release)

2020-11-10 Thread Nico Huber
Hi, On 04.11.20 23:21, Angel Pons wrote: > 3. Please take a look at the preliminary release notes in > Documentation/releases/coreboot-4.13-relnotes.md and add whatever > happened since 4.12 that is worth mentioning. If unsure, simply push a > change to Gerrit and have your fellow developers

[coreboot] Re: IRQ routing: how to do the mainboard_picr_data/_intr_data structures?

2020-11-10 Thread Naresh G. Solanki
Hi Mike, I see that IRQ routing that you set in Coreboot is different then that in UEFI bios. I recommend you first try to match them. Required data is already available in the dump you took. Also this link can be of help: https://gist.github.com/mcastelino/4acda7c2407f1c51e68f3f994d8ffc98 IRQ