Re: [coreboot] [Mohon Peak] Memtest86+

entry through the serial link in order to access to the memtest86+ menu... (Almost the same as in http://www.coreboot.org/pipermail/coreboot/2015-February/079173.html) Hope it helps. Regards, Patrick agrain Le 14/04/2015 16:22, Patrick Agrain a écrit : Hello, I try to perform some memory test

[coreboot] [Mohon Peak] Memtest86+

. After pressing 'ESC' and select '2', I'm not able to boot memtest86+, and fall back to the hard drive. Has anyone already faced this behavior. Thanks in advance. Best regards, Patrick Agrain -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [Solved][Mohon Peak] Console output on external UARTs behind PCIe

UART_FOR_CONSOLE at '0' for the first COM port and '1' for the second COM port. Hope it helps. Regards, Patrick Agrain PS: Kyösti, you told me about a possible patch for Seabios. Had you the opportunity to find it ? Le 17/03/2015 08:23, Patrick Agrain a écrit : Hello, Yesterday morning, I tried

Re: [coreboot] [Almost solved][Mohon Peak] Console output on external UARTs behind PCIe

with the OXPCIe board. Regards, Patrick On Fri, 2015-03-13 at 16:47 +0100, Patrick Agrain wrote: / Hello, // // One step further !! // // I succeed to get it working. // // Several modification has to be made. I will try (next week) to get them // in a readable form. // - in ./src/device

Re: [coreboot] [Almost solved][Mohon Peak] Console output on external UARTs behind PCIe

+ 0x1200 for the Startech board I have. BTW, I also included the patch covered by http://review.coreboot.org/#/c/8660/. Compiler does not complain anymore (and 'in fine' it works). Logs are now available from 'coreboot-... ramstage starting'. Thanks for your support. Regards, Patrick Agrain Le

Re: [coreboot] [Mohon Peak] Console output on external UARTs behind PCIe

)) void write8(volatile void *addr, uint8_t value) ^ cc1: all warnings being treated as errors make: *** [build/drivers/uart/uart8250mem.romstage.o] Error 1 Hope it helps. Best regards, Patrick On Wed, 2015-03-11 at 16:21 +0100, Patrick Agrain

Re: [coreboot] [Mohon Peak] Console output on external UARTs behind PCIe

on it. Regards, Patrick Le 06/03/2015 19:01, Marc Jones a écrit : Hi Patrick, You can look at the Oxford pcie card and 8250MEM drivers for reference: src/drivers/uart/oxpcie* src/drivers/uart/uart8250mem* Marc On Fri, Mar 6, 2015 at 9:37 AM Patrick Agrain patrick.agr...@alcatel-lucent.com

[coreboot] [Mohon Peak] Console output on external UARTs behind PCIe

? Thanks in advance. Best regards, Patrick Agrain -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [SOLVED] Read the Coreboot version in the .rom binary

Hi Patrick, Thanks for the tip and the related code snippet. It works like a charm. Best regards, Patrick Agrain Am 2015-01-28 15:39, schrieb Patrick Agrain: Is there a way to read the coreboot version (as a string or as binary chain) from inside the build coreboot.rom file. On x86, it's

[coreboot] Read the Coreboot version in the .rom binary

/sys/class/dmi/id/bios_version'. What is missing is the version of the new binary to compare them. Kind regards, Patrick Agrain -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [SOLVED] Internal Ethernet controller on Mohon Peak CRB failed to get activated

and ME_PATH in coreboot does the rest. Now, the Mohon Peak CRB boots with all internal GbE enabled and functionning. Thank to all. Kind regards, Patrick Agrain Le 05/01/2015 15:37, Alexander Couzens a écrit : -BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On Mon, 5 Jan 2015 13:49:05 +0100