Re: [coreboot] Out of MTRRs

2018-04-01 Thread Aaron Durbin via coreboot
On Sat, Mar 31, 2018 at 10:21 AM, Nico Huber wrote: > On 31.03.2018 17:31, Nico Huber wrote: >> >> On 23.03.2018 16:29, Jay Talbott wrote: >>> >>> Do you think they will resolve the issue that I am seeing? >> >> >> I don't know. As you top posted, I haven't looked at it yet. I'll

Re: [coreboot] Out of MTRRs

2018-03-31 Thread Nico Huber
On 31.03.2018 17:31, Nico Huber wrote: On 23.03.2018 16:29, Jay Talbott wrote: Do you think they will resolve the issue that I am seeing? I don't know. As you top posted, I haven't looked at it yet. I'll have a look. But it seems very likely that you'll have to fix something about your memory

Re: [coreboot] Out of MTRRs

2018-03-31 Thread Nico Huber
Hello Jay, On 23.03.2018 16:29, Jay Talbott wrote: What's the status for getting the patches merged that Aaron referenced below? I've just updated the first two. The last one is only a source optimi- zation that probably won't get merged (unless I find a better way to explain how it works).

Re: [coreboot] Out of MTRRs

2018-03-23 Thread Jay Talbott
aron Durbin [mailto:adur...@google.com] > Sent: Monday, March 19, 2018 10:22 AM > To: Jay Talbott > Cc: Coreboot > Subject: Re: [coreboot] Out of MTRRs > > On Mon, Mar 19, 2018 at 10:55 AM, Jay Talbott > <jaytalb...@sysproconsulting.com> wrote: > > See below… > > - Jay

Re: [coreboot] Out of MTRRs

2018-03-19 Thread Aaron Durbin via coreboot
On Mon, Mar 19, 2018 at 10:55 AM, Jay Talbott wrote: > See below… > - Jay > [Mon Mar 19 09:41:59.840 2018] MTRR Range: Start=79fff000 End=7a00 (Size 1000) [Mon Mar 19 09:41:59.840 2018] MTRR Range: Start=7a00 End=7a80 (Size 80) [Mon Mar 19

Re: [coreboot] Out of MTRRs

2018-03-17 Thread Aaron Durbin via coreboot
Please post the full logs so we can see the address space. The 'Unable to insert temporary MTRR range' log message is only for tempoarility mapping the SPI flash. However, it's impossible to debug w/o the full logs to see what your address space looks like. On Sat, Mar 17, 2018 at 12:28 PM, Jay

[coreboot] Out of MTRRs

2018-03-17 Thread Jay Talbott
I'm working on a coreboot solution for a SkyLake based board that uses SO-DIMMs. The plan is for two 8GB DIMMs, for a total of 16GB of RAM. But with two 8GB DIMMs installed, I get the following during the boot: Taking a reserved OS MTRR. Taking a reserved OS MTRR. Taking a reserved