Beware though that usually by default the I/O port 0x80 code aren't
routed to the PCI bus on any x86 platform that was released in maybe the
last maybe 10 years even if it still has PCI slots. The I/O port 0x80
writes often get decoded/routed to the LPC or eSPI bus on the platform
which is
I didn't have a post card, and ended up writing an early-boot serial byte
writer, to see the post codes via. After doing this they were quite useful.
Later I was forwarded to SerialICE which has already implemented such a
writer.
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coreboot mailing
As Ron said, they are very useful. A lot of initialization happens
before PCI is enabled. Bear in mind that the POST codes traditionally
are written to IO port 0x80 (not PCI MMIO), so they can be output from
firmware immediately after the CPU is let out of reset.
The old coreboot wiki has some
They are incredibly useful, which is why they are still there. That
first post-bist code has been there since the first code in 1999.
If you have jtag, it still helps. But many BMC also have ways to see
port 80 writes. You can see it before PCI is up.
On Mon, Jul 11, 2022 at 8:00 AM Pedro
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