Re: [coreboot] SMM save area in MSRs on newer intel CPUs

haswell and on has this. You can see it in the haswell code. We actually opted not to use it but for relocation so we could look at each cpu's save state from a single cpu to see who caused the smi, etc. On Sat, Oct 7, 2017 at 8:38 AM, ron minnich wrote: > can someone point

[coreboot] SMM save area in MSRs on newer intel CPUs

can someone point me at the documents that describe how this works? thanks ron -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot