Hey, I'm not sure if people pay much attention to these, but you can
safely ignore these issues. I'm not even seeing them show up as
issues inside coverity, so I'm not sure why they are presented here.
1) These issues are in the chromeec codebase, not the coreboot
codebase. We've marked them as
2016-08-09 11:23 GMT+02:00 :
> 421 defect(s), reported by Coverity Scan earlier, were marked fixed in the
> recent build analyzed by Coverity Scan.
I wish it was that simple.
Of those 421, maybe 10 are actually fixed, but the real reason for
this steep dive is that our
I'm curious about this part:
> *** CID 1349858: Memory - illegal accesses (OVERRUN)
> /src/soc/mediatek/mt8173/spi.c: 85 in mtk_spi_init()
> 79unsigned int speed_hz)
> 80 {
> 81 u32 div, sck_ticks, cs_ticks, reg_val;
> 82 /* mtk spi HW just support bus 0 */
> 83
** CID 1295489:(OVERRUN)
*** CID 1295489:(OVERRUN)
/src/mainboard/google/veyron_jerry/mainboard.c: 77 in configure_codec()
71 gpio_output(GPIO(2, B, 1), 1); /*
Hi all,
Am 16.11.2014 um 00:18 schrieb scan-ad...@coverity.com:
Please find the latest report on new defect(s) introduced to coreboot
found with Coverity Scan.
this automated report will now be copied to the mailing list. I run coverity on
our tree (in abuild default configuration) about
Am Samstag, den 27.09.2014, 15:28 -0700 schrieb scan-ad...@coverity.com:
Hi,
Please find the latest report on new defect(s) introduced to coreboot found
with Coverity Scan.
Defect(s) Reported-by: Coverity Scan
Showing 20 of 253 defect(s)
** CID 1229561: Bad bit shift operation
Am 28.09.2014 um 09:12 schrieb Paul Menzel:
Please find the latest report on new defect(s) introduced to coreboot found
with Coverity Scan.
Defect(s) Reported-by: Coverity Scan
Showing 20 of 253 defect(s)
Those many new reports are because the prior two builds didn't track our cross
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