On Friday, March 13, 2015 08:42:20 AM Paul Menzel wrote:
Am Freitag, den 13.03.2015, 00:05 -0500 schrieb Alexandru Gagniuc:
On Friday, March 13, 2015 12:42:38 AM ron minnich wrote:
On Thu, Mar 12, 2015 at 3:48 PM Paul Menzel wrote:
As this is an Intel device [1] and I am waiting for an
Paul,
Paul Menzel wrote:
I don’t think Google has understood how much power they have over
Intel with their Chromebook and Chromebox success.
It's inapppropriate to speak on behalf of others, please don't do that.
The facts are that neither you nor I know anything about what Google
might or
Hi all,
I put the mailing list under emergency moderation for a while because
things heated up quickly. This wasn't coordinated with anyone, so
please direct complaints about that at me.
All incoming emails (to this thread = all of them) in that period were
rejected with an explanation (I hope
eche...@free.fr wrote:
So we don't have the right to even ask or wonder why is this so secret?..
Everyone has the right to ask and wonder anything in the free world.
We are all curious to learn, but there are always better ways to learn,
and worse ways.
I think the engineering that Google puts
Dear Kevin,
Am Donnerstag, den 12.03.2015, 23:08 -0700 schrieb Kevin Paul Herbert:
Not sure how I missed this, unless util/abuild does not rebuild it.
native graphics is not selected by default. Next time change set #5957
[1] should be rebased on top to get it build tested.
Thanks,
Paul
On 11.03.2015 14:30, Stefan Tauner wrote:
This will be the last poll that evaluates specific features of the
logo. There may be another one to determine the final design.
I have selected a variety of fonts that I think are OK for a logo in
terms of thickness and playfulness. Not all of them
Dear coreboot folks,
thanks to (mainly) Kyösti’s awesome work, CBMEM console [1] is now
enabled by default in the master branch.
So, if you distribute coreboot based firmware and have not enabled these
two options yet, please publish new images from latest master and upload
the board status.
Am Donnerstag, den 12.03.2015, 05:55 -0700 schrieb Milton Krutt:
Thanks Paul.
so, software RAID is fine too?
What about hardware based ones?
Sorry, I have no idea if there are boards with a hardware RAID supported
by coreboot.
As you wrote small, I suggest the ASRock E350M1 [1] or the
Am Freitag, den 13.03.2015, 00:05 -0500 schrieb Alexandru Gagniuc:
On Friday, March 13, 2015 12:42:38 AM ron minnich wrote:
On Thu, Mar 12, 2015 at 3:48 PM Paul Menzel wrote:
As this is an Intel device [1] and I am waiting for an AMD based laptop,
I’d say no. ;-)
I'm not sure AMD
Not sure how I missed this, unless util/abuild does not rebuild it.
I can fix this.
Kevin
On Mar 12, 2015, at 21:48, Alexandru Gagniuc mr.nuke...@gmail.com wrote:
On Thursday, March 12, 2015 10:35:23 PM Mono wrote:
is it just me? trying to build coreboot for a X60 motherboard or a
+1!
(count me in)
Florentin
- Mail d'origine -
De: ron minnich rminn...@gmail.com
À: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net,
coreboot@coreboot.org
Envoyé: Thu, 12 Mar 2015 21:14:28 +0100 (CET)
Objet: Re: [coreboot] coreboot meeting this summer!
I think it would be
On Fri, Mar 13, 2015 at 12:42 AM Paul Menzel
paulepan...@users.sourceforge.net wrote:
Sadly, I don’t think Google has understood how much power they have over
Intel with their Chromebook and Chromebox success. RAM initialization is
for example still a BLOB and, instead of getting Intel to
On Fri, Mar 13, 2015 at 4:41 AM eche...@free.fr wrote:
Sorry Ron,
What is his crime?
Thought crime?..
Florentin
The problem with people making comments like this:
Sadly, I don’t think Google has understood how much power they have over
Intel with their Chromebook and Chromebox
On Fri, 13 Mar 2015 14:36:35 +0100
Stefan Tauner stefan.tau...@alumni.tuwien.ac.at wrote:
On Fri, 13 Mar 2015 08:37:49 +0100
Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net wrote:
On 11.03.2015 14:30, Stefan Tauner wrote:
This will be the last poll that evaluates specific
Sorry Ron,
What is his crime?
Thought crime?..
Florentin
- Mail d'origine -
De: ron minnich rminn...@gmail.com
À: Paul Menzel paulepan...@users.sourceforge.net, Alexandru Gagniuc
mr.nuke...@gmail.com
Cc: Anthony Martin al...@pbrane.org, coreboot@coreboot.org
Envoyé: Fri, 13 Mar 2015
On Fri, Mar 13, 2015 at 5:27 AM eche...@free.fr wrote:
Ok Ron,
We all recognise your efforts and don't deny that the question of the
binary blobs is a very complex and politicaly hot one..
But (and I speak here from a STRICTLY personal point of view) it is the
fashion you chose to lecture
Ok Ron,
We all recognise your efforts and don't deny that the question of the binary
blobs is a very complex and politicaly hot one..
But (and I speak here from a STRICTLY personal point of view) it is the fashion
you chose to lecture Paul than I found not very nice..
I sense a trace of elitism
Hello,
One step further !!
I succeed to get it working.
Several modification has to be made. I will try (next week) to get them
in a readable form.
- in ./src/device/pci_early.c:pci_early_bridge_init() :
-- secondary = 1 for Mohon Peak.
-- remove udelay() in PCI_VENDOR_ID reading (that's the
Guys, I don't speak for Ron but I don't find his comment (apparently
sent in a emailed to a few folks but then made public (sic!)) elitist,
it was a matter of fact question.
I have been with Chromebook program pretty much from the very
beginning, and I can tell you that the public availability of
How about making flashrom available for Bay Trail architecture?
13 mar 2015 kl. 14:36 skrev Stefan Tauner stefan.tau...@alumni.tuwien.ac.at:
On Fri, 13 Mar 2015 08:37:49 +0100
Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net wrote:
On 11.03.2015 14:30, Stefan Tauner wrote:
This
On Fri, 13 Mar 2015 08:37:49 +0100
Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net wrote:
On 11.03.2015 14:30, Stefan Tauner wrote:
This will be the last poll that evaluates specific features of the
logo. There may be another one to determine the final design.
I have selected a
Hi,
Please find the latest report on new defect(s) introduced to coreboot found
with Coverity Scan.
3 new defect(s) introduced to coreboot found with Coverity Scan.
42 defect(s), reported by Coverity Scan earlier, were marked fixed in the
recent build analyzed by Coverity Scan.
New defect(s)
Thanks! I’ll keep that in mind when I next submit patches.
Kevin
On Mar 13, 2015, at 12:19 AM, Paul Menzel paulepan...@users.sourceforge.net
wrote:
Dear Kevin,
Am Donnerstag, den 12.03.2015, 23:08 -0700 schrieb Kevin Paul Herbert:
Not sure how I missed this, unless util/abuild does
On Thursday, March 12, 2015 07:29:00 PM Peter Stuge wrote:
Stefan Reinauer wrote:
I would like to organize a coreboot project meeting in San Jose,
California this summer.
..
If you are interested in joining this summer, if you have ideas, or
concerns, please contact me
Chances are
If one wanted to use a relatively recent Opteron or Xeon, are there any
motherboards known to work with coreboot?
I looked at the wiki and there's a lot of red unknowns there, the lone
exception being the ASUS KFSN4-DRE, which is Socket F/DDR2. And it
appears to no longer be available other
So we don't have the right to even ask or wonder why is this so secret?..
Call me a moron but I don't find it justified to keep the memory initialisation
code a very close secret.
And I will not change my mind until I am presented with real arguments. (And
this will never happen because this
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