[coreboot] How to assign a fixed resource to PCI BAR?

Hi, coreboot folks, I'm trying to assign a fixed resource to a specific PCI BAR, does any know how to do it? Also is there a switch to change the PCI enumeration order? for example, PCI devices enumerate from high device number to low device number? Thanks. -- coreboot mailing list:

Re: [coreboot] force https on review.coreboot.org

On 04/16/2015 08:57 AM, Alexander Couzens wrote: Hi, review isn't forcing https. Can we please do this? Otherwise stealing cookies is posibble. Review supports https. There is atm an CACert based certificate and CaCert isn't included in the default root keychain. Thus a normal user will shown

Re: [coreboot] force https on review.coreboot.org

2015-04-16 15:57 GMT+02:00 Alexander Couzens lyn...@fe80.eu: than let us change to StartSSL or someother SSL authority. I'll ask CNNIC. I heard they have good offers. PPS. Please write a +1 if you're supporting this opinion. Please don't. Patrick -- Google Germany GmbH, ABC-Str. 19, 20354

[coreboot] Gerrit access rules

Hi, after deliberation to encourage positive feedback, gerrit rules are changed so that 'reviewers' can now give +2 Code-Reviews. Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Graham

[coreboot] force https on review.coreboot.org

Hi, review isn't forcing https. Can we please do this? Otherwise stealing cookies is posibble. Review supports https. There is atm an CACert based certificate and CaCert isn't included in the default root keychain. Thus a normal user will shown a big fat warning, not to connect to

Re: [coreboot] fsp_baytrail default SMM_TSEG_SIZE value

On Wed, Apr 15, 2015 at 5:06 AM, David Imhoff dimhoff_de...@xs4all.nl wrote: Hi, Running the current Coreboot on a Minnowboard Max I ran into the following error when booting: Unable to install SMM permanent handler. Error loading SMM handlers. This results in the boot hanging at

[coreboot] cbmem console broken on Intel hardware since ec5e5e0

Greetings! When building upstream master tonight, discovered that cbmem console output is broken for Intel hardware (testing on google/panther). With some help on IRC from kmalkki, was able to determine the culprit is commit ec5e5e0 (New mechanism to define SRAM/memory map with automatic

Re: [coreboot] force https on review.coreboot.org

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi Alexander, On 16/04/15 14:57, Alexander Couzens wrote: Hi, review isn't forcing https. Can we please do this? Otherwise stealing cookies is posibble. Review supports https. There is atm an CACert based certificate and CaCert isn't included

Re: [coreboot] force https on review.coreboot.org

On Fri, Apr 17, 2015 at 2:01 AM, The Gluglug i...@gluglug.org.uk wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi Alexander, On 16/04/15 14:57, Alexander Couzens wrote: Hi, review isn't forcing https. Can we please do this? Otherwise stealing cookies is posibble. Review supports