Re: [coreboot] Extracting MRC training data

you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. This footer makes absolutely no sense when you address a mailing list. I wouldn't be surprised if you get less answers because of it. Best regards, Angel P

Re: [coreboot] Porting Qotom Q355G4 SBC (similar to Librem 13)

. Please check this before doing anything else to avoid wasting time. Best regards, Angel Pons -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] coreboot on Thinkpad T420 : Ctrl and Fn key swap

eny stated should be possible with the old image though. Regards, Angel Pons -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] coreboot on Thinkpad T420 : Ctrl and Fn key swap

rogrammer is possible. The laptop warning does not apply to all laptops (depends on how hardware is connected), and the T420 is safe to use in this sense. If you happen to flash a non-booting coreboot, you can use an external programmer. I am not sure whether the flash chip is powered, though. Regard

Re: [coreboot] Intel G41 - Asrock G41M-GS: no coreboot screen output from Intel GPU on VGA

Hello h42, I am porting a G41M-S3, which is pretty much the same thing but with DDR3 (heck, the component layout is pretty much the same too). I have the same issue (libgfxinit fails) but I have not done anything about it yet. Best regards, Angel Pons -- coreboot mailing list: coreboot

Re: [coreboot] T450S + Coreboot

ject is good for all. Ron, those are a true wise man's words. Thank you for reminding what we should strive for. I feel that is much more productive than arguing. I realized how pleasing it is to contribute code and feel something is being produced. Best regards, Angel Pons [1]: https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Questions about using coreboot riscv with qemu

Hello, > qemu-system-x86_64 -bios build/coreboot.rom -serial stdio Note that this command is for x86_64, which is not the architecture the author of this thread is referring to (RISC-V) Regards, Angel Pons -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mail

Re: [coreboot] Will a KCMA-D8 boot without the 8pin EPSV12 cable if you are using a 35W CPU?

Hello, First and foremost, I don't have a KCMA-D8. I believe the power traces are different, so the CPU VRM feeds only through the EPS12V connector. However, if your PicoPSU is large enough, I guess a EPS12V cable can be attached to it. Regards, Angel Pons P.S. I forgot to "Reply t

Re: [coreboot] Matrix instead (or additionally to) IRC

rather popular among those who only connect for support), but requires messaging an OP should someone need to be manually voiced. Regards, Angel Pons Pons -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] There are ASMB5's on fleabay right now for $30/ea (firmware storage module required for OpenBMC on the KGPE-D16/KCMA-D8)

Hello, Is it me, or is that thing a SPI flash chip on a PCB plus a few transistors? It seems like copying the PCB design is rather doable, or am I missing something? Regards, Angel Pons -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Will a KCMA-D8 boot without the 8pin EPSV12 cable if you are using a 35W CPU?

- http://www.jonnyguru.com/modules.php?name=NDReviews=Story=207 PicoPSU roundup (from 2010, somewhat old, but still interesting) Best regards, Angel Pons Pons -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Supported Motherboards

automatically. The wiki, however, is not. It is read-only as well since documentation is being moved to [2]. Best regards, Angel Pons Pons [1]: https://review.coreboot.org/c/coreboot/+/29402 [2]: https://doc.coreboot.org -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Supported Motherboards

Hello nekoboi, On Wed, Nov 7, 2018 at 7:53 PM Kinky Nekoboi wrote: > > Did not know it that there is a replacement for FSP. > > Was it Reserve-engineered? i just recently build a working rom for my > W520 with the afford to reduce as much blobs as possible. shined me and > stuff. > > is there

Re: [coreboot] Status Thinkpad T410

don't have any Thinkpad (let alone a T410). And I have too many computers already, so buying one isn't a sane option for me. Best regards, Angel Pons Pons -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] T430s prop BIOS Image

On Sat, Nov 10, 2018, 17:47 Alberto Bursi Afaik there are companies that will ship you a pre-programmed SPI chip for > most devices, for like 20 euros. > > I used this one in the past http://www.bios-chip24.com/en_US but there > are others too. > > This is of course just as secure as getting it

Re: [coreboot] Source code for "Intel Firmware"

ates the start of the IFD. Regards, Angel Pons > -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] flashrom and 256 MiB S256FL256S

Hello Ron, I do not have such chip, but I am aware there are three patches regarding the S25FL256S: [1] Best regards, Angel Pons [1]: https://review.coreboot.org/q/topic:"s25fl256s; -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Will a KCMA-D8 boot without the 8pin EPSV12 cable if you are using a 35W CPU?

may not boot because the CPU is not powered. If it works, swapping the ATX PSU with a PicoPSU should work too. Best regards, Angel Pons Pons -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] Re: Coreboot build process with gcc 8.1

red in this failure several times and even with the > latest 4.9 release. Shouldn't I be able to build at least this latest > release using unmodified crossgcc or am I missing something else? Definitely, you should be able to, but you need crossgcc-i386 to build coreboot for x86 platforms. than

[coreboot] Re: No GRUB/Graphical boot-output on x4x chipset series with PCIe GPU

t; How i build coreboot: > make menuconfig, choose mainboard-vendor, mainboard model, press esc and > confirm saving. Then build. > If nothing else is changed, this should definitely be bootable. Best regards, Angel Pons ___ coreboot mailin

[coreboot] Re: No GRUB/Graphical boot-output on x4x chipset series with PCIe GPU

Hello, On Fri, Jan 18, 2019, 23:51 akjuxr3--- via coreboot Thanks for the fast answer. > For example i have the issue with an Asrock G41 mainboard. > Right, I have the Asrock G41M-S3 here. I have tried 2 different AMD cards (3000 series and 7000 series) and 3 > different Nvidia cards (old 6000

[coreboot] Re: Configuration for Thinkpad T530

are never a good reference! Best regards, Angel Pons > ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Configuration for Thinkpad T530

> functionality could be degraded without one > The xHCI controller firmware and the Lenovo g505s you mention are AMD-specific stuff, which does not apply to the Intel chipset on the Thinkpad T530 (it should work out-of-the-box). Best regards, Angel Pons > ___

Re: [coreboot] Asus KGPE-D16 non-working S3 suspend with Qubes 4

at is why timings must be cached to flash for S3 to work). Does AMD have anything special to retrain memory yet still preserve RAM data to allow suspend, or am I missing something here? Best regards, Angel Pons > -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mail

Re: [coreboot] coreboot for Advantech SOM-4461

Hello, On Tue, Dec 18, 2018 at 9:27 AM junaid saleem wrote: > > Hello , > > I have been trying to port coreboot on advantech SOM 4461, with the following > specifications. > > Processor: Intel ® Atom N270 > Chipset : Intel 945GSE/ ICH7M > Memory: DDR2 (2GB) AFAIK, these chips are supported,

Re: [coreboot] Asus Chromebox Panther: no HW RNG?

conds). I'm assuming the /dev/random > driver is not seeing enough actiivity otherwise. > I have observed the same behavior on Debian Sid, I would have to smash my keyboard a few times to generate enough entropy. I don't see anything similar with Arch Linux. Maybe it has to do with distro-

Re: [coreboot] GSOC submission

ry so do various other > OpenPOWER machines. > Do you refer to only the last point (qemu POWER9) or the whole quoted text? Timothy Pearson expressed interest in getting coreboot on POWER9, and gave a few reasons: - Speed: coreboot will be faster - DDR4: coreboot devs can see how DDR4 bringup

Re: [coreboot] Asus KGPE-D16 with latest coreboot errors with Unsupported Hardware on Qubes 4 install missing IOMMU?

t; been too quick to catch so far but mentions "PCI" and "IRQ". One of the options you selected has the word "experimental" on its name. I would suspect it may cause issues. Regards, Angel Pons -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] coreboot & Absolute "Computrace"

has specific code for Computrace, in which case replacing the ME firmware with a clean copy (either use a compatible ME firmware or run me_cleaner on the original one) should work. Regards, Angel Pons Pons -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Coreboot for Apollolake

, which is more error-prone). Best regards, Angel Pons Pons [1]: https://review.coreboot.org/c/coreboot/+/28382 [2]: https://www.flashrom.org/Flashrom (I do not know about Chromium flashrom's capabilities) -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo

Re: [coreboot] coreboot for Advantech SOM-4461

arding updated documents, somebody with that board would have to check what still applies and what does not. Best regards, Angel Pons > -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] Re: Help with devicetree.cb

nsole to get debug logs from (harder to get one on laptops). With that being said, porting this laptop is a daunting task. I would strongly suggest picking up something else to begin with. I started with a Sandy Bridge desktop mainboard, which are much easier to work with. Best re

[coreboot] Re: Reading the T530 BIOS chips

hip. To connect this resistor, you can use a spare flash chip clip without a programmer. Best regards, Angel Pons > ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Microcode in ROM is not loaded with X60s

Hello, I was recently made aware of a change in coreboot's gerrit which may address this issue: https://review.coreboot.org/c/coreboot/+/31600 Best regards, Angel Pons Pons ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send

[coreboot] Re: Coding style and automatic code formatting

e code will not always look the way you think it > should look. Now that I see this, I fully agree. I'd rather see code that does things properly instead. I can't see how bikeshedding about code style is ever going to be productive. Best regards, A

[coreboot] Re: Coding style and automatic code formatting

e on one code style, yes. > Nico > > [1] https://review.coreboot.org/c/coreboot/+/31651 Do note this is my personal, uneducated opinion on the matter. Best regards, Angel Pons ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: p8h61-m pro gfx no init sandybridge

t to work properly. This can be changed on any SNB/IVB board as well. I hope the libgfxinit patches that fix this issue get merged soon, but for now this workaround will have to do. Best regards, Angel Pons > ___ coreboot mailing list -- coreboot

[coreboot] Re: if your G505S does NOT have a discrete GPU (= LA-A092P board), please test this coreboot build

Hello, On Sat, Feb 16, 2019, 14:49 Mike Banon https://github.com/informer2016/shared_devfiles/blob/master/coreboot.rom How can one build a coreboot.rom like this one with the patches you mentioned? Best regards, Angel Pons ___ coreboot mailing list

[coreboot] Re: Caby lake support

Hello, On Wed, Feb 20, 2019, 11:23 Mayuri Tendulkar Is there support for Intel Cabylake chipset in latest coreboot? > Kaby Lake? Yes. > ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Intel Braswell uploads

-le...@coreboot.org There are mail addresses on MAINTAINERS. I CC'd this message to the maintainer for braswell so that they can reply to it. Best regards, Angel Pons ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Early kernel Panic linux 4.19 on ASUS KGPE-D16

Hello, Have you tried bisecting coreboot/linux versions? It would help know where the problem is, and fix it accordingly. Microcode updates should not be a problem, so please leave them enabled for now. Best regards, Angel Pons ___ coreboot mailing

[coreboot] Re: AM1I-A and other 16h Jaguar boards cant have a working IOMMU

uld appreciate if you would please refrain from posting baseless speculations on this mailing list. I believe you have been asked to not do so on earlier occasions, so it should not come to you as a surprise. I would not want unfounded guesses to damage this list's credibility, and I believe others wo

[coreboot] Re: Can't build (for g505s) with crossgcc-x64 toolchain, builds fine with crossgcc-i386

in was built with a multilib patch, which means it could build 32bit and 64bit binaries. However, when upgrading to GCC8, that multilib patch was not updated (thus removed), hence the error you get. Regards, Angel Pons > ___ coreboot mailing list -- corebo

[coreboot] Re: p8h61-m_pro PS/2

when using SeaBIOS because of that. I checked devicetree and the mappings look correct from the ioport dump > and superio dump, so unsure of why the coreboot init would cause this > problem, but the solution seems to be "let the payload handle it" &g

[coreboot] Re: Atom C2000 processor FSP 1.0 initialization process fail if read SMBus0 before.

Hello, If the board you have is not exactly the Intel Mohonpeak RVP, using the RVP code as-is on your board is bound to fail, and can even cause damage (shortcircuits on GPIO pins). Regards, Angel Pons On Thu, Jul 11, 2019, 21:56 Martin Roth wrote: > I'd check the smbus base address ri

[coreboot] Re: Booting Legacy + UEFI disks: SeaBIOS / tianocore as secondary payload?

pace usage is printed out at the end of the build process :) Cheers, > Rafael > Best regards, Angel Pons > ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Mainboard porting assistance

Hi Benjamin, On Mon, Sep 2, 2019 at 1:31 PM Patrick Georgi via coreboot wrote: > > On Mon, Sep 02, 2019 at 02:50:15PM +1000, Benjamin Doron wrote: > > c) The fans spin up to high and then it stays that way. It does nothing > > else. The display is dark too. > The display is approximately the

[coreboot] Re: Commit message in Coreboot

Hi Himanshu, On Sat, Sep 7, 2019, 11:53 himanshu sahdev wrote: > Hi, > > I have seen some patches on gerrit, found "BUG=b:#bug_no." in the commit > message. > > example: CB:35233 > As far as I recall, these BUG=b:# lines refer to a private

[coreboot] Re: Mainboard porting assistance

Hi Benjamin, Yes, the link was moved there the other day. Best regards, Angel On Wed, Sep 18, 2019, 12:34 Benjamin Doron wrote: > Angel, the link you sent is unavailable now, but is the gist of it that I > attempt to commit and Gerrit automatically puts it into review? > > Also, would this

[coreboot] Re: supported hardware

Hello, On Mon, Sep 16, 2019 at 12:56 PM Michal Zygowski wrote: > > On 14.09.2019 17:16, Андрей Карелин wrote: > > Hello > > > Hi, > > First of all thank you for your great work, I mean coreboot, it's > > really cool > > > > I have mainboad Supermicro X11SSM-F rev 1.01, which almost the same as >

[coreboot] Re: Trying to check potential compatibility of intel server board

Hi, I have ported three boards with the cougarpoint H61 PCH, so I hope I can help you out. On Sun, Sep 29, 2019, 19:58 Lance Zhao wrote: > https://github.com/IntelFsp/FSP that shall have all the current platform > that FSP can supported, > > Matt B 于2019年9月29日周日 上午10:52写道： > >> Hello, >> >>

[coreboot] Re: Mainboard porting assistance

Hi Benjamin, Skylake chips do not have any EHCI (USB 2.0) controllers in hardware, so using EHCI for coreboot debug is not possible. Best regards, Angel On Mon, Sep 30, 2019, 16:14 Benjamin Doron wrote: > I've been using the SPI flash console log, but thanks for the suggestion. > Could I do

[coreboot] Re: Looking for INTEL board compatible with Coreboot

ith most, if not all supported boards. However, some boards restrict internal flashing (flashing from within the board itself), so you might need an external programmer. > Thanks Best regards, Angel Pons ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Comment on story about bootloader security?

Hi Seth, On Mon, Dec 9, 2019, 19:02 Seth Rosenblatt wrote: > I wasn't able to find the security@ alias, otherwise would've emailed > y'all there. I didn't hear back before publication but happy to make any > corrections if needed. I'm also willing to include a statement from > Coreboot if you

[coreboot] Re: Enable non-NVME devices in M.2 slot?

Hi Rafael, On Sat, Dec 7, 2019, 07:47 Rafael Send wrote: > Hi, > I know a couple folks here are active on Thinkpads.com / familiar with the > X210 port by Matthew. > > The stock BIOS doesn't appear to support non-NVME devices in the M.2 slot; > I'm attempting to get a Sunix UPD2018 card working

[coreboot] Re: Graphics Initialization

und in the PCH datasheet. > Regards, > Michał > > -- > Michał Żygowski > Firmware Engineerhttp://3mdeb.com | @3mdeb_com > > Best regards, Angel Pons > ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Still need assistance porting to ASUS P8Z77-M

tRFCmin : 160.000 ns > tWTRmin : 7.500 ns > tRTPmin : 7.500 ns > tFAWmin : 30.000 ns > channel[0] rankmap = 0xf > SPD probe channel1, slot0 > SPD probe channel1, slot1 > SPD probe chann

[coreboot] Re: Still need assistance porting to ASUS P8Z77-M

debugging than post codes. > Thanks for your help > Keith > ___ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org Best regards, Angel Pons ___ co

[coreboot] Re: Need suggestions for SPI flash programmer, setting up to begin P8Z77-M port

able. > [1] https://review.coreboot.org/c/flashrom/+/38578 > [2] https://www.velleman.eu/products/view/?id=435578 > ___ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org Best regards, Angel Pons ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Asus P2B-LS board status upload after C environment bootblock conversion

Hi, On Sun, Jan 12, 2020 at 1:25 AM Paul Menzel wrote: > > Dear Keith, > > Am 11.01.20 um 06:35 schrieb Keith Hui: > > > As I am still chasing how to enable SCSI termination on the board, > > Due to the conversion, please always write if that worked with romcc, > that means, a regression with C

[coreboot] Re: Coreboot + ASUS P5K-E???

Hi Aaron, Mike, On Mon, Jan 13, 2020 at 9:34 AM Mike Banon wrote: > > On Mon, Jan 13, 2020 at 11:10 AM Aaron Garza wrote: > > > > Does Coreboot work on every motherboard or does it have to be certain > > motherboards/PCs? > > > > I have an old Intel Core 2 Quad and an ASUS P5K-E motherboard

[coreboot] Re: "Delete change" Gerrit feature does more harm than good

_ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org Best regards, Angel Pons ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Mainboard porting assistance

Hi Benjamin, On Sat, Jan 4, 2020, 01:57 Benjamin Doron wrote: > Hi again, > I had the display working with Kabylake's VBT but without my laptop's > dedicated graphics card. I've since been working on that. > Is this laptop using Nvidia Optimus? If so, the displays are only connected to the

[coreboot] Re: About autoport in coreboot source tree

mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org Regards, Angel Pons ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: How to get a working snapshot of coreboot, submodules, seabios... everything for T440p?

s too bloated and it's hard to see what differs from defaults (what the defconfig contains). Best regards, Angel Pons PS: I've omitted the unnecessary quoted text from this reply. If context is needed, it can be found in previous messages. ___

[coreboot] Re: About support for my netbook

coreboot-le...@coreboot.org > > ___ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org Best regards, Angel Pons ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: How to get a working snapshot of coreboot, submodules, seabios... everything for T440p?

; Please use "make savedefconfig" with your settings. The full config is > too bloated and it's hard to see what differs from defaults (what the > defconfig contains). > > Best regards, > > Angel Pons > > PS: I've omitted the unnecessary quote

[coreboot] Re: How to get a working snapshot of coreboot, submodules, seabios... everything for T440p?

___ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org Best regards, Angel Pons ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Difference between GA-B75M-D3V and GA-B75M-D3H?

f this file: https://review.coreboot.org/c/coreboot/+/32708/16/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c > Kind regards, > > Paul > > [1]: https://review.coreboot.org/c/coreboot/+/32708 > ___ >

[coreboot] Re: beginner's despair ;) coreboot update via internal fails

Hi, On Thu, May 7, 2020 at 7:13 PM Nico Huber wrote: > > Hi, > > On 07.05.20 18:11, Felix Held wrote: > > I'd say that flashrom only verifying the section it writes by default > > would be less surprising behavior than the current behavior. > > we'd need a distinction between reliable and

[coreboot] Re: About support for my netbook

Hi Piotr, On Mon, May 11, 2020 at 4:02 PM Piotr Król wrote: > > On 3/13/20 11:23 AM, Angel Pons wrote: > > Hi, > > > > On Thu, Mar 12, 2020 at 11:07 AM Michal Zygowski > > wrote: > >> > >> Hi, > >> > >> it may also be a Ced

[coreboot] Re: Need PCI(e) vs PNP resource allocation help

Hi, On Thu, Mar 19, 2020 at 9:52 AM Nico Huber wrote: > > Hi Keith, > > On 18.03.20 23:55, Keith Hui wrote: > > These are the devicetree.cb entries: > > > > device pnp 2e.b on # HWM, LED > > io 0x60 = 0x290 # HWM address > > drq 0xe4 = 0xf9 # GP50,52,55 > > drq 0xf0 = 0x3e # Enable all fan

[coreboot] Re: Hiccups bringing ACPI support to p3b-f

Hi all, On Sat, May 16, 2020 at 2:23 AM Keith Hui wrote: > > Hi Nico, > > I tried a few things. Looks like Linux kernel activated a couple PCI > quirks and claimed the ACPI and SMBus port ranges on top of what we > already reported. Seems to be the source of the conflict. > I have to omit the

[coreboot] Re: How to debug open-source AGESA with serial console?

Hi list, On Thu, Oct 15, 2020 at 5:48 PM Clay Daniels wrote: > > Paul, you are probably way ahead of this, but I found something pre-AGESA > from 2003 that says: > > "Unlike minicomputer systems, the IBM PC was not designed to use a serial > console. This has two consequences. > > Firstly,

[coreboot] Re: FW: P8H61-m LX2 coreboot?

Hi Matej, On Sun, Oct 4, 2020 at 7:37 AM Matej Voľanský wrote: > > Hello, > I have P8H61-m LX2 in my desktop right now. I want to switch from Win10 to > Arch Linux and thought about also switching to coreboot. Unfortunately, I > can’t find this MBO in your board status. There’s P8H61-m LX, LX3

[coreboot] Re: kabylake RVP7 coreboot pcie/sata issue

.cb > > 3. gpio.h (SATAXPCIE1 detect) It would be nice to see which changes are needed. This would be very easy if the code were public, e.g.: upstream or on review. > Thanks a lot for your help on any of these issue. > > John > __

[coreboot] Naming convention of register update functions

Dear mailing list, I've been asked in https://review.coreboot.org/42134 to please start a discussion on the mailing list about the naming convention of the functions I've added in said patch. I decided to use `unset_and_set` because that's what libgfxinit uses. In coreboot, we already have

[coreboot] Re: Proper way to obtain mrc.bin for thinkpad t440p?

Hi all, That coreboot fork does not automate the process of obtaining mrc.bin at all. Instead, it contains a disassembled/decompiled version of MRC and uses that instead. I would not recommend using that fork because it's outdated. On coreboot master, there's https://review.coreboot.org/43559

[coreboot] Re: Question about PR

Hi, On Thu, Sep 17, 2020 at 2:50 PM Michal Zygowski wrote: > > Hi, > > Please check out also this guide: > https://www.coreboot.org/Git#Pushing_changes > > you need to tell git where to push: `HEAD:refs/for/master`. It seems the > guide on https://doc.coreboot.org/tutorial/part2.html is missing

[coreboot] Re: Extended IvyBridge CPU configuration

Hi Lars, list, On Wed, Jul 15, 2020 at 5:41 PM Lars Hochstetter wrote: > > Update: I tried the https://review.coreboot.org/c/coreboot/+/42547/ on > my T430 (i7-3840QM, Debian Buster 4.19.0-9-amd64) using coreboot v4.12 + > SeaBIOS as base. > > I used s-tui to track the CPU frequency. > > Without

[coreboot] Re: Lenovo R500

Hi list, On Thu, Jun 18, 2020 at 9:18 AM Mike Banon wrote: > > It's a bit not obvious, but by searching at > ./coreboot/src/mainboard/lenovo$ find . -type f -print0 | xargs -0 > grep -n "R500" - I could see that R500 is a variant of Thinkpad > T400: i.e. " ./t400/Kconfig.name:10:config

[coreboot] Re: request simple information

Hi Marco, On Wed, Jul 15, 2020 at 6:25 PM Marco Franchi Moretti wrote: > > Thanks all coreboot core team for support and innovation, privacy and > free technology. I have a technician question. I have Onda OBook 11 > Plus, Intel Cherry Trail Z8300 64bit Quad Core and Intel Graphics. I > can ask

[coreboot] Re: Call for testing: Weird behavior of the EC on Thinkpad X230s

ye have a chance to > access your own Thinkpad X230s? > > Regards, > Persmule > ___ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org Best regards, Angel Pons

[coreboot] Re: Call for testing: Weird behavior of the EC on Thinkpad X230s

Hi Persmule, On Thu, Jul 16, 2020 at 5:02 PM Persmule wrote: > > Hi Angel Pons, > > ‐‐‐ Original Message ‐‐‐ > On Thursday, July 16, 2020 2:47 PM, Angel Pons wrote: > > I suspect that reusing the H8 EC code for the xx30 series Thinkpads is > > a source of

[coreboot] Re: Call for testing: Weird behavior of the EC on Thinkpad X230s

Hi Persmule, On Thu, Jul 16, 2020 at 5:17 PM Persmule wrote: > > Hi Angel Pons, > > It seems that we may copy ec/lenovo/h8 to ec/lenovo/mec16xx ( or separate > directory for different chips ) to start dedicated support to them, since > though they are different, their behav

[coreboot] Re: How to choose my ‘‘mainboard vendor’’ for Sony laptops?

Hi there, Currently, no Sony laptops are supported. So, there isn't any option to build coreboot for your laptop. If you *really* want to have coreboot on it, you could try porting (adding coreboot support for) this laptop. However, you *need* to be able to flash externally (something to flash a

[coreboot] Re: will my machine support coreboot ?

Hello, On Thu, Jul 30, 2020 at 1:53 PM Jonathan Neuschäfer wrote: > > On Tue, Jul 28, 2020 at 07:54:33PM +0530, Nihar Khuntia wrote: > > Hi Developers, > > > > my laptop has hardwares details as attached in this email. will it support > > coreboot ? > > At present time, no. As you can see in

[coreboot] Re: Supporting a new board

Hi, On Tue, Jan 12, 2021 at 11:24 AM Alif Ilhan wrote: > > Thank you. I will make sure it will not happen. But can anyone tell me where > can I find MRC.bin from pineview? Which chromebook specifically? Pineview Chromebooks did not use coreboot, so there's no MRC.bin to use with coreboot. In

[coreboot] Re: "Fixing" `1 << 31` (technically undefined behavior with known implementation-specific results)

Hi list, Since register fields usually have more than one bit, I prefer to always use explicit shifts for consistency. The one case where I prefer the BIT() macro is to reduce the amount of nested braces when testing for individual bits in a mask. GCC encourages adding unnecessary braces for

[coreboot] Re: Is HP ProLiant DL360e Gen8 supported in Coreboot?

Hi, On Mon, Nov 9, 2020 at 6:42 PM wrote: > > Hello! I'm trying to find if my hardware supports Coreboot. I found 1 table > which is retired, second that is probably not retired and then current > documentation that doesn't seem to say as much. So, sorry if I missed it. > Will Coreboot work

[coreboot] Re: Deprecating spurious PCI bus master enabling (was Re: Planning the next coreboot release)

Hi Werner, Ron, Nico, list, While it would be great to not have to implement Bus Master workarounds in coreboot, I guess it's sometimes unavoidable because of external constraints. I would much prefer to have the actual problem fixed instead (code assuming Bus Master is enabled by default), but

[coreboot] Re: Including a video BIOS

Hi Andy, Naresh, On Wed, Nov 11, 2020 at 5:10 PM Andy Pont wrote: > > Naresh wrote… > > Looking at kconfig, the mainboard should select MAINBOARD_HAS_LIBGFXINIT. > For example see "grep -rsn MAINBOARD_HAS_LIBGFXINIT src/" > > I haven't used this, so not sure what else might be needed. > > In

[coreboot] Re: Planning the next coreboot release

Hi again, About a week ago, I announced our plans to do a new coreboot release, which is scheduled to take place next Wednesday, November 18. This means we're currently at the "~1 week prior to release" point of our release checklist (at https://doc.coreboot.org/releases/checklist.html). To this

[coreboot] Announcing coreboot 4.13

orms beyond the next release, please ensure that the platforms are fixed to conform to the expectations of resource allocation. Best regards, Angel Pons OpenPGP_0x53C88CBFBC4F65F3.asc Description: application/pgp-keys OpenPGP_signature Description: OpenP

[coreboot] Re: Memory initialisation error

Hi, On Wed, Nov 18, 2020 at 10:00 AM Andy Pont wrote: > > Naresh wrote… > > Don't know how to recover SPD from UEFI but Try to read memory part number > written on chip and provide that. Look for SPD file with that name if it's > already present in coreboot. > > The schematics for the platform

[coreboot] Re: Memory initialisation error

Hi Andy On Wed, Nov 18, 2020 at 1:22 PM Andy Pont wrote: > > Angel wrote... > > I can’t match what is printed on the top of the Micron devices (two lines of > text “0JE75” and “D9ZFW”) to any part numbers on Micron’s website. Is it some > kind of encoded version of the part number or is it

[coreboot] Re: Planning the next coreboot release

Hello again, Given that there's still some activity going on regarding deprecations on the release notes, the release may be delayed one or two more days to let things settle down, but no more. I look into having the release done this week, but I'd also like to proceed without rushing as it's my

[coreboot] Re: Information about "HP-Compaq 8200 Elite SFF"

Hi Dario, On Sun, Nov 15, 2020 at 5:42 PM wrote: > > Hi guys > Thanks a lot for the great work on coreboot. > > I'm looking for install coreboot on my "HP-Compaq 8200 Elite SFF", so > I was happy to found your site: > https://doc.coreboot.org/mainboard/hp/compaq_8200_sff.html > > In this

[coreboot] Re: [RFC] Replace strapping entries in coreboot table

Hi list, On Wed, Oct 28, 2020 at 10:17 PM Julius Werner wrote: > Okay, fair enough. Angel commented on the CL that this email thread > needs to get resolved before the patch can land, so I wanted to try to > help resolve it. No, I never said that. I merely pointed out that discussion was taking

[coreboot] Planning the next coreboot release

ease notes in Documentation/releases/coreboot-4.13-relnotes.md and add whatever happened since 4.12 that is worth mentioning. If unsure, simply push a change to Gerrit and have your fellow developers discuss it. Thanks, Angel Pons ___ coreboot mailing list -

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