On Thu, Jan 17, 2008 at 01:24:38AM +0100, Carl-Daniel Hailfinger wrote:
Please be aware that the M57SLI may read the reset vector and other
really early stuff at 33 MHz, thereby causing read errors
(sometimes single bit shifts) which are really hard to find.
English translation:
SST25VF016B
On Thu, Jan 17, 2008 at 01:40:07PM +0100, Florentin Demetrescu wrote:
+ /* FIXME : really dirty! It seems that the IO addr range for the SPI IF.
+ HAS to be set into the 0xb0 or 0xb4 reg which conflicts strongly with
+ mcp55_lpc_enable_childrens_resources() */
+ pci_write_config32(dev,
On Fri, Jan 18, 2008 at 04:08:58PM +0100, [EMAIL PROTECTED] wrote:
-See http://snapshots.linuxbios.org/
+See http://tracker.coreboot.org/
snapshots in the tracker?
-unsigned long write_linuxbios_table(
+unsigned long write_coreboot_table(
Really?
- /* Create cmos
On Sat, Jan 19, 2008 at 09:09:03AM -0500, Tom Sylla wrote:
Of course, you can access MSRs on those devices before VSA is
loaded.
It would be really awesome to support the bus natively.
//Peter
--
coreboot mailing list
coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
On Sat, Jan 19, 2008 at 10:50:26AM -0500, [EMAIL PROTECTED] wrote:
So people that are working on v3 should still put that in the email
subject line so it doesn't cause confusion, correct?
Just like before, yes. Often it is kind of clear from the
context/content though, v2 and v3 have different
On Sat, Jan 19, 2008 at 08:03:50PM +0100, Uwe Hermann wrote:
Properly cleanup null.o and builtin.o upon 'make clean'.
Signed-off-by: Uwe Hermann [EMAIL PROTECTED]
Acked-by: Peter Stuge [EMAIL PROTECTED]
Index: Makefile
Hi,
On Sun, Jan 20, 2008 at 10:31:23PM +0100, Carl-Daniel Hailfinger wrote:
New plan:
Scratch all special LAR member stuff and simply add a normal file
called foo or placeholder with the nocompress: parameter to the
LAR. No new code needed, gives us almost everything we need right
now.
On Mon, Jan 21, 2008 at 04:42:04PM +0100, Uwe Hermann wrote:
See patch.
We keep forgetting to update all the sources of information, let's
drop some and only use one location where we document stuff
Ack.
(mostly wiki).
Not so sure.
I would prefer to have these docs in the tarball as
On Tue, Jan 22, 2008 at 04:19:11PM +0100, Carl-Daniel Hailfinger wrote:
I am thinking of something like this:
id=pci,somevendorname,somedevicename;
Makes sense if the coreboot code itself does not have to perform
any string parsing.
Small thing; I would prefer something else than a comma
On Tue, Jan 22, 2008 at 10:29:17AM +0100, [EMAIL PROTECTED] wrote:
I own a VIA EPIA EN15000 Motherboard
..
Is there a chance to get my board working ?
Some, if you have time to hack a bit.
Can anybody tell me what to do ?
Corey Osgood has posted a C7/CN700 patch to the list. It has been
On Tue, Jan 22, 2008 at 09:43:35PM +0100, Patrick Georgi wrote:
This patch adds a new record type for lbtable to provide information
about a serial port. If a port is defined in the board configuration,
add it to lbtable.
Signed-off-by: Patrick Georgi [EMAIL PROTECTED]
Acked-by: Peter Stuge
and chip entry for Spansion S25FL016A.
Reading seems to work reliably, writing not so much.
Signed-off-by: Peter Stuge [EMAIL PROTECTED]
Index: util/flashrom/flash.h
===
--- util/flashrom/flash.h (revision 3073)
+++ util/flashrom
The Call for Projects has been released.
http://www.linuxtag.org/2008/de/community/projects/cfpro.html
http://www.linuxtag.org/2008/en/community/projects/cfpro/call-for-projects.html
Applications must be in before February 21st.
I think we did OK last year, but if we do a bit more careful
On Fri, Jan 25, 2008 at 03:43:02PM +0100, Uwe Hermann wrote:
Personally, I'm not convinced we want to do tarball releases at
all, not sure it's worth the hassle. Definately not real releases
as in flashrom 0.4.5 or so,
These are very good for distributions. Not all distributions can deal
with
On Fri, Jan 25, 2008 at 10:44:38AM -0700, Jordan Crouse wrote:
I agree with all of this. We should switch to complete Config.lbs
for v2.
Also, the reason why I haven't submitted my patch is that
buildtarget is still broken for -fno-stack-protector (as per a
previous email), and I figured
On Sat, Jan 26, 2008 at 08:20:06AM +, Brendan Trotter wrote:
Basically, I want to implement code that complies with some sort of
Coreboot Specification and know that my code will work for all
(past, present and future) versions of Coreboot
It would be great if you would help create this.
Hi Danny,
On Sat, Jan 26, 2008 at 07:00:43PM -0500, Danny Piccirillo wrote:
Can random people donate money or hardware to coreboot? I'd love to
see a page on the wiki with instructions for people who would like
to.
This has come up before. When someone wants to donate hardware it's
good to
Hi Andreas,
On Sun, Jan 27, 2008 at 05:32:20AM +0100, Andreas Rudin wrote:
Am I right, that the only mainboard listed as supported by
coreboot, I still can get as new is the Gigabyte GA-M57SLI-S4 Board
with Socket AM2?
That's possible, I'm not sure about other AM2 boards.
My company is now
On Sat, Jan 26, 2008 at 09:07:23PM -0800, ron minnich wrote:
OK, VSA is running fine. BUT, after VSA runs, memory at 0x1000 is
ZERO'd. This is Bad, as this is where stage2 lives!
Can you confirm it is not zero before calling do_vsmbios() and zero
immediately after returning? That would indicate
On Sun, Jan 27, 2008 at 06:32:42AM +0100, Peter Stuge wrote:
Hi Andreas,
So, this wasn't really meant for the list. I only saw the list
address in To just as I hit send. No problem for me, but;
Should we really have a Mail-Followup-To header?
I believe it is what makes my mutt reply command
On Fri, Jan 25, 2008 at 07:08:58PM -0500, [EMAIL PROTECTED] wrote:
I am certainly interested in exhibiting coreboot. Anyone else?
I would love to help but traveling to Germany is out of the
question. Let me know if there is anything I can do to help
remotely.
Last year we had an idea about
On Sun, Jan 27, 2008 at 03:15:58AM +0100, Stefan Reinauer wrote:
#define ID is well tested but I'm not adamant in any way. You're
basically asking for less information in source and more at run
time. I like more info at run time but I still think it would be
nice to have IDs in the code.
On Sun, Jan 27, 2008 at 01:51:15PM +0100, Rudolf Marek wrote:
The logical device for SPI flash has only bit 1 for enable/disable.
Bit 0 is reserved.
I guess bit 3 also reserved?
Question is how to solve that? Would help to ommit 2e.9 off/on in
Config.lb? And enable this manually in sio_init
On Sun, Jan 27, 2008 at 03:01:50PM +0100, Patrick Georgi wrote:
When that works, we could provide a .jar file with a demo bios
image or something like that, for instant experimentation as java
applet.
Indeed neat! Do you know if jpc is actively worked on?
//Peter
--
coreboot mailing list
On Sun, Jan 27, 2008 at 07:59:33AM -0500, [EMAIL PROTECTED] wrote:
I am pretty fluent in php / html.
Going back to the competition, we will need a database, an entry form
and some way to pick the winner. I think a web based entry form is a
good idea.
//Peter
--
coreboot mailing list
On Sun, Jan 27, 2008 at 02:53:49PM +0100, Carl-Daniel Hailfinger wrote:
Should we really have a Mail-Followup-To header?
The Mail-Followup-To header appears in all mails from you to the
list, in all mails from Ward and in one fourth of the mails from
Stefan. The mails I got from you which
On Sun, Jan 27, 2008 at 05:12:34PM +0100, Stefan Reinauer wrote:
Most enhanced stuff (HPET) has to be passed via ACPI anyways.
Which lead to this dream of mine to have one central data structure
+1
which can be used to create acpi, pirq, mptable, dmi/smbios, ...
structures from the same
Hi Andreas,
On Sun, Jan 27, 2008 at 08:04:53PM +0100, Andreas Rudin wrote:
I have icedove (thunderbird) as mail client, where I have the
possibility to answer a mail with the button reply and reply to
all.
Oh! Then have a look at this:
On Sun, Jan 27, 2008 at 11:32:26PM +0100, Torsten Duwe wrote:
My question is this. I'd like to secure machines against the
people that should work with them [1].
Ah. Classic DRM.
DRM does not work.
I think this is because it tries to provide an all-encompassing
solution to a generic
On Sun, Jan 27, 2008 at 08:55:24PM +0100, Andreas Rudin wrote:
It's a fantastic thing you all are doing here and I hope, after
having done our first steps with coreboot, we will be able to make
some contribution as well.
Thank you, and welcome to the project! :)
//Peter
--
coreboot mailing
On Sun, Jan 27, 2008 at 07:08:10PM -0500, Corey Osgood wrote:
Question to others, do we want this to be grabbed by externals,
Isn't utils already externaled into both v2 and v3?
Afaik, just the individual utilities are, so we can pick and choose
which utilities we want with each repo.
On Mon, Jan 28, 2008 at 11:16:01AM +0100, Torsten Duwe wrote:
Without knowing exactly what you are trying to protect against ( I
know -- the user ) we cannot tell.
What I think Torsten is getting at is that it would be beneficial to
think about what user actions you want the system to be able
Hi again Brendan,
On Mon, Jan 28, 2008 at 08:04:28PM +, Brendan Trotter wrote:
On 1/27/08, Peter Stuge [EMAIL PROTECTED] wrote:
What, specifically, do you need?
For long-term viability, I need something (e.g. a formal
specification) that gives guarantees on the (past, present
On Sun, Feb 03, 2008 at 08:19:26PM -0500, Corey Osgood wrote:
Thanks, this should be very helpful. I'll take your changes into
account, and have a fresh patch sometime soon.
I'll test on my CN10k board as well when you do.
Watching the super bowl atm
Heh, had an eye on it while doing some
On Mon, Feb 04, 2008 at 02:52:05PM +0100, Carl-Daniel Hailfinger wrote:
I have a really tough challenge for you: I need a global variable
in v3.
Why?
//Peter
--
coreboot mailing list
coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
On Mon, Feb 04, 2008 at 05:22:24PM +0100, Stefan Reinauer wrote:
e.g. %esp 0x is where globals live.
Let's just put the buffer to a well known address.
Yes, simple is good.
//Peter
--
coreboot mailing list
coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
On Mon, Feb 04, 2008 at 04:06:44PM +0530, Lalitha V.N. wrote:
in a file name called jan-14 and tried to flash(write) the content
in the filename jan-14 on to a new flashrom SST49LF004B..
This should work.
***Then we removed the original Bios chip and inserted the new
flashrom SST49LF004B
On Tue, Feb 05, 2008 at 10:51:39AM -0500, [EMAIL PROTECTED] wrote:
So I found this in the ICH4 datasheet:
The LAN controller enters Wake on LAN mode after reset if the Wake
on LAN bit in the EEPROM is set *(which it is)*.
You could try changing this bit in the EEPROM before running
coreboot
On Wed, Feb 06, 2008 at 03:40:15PM +, Chris Lingard wrote:
Switch down
bash-3.2# ./flashrom-m gigabyte:m57sli -V
..
probe_spi: id1 0x7f9d, id2 0x7e
Probing for PMC unknown SPI chip, 0 KB
WARNING: size: 0 - 4096 (page size)
RDID returned 7f 9d 7e.
probe_spi: id1 0x7f9d, id2 0x7e
On Tue, Feb 05, 2008 at 09:47:18PM +0100, Luc Verhaegen wrote:
Flashrom: Add board enable for VIA EPIA SP.
Signed-off-by: Luc Verhaegen [EMAIL PROTECTED]
If it works: (I can't test)
Acked-by: Peter Stuge [EMAIL PROTECTED]
Index: board_enable.c
On Tue, Feb 05, 2008 at 02:20:06PM -0700, Myles Watson wrote:
The correct place for Config.lb files is in the coreboot-v2 tree.
So obvious when you write it out. :)
The next patch would add Config-lab.lb files for each architecture
supported by buildrom.
I like it!
//Peter
--
coreboot
On Wed, Feb 06, 2008 at 06:20:51PM +, Chris Lingard wrote:
Switch up
Pm25LV020 found at physical address 0xfffc.
Flash part is Pm25LV020 (256 KB).
Switch down
Pm25LV040 found at physical address 0xfff8.
Flash part is Pm25LV040 (512 KB).
Difference at least, but something is
v3/util/lar $ make
printf BUILD LAR\n
BUILD LAR
mkdir -p /util/lar
mkdir: cannot create directory `/util': Permission denied
make: *** [lardir] Error 1
v3/util/lar $ obj=. make
printf BUILD LAR\n
BUILD LAR
mkdir -p ./util/lar
v3/util/lar $
wtf? I just want to make lar, that
On Wed, Feb 06, 2008 at 10:52:02PM -0800, ron minnich wrote:
I just booted linux. First v3 boot on real hardware.
Congratulations!
There are still problems. Linux is quite busy as revealed by a POST
card but we don't seem to get interrupts.
They are probably related.
Wow, this was a long
On Fri, Feb 08, 2008 at 08:55:50AM -0500, [EMAIL PROTECTED] wrote:
1: set up csr memory/io base in the nic. ami bios uses 0xff7ff000
for mem base, and 0xdc01 as io base, these values should work to
test with.
I think your right Corey, we need to setup space for for the CSR
register
On Fri, Feb 08, 2008 at 02:37:19PM -0700, Jordan Crouse wrote:
[openvsa] Fix for 64 bit hosts, and add in our good friend
-fno-stack-protector
Signed-off-by: Jordan Crouse [EMAIL PROTECTED]
Acked-by: Peter Stuge [EMAIL PROTECTED]
Index: openvsa/common.mk
On Sat, Feb 09, 2008 at 09:40:54AM -0800, ron minnich wrote:
On Feb 9, 2008 9:27 AM, Stefan Reinauer [EMAIL PROTECTED] wrote:
We need to add all information from irq_tables.c to the mainboard
DTS and read it from there. The mainboard DTS is our central data
structure.
Was just about to
On Sat, Feb 09, 2008 at 01:59:47AM +0100, Carl-Daniel Hailfinger wrote:
On 09.02.2008 01:31, ron minnich wrote:
so far it looks like I have some pretty great speakers,
*Please* tape all the talks, preferably with good audio.
+1
//Peter
--
coreboot mailing list
coreboot@coreboot.org
On Sat, Feb 09, 2008 at 09:34:55PM +, Brendan Trotter wrote:
Sorry for the interruption, but...
All input is valuable!
On 2/9/08, ron minnich [EMAIL PROTECTED] wrote:
There's only 2 things coreboot is missing. The first is an inbuilt
update payload from device utility
This is basically
On Sat, Feb 09, 2008 at 09:55:32PM +0100, [EMAIL PROTECTED] wrote:
Author: kilgour
Date: 2008-02-09 21:55:31 +0100 (Sat, 09 Feb 2008)
New Revision: 2
Removed:
trunk/openvsa/sysmgr/delme
trunk/openvsa/sysmgr/delme.c
Log:
remove files accidentally added to SVN
Should the
On Sat, Feb 09, 2008 at 09:35:49PM -0800, ron minnich wrote:
It should be simple enough to get the type if struct property had
a struct node *node; member so that the owner-parent node could
be reached from within the property foreach loop.
it's there.
Hmm. How?
but that doesn't
On Sun, Feb 10, 2008 at 10:17:01AM -0800, ron minnich wrote:
What would such a global identifier be used for?
You have found a type of a thing (e.g. southbridge) and you want
to find the operations for that thing. You need an ID to do that.
Ah! Of course.
One option is we just adopt a
On Sun, Feb 10, 2008 at 12:10:58PM -0800, yhlu wrote:
If you have one DSDT that could handle irq routing, (that DSDT need
one clean room implementation, instead of stealing or referring
dumping from legacy BIOS)
you could acpi with DSDT only.
you will still need pirq table for some
On Mon, Feb 11, 2008 at 01:57:40AM +0100, Carl-Daniel Hailfinger wrote:
Signed-off-by: Carl-Daniel Hailfinger [EMAIL PROTECTED]
Acked-by: Peter Stuge [EMAIL PROTECTED]
Index: LinuxBIOSv3-carsize_Kconfig/include/arch/x86/amd_geodelx.h
On Sun, Feb 10, 2008 at 03:43:25PM -0800, Baski wrote:
rom address for PCI: 01:06.0 = f408
PCI Expansion ROM, signature 0xaa55, INIT size 0x8000, data ptr 0x0144
PCI ROM Image, Vendor 5333, Device 8a01,
PCI ROM Image, Class Code 03, Code Type 00
Class Code mismatch ROM 0003, dev
On Sun, Feb 10, 2008 at 01:51:18PM -0800, ron minnich wrote:
This is a possible dts for alix1c. This actually builds and works,
but linux panics, so that's an issue, but how does it look?
Definately the right direction, but some comments..
cpus {
cpupath=0;
On Mon, Feb 11, 2008 at 02:39:15AM +0100, Carl-Daniel Hailfinger wrote:
The config system is not there to set code internal only
variables.
Hmm.
That's what the arch/x86 cpu dependent include files are there
for.
Which files?
How do you define code internal only variables? I think
On Mon, Feb 11, 2008 at 02:57:53PM +0100, Tomasz. Malewski wrote:
Currently I think about
TPC-1261
http://taiwan.advantech.com.tw/unzipfunc/Unzip/1-1VSUA1/TPC-1261H_DS.pdf
Could be used for a very nice PoS system, booting the application
from BIOS flash in a few seconds. :)
Inside are:
On Mon, Feb 11, 2008 at 07:10:07PM -0800, Chris Kilgour wrote:
[openvsa]
provide default pointer initializer to avoid compiler warning
Signed-off by: Chris Kilgour [EMAIL PROTECTED]
Acked-by: Peter Stuge [EMAIL PROTECTED]
--
coreboot mailing list
coreboot@coreboot.org
http
On Wed, Feb 13, 2008 at 12:33:48PM -0800, ron minnich wrote:
The ELF parser in v3 ought to be removed.
Do you mean elfboot?
//Peter
--
coreboot mailing list
coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
I have issues with parts of this.
On Wed, Feb 13, 2008 at 10:00:21PM +0100, [EMAIL PROTECTED] wrote:
Minclude/device/path.h
Add LPC path type, replacing SUPERIO path type, since SUPERIO is
only one type of LPC. Clean up tabbing in parts of the file
(cosmetic).
I think this needs more
On Thu, Feb 14, 2008 at 02:30:48PM -0800, ron minnich wrote:
It's not that hard to create a MANIFEST file.
I still think it's far simpler to have an option to extract LAR
files as LAR files.
I would prefer ELF because it's more standard - if it can do all we
need.
//Peter
--
coreboot
On Thu, Feb 14, 2008 at 03:16:24PM -0700, Marc Jones wrote:
This is an interesting idea but the devices are CS5536 specific and
I don't think we want to make dts CS5536 aware.
I would like nothing more than to make coreboot understand the Geode
architecture natively. Maybe a goal for v4, once
On Thu, Feb 14, 2008 at 05:34:04PM -0800, ron minnich wrote:
Note one thing the arrays in the individual files got you. You
could drag along ALL types of a (e.g.) the intel southbridge even
when you only specified one of them in a dts.
*nods* Hopefully we can be smart about this also in the
On Thu, Feb 14, 2008 at 05:48:01PM -0800, ron minnich wrote:
This is not signed off yet, but is close.
It also boots qemu just fine, which is a good sign.
Great!
Note that from now on, to pull a constructor into the coreboot
image and make it available, some dts somewhere has to name
On Thu, Feb 14, 2008 at 07:12:54PM +0100, Segher Boessenkool wrote:
The general syntax of a pathname component in OF is:
[EMAIL PROTECTED]:args
Thanks for the insight!
unit-addr is (the text representation of) the address for the
node, in the parent's address space.
This statement
On Fri, Feb 15, 2008 at 12:13:10PM +0300, Mikhail Savchenko wrote:
Are where any methodic to patch this file follow the platform
specific?
Sorry, I do not completely understand you.
If you are asking if the implementation of cache as ram is platform
specific then the answer is yes.
Currently
Hi Fridel,
On Sat, Feb 16, 2008 at 12:15:14AM +0200, Fridel Fainshtein wrote:
My employer generally allows to submit GPL staff. However, it seams
that he refuses that I submit something.
I tried to get an official permit a month ago and still failed to get
something.
As I'm sure your
On Fri, Feb 15, 2008 at 11:43:48AM -0700, Marc Jones wrote:
Does the VSA have any default policy by the way?
The devices are present and available to the system. Is that what
you were asking?
Right - so by default all virtual PCI devices are present and
available, and any unwanted ones
, we may never.
With rename:
Acked-by: Peter Stuge [EMAIL PROTECTED]
--
coreboot mailing list
coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
southbridge/intel/i82371eb/ide - ide.dts
Update mainboard/pcengines/alix1c/dts and emulation/qemu-x86/dts accordingly.
Signed-off-by: Peter Stuge [EMAIL PROTECTED]
--
Index: southbridge/intel/i82371eb/ide
===
--- southbridge/intel/i82371eb/ide
On Mon, Feb 18, 2008 at 01:12:23AM +0100, Ronald Hoogenboom wrote:
So now I get in the 'initializing devices'-stage:
rom address for PCI: 07:00.0 = f700
copying VGA ROM Image from 0xf700 to 0xc, 0xda00 bytes
entering emulator
halt_sys: file
On Sun, Feb 17, 2008 at 08:38:30PM -0500, [EMAIL PROTECTED] wrote:
I need something that will probe the GPIO's to find out which one is
asserted and if the signal is in or out? Does that make more sense?
Unfortunately you are now at the point where you would need the board
schematic.
It can't
On Sun, Feb 17, 2008 at 08:00:39PM -0800, Jonathan Sturges wrote:
It seems unlikely the patch would be accepted without license
headers, yet I can't vouch for the origin of the Eaglelion source
files, so it would seem presumptuous of me to put a GPL license
header in my target's files.
What's
On Mon, Feb 18, 2008 at 08:12:30AM -0800, ron minnich wrote:
One other option: have the code see how many boards match based on PCI
ids. If it is more than one, ask the user which board it is by giving
them a selection. That way, code won't stop at first match, and it can
detect ambiguities.
On Tue, Feb 19, 2008 at 12:18:00AM +0100, Ronald Hoogenboom wrote:
I also noticed that the k8 powernow doesn't work:
'powernow-k8: MP systems not supported by PSB BIOS structure'
the kernel says.
Yeah - I always thought that was related to the lack of ACPI
support.
How to tackle
On Mon, Feb 18, 2008 at 09:44:54PM +0100, [EMAIL PROTECTED] wrote:
Completely replace DBE61 initram code by Alix.1C initram code.
+/* The part is a Hynix hy5du121622ctp-d43.
Still true?
//Peter
--
coreboot mailing list
coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
On Mon, Feb 18, 2008 at 07:45:55PM -0500, [EMAIL PROTECTED] wrote:
Once you have the base address, you can read the GPIO control
registers from /dev/port, with the seek equal to the base address.
How?? This is the part I am looking for, this would be the golden
ticket:-)
Oh! This can be
nonexisting files were #included.
Looks good. Works? Ack.
Signed-off-by: Carl-Daniel Hailfinger [EMAIL PROTECTED]
Acked-by: Peter Stuge [EMAIL PROTECTED]
Index: LinuxBIOSv3-includecleanup/include/device/smbus.h
On Tue, Feb 19, 2008 at 09:17:17AM +0200, Mart Raudsepp wrote:
So basically it would be nice if setting up the serial port on
DDC pins would be a configurable thing.
As it should be! The 5536 code needs to learn how to control it, and
there could be a setting in the dts - for starters.
Or
On Wed, Feb 20, 2008 at 11:00:00AM +1000, Nick Stallman wrote:
a Intel 82845PE MCH northbridge
This is the main problem. I don't think anyone has both documentation
and time for this at the moment. :\
and a Intel 82801DA ICH 4 southbridge.
The rest of the board should be fairly
}, {333, 75}
}
instead? Other than that:
Acked-by: Peter Stuge [EMAIL PROTECTED]
--
coreboot mailing list
coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
On Fri, Feb 22, 2008 at 06:28:47PM -0700, Marc Jones wrote:
Updates to Norwich to get the system booting.
Signed-off-by: Marc Jones [EMAIL PROTECTED]
Acked-by: Peter Stuge [EMAIL PROTECTED]
Index: coreboot-v3/mainboard/amd/Kconfig
On Sun, Feb 24, 2008 at 11:21:29PM +0100, Ronald Hoogenboom wrote:
This trivial patch removes an unused local variable, thus getting rid of
a compiler warning.
Signed-off-by: Ronald Hoogenboom [EMAIL PROTECTED]
Acked-by: Peter Stuge [EMAIL PROTECTED]
Index: src/southbridge/nvidia/mcp55
On Sun, Feb 24, 2008 at 09:18:33PM -0500, [EMAIL PROTECTED] wrote:
Should I download both, and copy filo into the etherboot src
directory and try to build it?
I like a plain Etherboot from rom-o-matic.net and then storing FILO
or whatever other payload on a boot server until I am ready to
it, make those unsigned longs u32s, if not,
still:
Acked-by: Peter Stuge [EMAIL PROTECTED]
--
coreboot mailing list
coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
On Wed, Jun 04, 2008 at 01:21:46PM -0600, Marc Jones wrote:
This patch uses byte pointer and the MMIO read and write functions.
Nice.
+ writel(readl(bar + IPREG04) | USB_HCCPW_SET, bar + IPREG04);
..though I still prefer set and clear functions or macros over this.
//Peter
--
On Thu, May 29, 2008 at 10:46:33AM -0400, Tom Sylla wrote:
Add dump support for Winbond (NSC) PC87427. Dumps available from real
hardware.
Signed-off-by: Tom Sylla [EMAIL PROTECTED]
Acked-by: Peter Stuge [EMAIL PROTECTED]
Index: nsc.c
On Wed, Jun 04, 2008 at 01:30:52PM +0200, Uwe Schwarz wrote:
If it fails in the reset you can try making the pll lock time
longer but I doubt that it will help.
msrGlcpSysRstpll.lo |= (0xFF RSTPPL_LOWER_HOLD_COUNT_SHIFT);
and that did the trick.
What is this indicative of?
Some clock
On Fri, Jun 06, 2008 at 11:01:06PM +0200, Patrick Georgi wrote:
Index: northbridge/intel/i440bxemulation/domain
===
--- northbridge/intel/i440bxemulation/domain (revision 689)
+++ northbridge/intel/i440bxemulation/domain
On Fri, Jun 06, 2008 at 09:10:49PM +0200, Peter Stuge wrote:
On Thu, May 29, 2008 at 10:46:33AM -0400, Tom Sylla wrote:
Add dump support for Winbond (NSC) PC87427. Dumps available from real
hardware.
Signed-off-by: Tom Sylla [EMAIL PROTECTED]
Acked-by: Peter Stuge [EMAIL PROTECTED
On Sat, Jun 07, 2008 at 04:07:29PM +0200, Stefan Reinauer wrote:
Ah, this is broken... flashrom should not continue when it found a
chip in a given memory area already.
flashrom supports boards with more than one flash chip.
But perhaps we need to teach flashrom more about how chips can be
On Sat, Jun 07, 2008 at 09:23:07PM -0700, Chris Kilgour wrote:
http://www.whiterocker.com/gpxe/
FYI - At this point I don't plan to submit any patches to gPXE as
my approach is rather hackish and still experimental.
Any comments/suggestions welcome.
Great work!
How do you think that a
On Sun, Jun 08, 2008 at 11:37:40PM -0400, Kevin O'Connor wrote:
I plan on hacking coreboot-v2 so that it deploys the tables to the
top of ram instead of 0xf. I then plan on having legacybios
locate the tables (by looking at the coreboot table) and then copy
the subset of tables that must
On Mon, Jun 09, 2008 at 01:06:08PM -0400, Joseph Smith wrote:
Does anyone know the mathematical formula for converting memory
clock cycles into microseconds (us)??
1 MHz means 1 million clock cycles per second, so 1 clock cycle
per microsecond.
166 MHz - 166 clock cycles per
On Mon, Jun 09, 2008 at 01:23:21PM -0400, Joseph Smith wrote:
If yes, why shouldn't LegacyBIOS simply be included in coreboot?
I definitely think it should. We have half a legacybios in there
for VGA init anyways.
Obviously as an option. Or, rather, as a dependency when you choose
the
On Mon, Jun 09, 2008 at 11:23:51AM -0600, Marc Jones wrote:
I still don't want coreboot to know about BIOS tables at all.
Alas, it already does, there is both PIR and ACPI.
Because they are required by Linux.
Wasn't that supposed to change though? Does anyone know what happened
with the
On Mon, Jun 09, 2008 at 01:36:29PM -0400, Joseph Smith wrote:
Does anyone know the mathematical formula for converting memory
clock cycles into microseconds (us)??
1 MHz means 1 million clock cycles per second, so 1 clock cycle
per microsecond.
166 MHz - 166 clock cycles per
On Mon, Jun 09, 2008 at 09:50:30PM +0200, Rudolf Marek wrote:
I dont understand why:
...
Setting variable MTRR 02, base: MB, range: 0200MB, type WB
...
The range is only to 200MB ???
I believe this is hex, so 512MB decimal.
I have no other DDR2 module to check.
Could you test the
On Mon, Jun 09, 2008 at 05:48:11PM -0400, Joseph Smith wrote:
On Mon, 9 Jun 2008 23:43:10 +0200, Peter Stuge [EMAIL PROTECTED] wrote:
On Mon, Jun 09, 2008 at 03:15:46PM -0400, Joseph Smith wrote:
How hard would it be to add a nanoseconds delay to delay.h?
It would probably have
1 - 100 of 2826 matches
Mail list logo
