Re: [coreboot] #91: Add --list-supported option

+--- Changes (by uwe): * status: new = closed * patchstatus: there is no patch = patch has been committed * resolution: = fixed Comment: Fixed in r91. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/91#comment:1

[coreboot] #92: Add --version option

| -+-- Flashrom should have a --version option too, similar to superiotool (based on svn revision). -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/92 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org

Re: [coreboot] #87: flashrom issues on m57sli-s4

= closed * resolution: = fixed Comment: PLCC-based flashing was accidentally broken in r2972. This was fixed in r3087. SPI-based flashing is now also fixed since r3088, thanks to Florentin Demetrescu. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/87#comment:6 coreboot

Re: [coreboot] #69: Fix mptable util so the output will compile

://tracker.linuxbios.org/trac/coreboot/ticket/69#comment:3 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #70: fix util/getpir so that the output will compile

: | Patchstatus: patch needs work --+- Comment (by [EMAIL PROTECTED]): Signed-off-by: Jon Dufresne [EMAIL PROTECTED] -- Ticket URL: http://tracker.linuxbios.org/trac/coreboot/ticket/70#comment

Re: [coreboot] #70: fix util/getpir so that the output will compile

URL: http://tracker.linuxbios.org/trac/coreboot/ticket/70#comment:3 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #80: serial console in grub2 works

: Port GRUB2 to coreboot Component: grub2| Version: Resolution: fixed| Keywords: Dependencies: | Patchstatus: patch needs review

[coreboot] #97: Clean up probe_flash()

and extensibility. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/97 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] #98: Eliminate false positive unknown .. SPI chip matches

URL: http://tracker.coreboot.org/trac/coreboot/ticket/98 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] #99: Clean up it87xx_probe_spi_flash() for better readability

| --+- -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/99 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #97: Clean up probe_flash()

+--- Changes (by stepan): * owner: somebody = stuge * patchstatus: patch needs review = patch is ready to be committed Comment: Acked-by: Stefan Reinauer [EMAIL PROTECTED] -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/97#comment

[coreboot] #101: flashrom: Remove pciutils check from Makefile

/coreboot/ticket/101 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] #102: flashrom: coreboot ROM image file identification heuristic is broken

#102: flashrom: coreboot ROM image file identification heuristic is broken ---+ Reporter: stuge| Owner: somebody Type: defect | Status: new

Re: [coreboot] #101: flashrom: Remove pciutils check from Makefile

://tracker.coreboot.org/trac/coreboot/ticket/101#comment:1 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] #104: flashrom: Change flash drivers to never erase data before writing

://tracker.coreboot.org/trac/coreboot/ticket/104 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] #105: flashrom: add documentation files (ChangeLog etc) that need to be in the release

| -+-- -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/105 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #107: flashrom: Display test status in -L chip listing

+--- Comment(by stuge): Can also include adding wiki-usable output. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/107#comment:1 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #97: Clean up probe_flash()

+--- Changes (by stuge): * status: new = closed * patchstatus: patch is ready to be committed = patch has been committed * resolution: = fixed Comment: r3407 -- Ticket URL: http://tracker.linuxbios.org/trac/coreboot/ticket/97#comment:2 coreboot http

Re: [coreboot] #101: flashrom: Remove pciutils check from Makefile

-+-- Changes (by stuge): * owner: somebody = stuge * patchstatus: patch needs review = patch needs work Comment: Fair enough, will work on patch. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/101#comment:2 coreboot http

[coreboot] #108: Add int 10 VESA video driver to libpayload

/coreboot/ticket/108 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #105: flashrom: add documentation files (ChangeLog etc) that need to be in the release

marked as e.g. Calling this our release 1.0 should be enough. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/105#comment:1 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #102: flashrom: coreboot ROM image file identification heuristic is broken

#102: flashrom: coreboot ROM image file identification heuristic is broken -+-- Reporter: stuge | Owner: somebody Type: defect|Status: new Priority

Re: [coreboot] #102: flashrom: coreboot ROM image file identification heuristic is broken

#102: flashrom: coreboot ROM image file identification heuristic is broken -+-- Reporter: stuge | Owner: somebody Type: defect|Status: new Priority

Re: [coreboot] #102: flashrom: coreboot ROM image file identification heuristic is broken

#102: flashrom: coreboot ROM image file identification heuristic is broken -+-- Reporter: stuge | Owner: somebody Type: defect|Status: closed

Re: [coreboot] #105: flashrom: add documentation files (ChangeLog etc) that need to be in the release

into the Makefile to create a Changelog file out of 'svn log', I'm just saying it's not absolutely required for the debian package. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/105#comment:2 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http

Re: [coreboot] #102: flashrom: coreboot ROM image file identification heuristic is broken

#102: flashrom: coreboot ROM image file identification heuristic is broken -+-- Reporter: stuge | Owner: somebody Type: defect|Status: reopened Priority: major

Re: [coreboot] #103: flashrom: Don't exit() after successful erase operation

(by stuge): * owner: somebody = stuge -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/103#comment:1 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #100: flashrom: Change start/end -s and -e to -S and -E, and change erase -E to -e.

+--- Comment(by hailfinger): If you can make sure nobody erases his chip by accident with this patch, why not? That would reauire additional command line argument verification, though. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket

Re: [coreboot] #104: flashrom: Change flash drivers to never erase data before writing

the automatic behavior per default in advance. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/104#comment:2 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #102: flashrom: coreboot ROM image file identification heuristic is broken

#102: flashrom: coreboot ROM image file identification heuristic is broken -+-- Reporter: stuge | Owner: somebody Type: defect|Status: reopened Priority: major

Re: [coreboot] #102: flashrom: coreboot ROM image file identification heuristic is broken

#102: flashrom: coreboot ROM image file identification heuristic is broken -+-- Reporter: stuge | Owner: somebody Type: defect|Status: reopened Priority: major

Re: [coreboot] #102: flashrom: coreboot ROM image file identification heuristic is broken

#102: flashrom: coreboot ROM image file identification heuristic is broken -+-- Reporter: stuge | Owner: somebody Type: defect|Status: reopened Priority: major

Re: [coreboot] #102: flashrom: coreboot ROM image file identification heuristic is broken

#102: flashrom: coreboot ROM image file identification heuristic is broken -+-- Reporter: stuge | Owner: somebody Type: defect|Status: reopened Priority: major

Re: [coreboot] #102: flashrom: coreboot ROM image file identification heuristic is broken

#102: flashrom: coreboot ROM image file identification heuristic is broken -+-- Reporter: stuge | Owner: stuge Type: defect|Status: new Priority: major

Re: [coreboot] #102: flashrom: coreboot ROM image file identification heuristic is broken

#102: flashrom: coreboot ROM image file identification heuristic is broken -+-- Reporter: stuge | Owner: stuge Type: defect|Status: new Priority: major

[coreboot] #109: flash base autodetection on AMD SC520

. It drops the nasty ifdefs and implements auto detection for AMD SC520 systems, such as the Technologic Systems TS5300. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/109 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman

Re: [coreboot] #109: flash base autodetection on AMD SC520

): * version: v2 = * component: adlo = flashrom * milestone: = flashrom v1.0 -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/109#comment:1 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #105: flashrom: add documentation files (ChangeLog etc) that need to be in the release

+--- Comment(by stepan): Is this only about changelog, or anything else? (topic says ChangeLog etc) -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/105#comment:3 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http

Re: [coreboot] #106: flashrom: Add -T to automatically test all flash chip operations

+--- Changes (by stepan): * milestone: flashrom v1.0 = flashrom 1.1 -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/106#comment:3 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #109: flash base autodetection on AMD SC520

and another variable elan_baseaddr. That way, we can keep the main flashrom loop mostly free of chipset/processor dependent stuff. I'm open to variants of the above, though, as long as code is moved to chipset_enable.c. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/109#comment:2

Re: [coreboot] #109: flash base autodetection on AMD SC520

is very readable and upon moving it to chipset_enable.c, it is Acked-by: Carl-Daniel Hailfinger [EMAIL PROTECTED] -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/109#comment:3 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http

Re: [coreboot] #102: flashrom: coreboot ROM image file identification heuristic is broken

#102: flashrom: coreboot ROM image file identification heuristic is broken -+-- Reporter: stuge | Owner: stuge Type: defect|Status: new Priority: major

[coreboot] #110: Allow for per-device subsystem IDs

: Component: coreboot |Version: v3 Keywords: | Dependencies: Patchstatus: there is no patch | -+-- Currently both v2 and v3 only allow us to use one global set

[coreboot] #111: Add i18n support for translating strings e.g. for bayou / coreinfo

://tracker.coreboot.org/trac/coreboot/ticket/111 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] #112: probe_flash calculates base address before final value of size is known

to segher in #coreboot. In probe_flash(), flash_baseaddr is set before the getpagesize() size check, thus can be invalid, causing mmap issues. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/112 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http

Re: [coreboot] #112: probe_flash calculates base address before final value of size is known

://tracker.coreboot.org/trac/coreboot/ticket/112#comment:1 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] #113: problem

|Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | -+-- there is a bug -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/113

Re: [coreboot] #113: problem

`? {{{ # ./flashrom Calibrating delay loop... OK. No coreboot table found. Found chipset Intel ICH7M, enabling flash write... OK. Found chip Macronix MX25L8005 (1024 KB) at physical address 0xfff0. Found chip Macronix unknown Macronix SPI chip (0 KB) at physical address 0xf000. Multiple

Re: [coreboot] #113: problem

. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/113#comment:2 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #113: flashrom -c does not accept vendor+chip name, only chip name (was: problem)

should accept the combination of vendor and chip name as well, not only the chip name. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/113#comment:3 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #88: Add UHCI/OHCI/EHCI support to GRUB2

): * priority: critical = minor * resolution: = wontfix * status: new = closed * component: grub2 = libpayload * milestone: Port GRUB2 to coreboot = Comment: The usb stack was moved to libpayload, and we stopped developing for GRUB2. Thus closing this bug. OHCI and EHCI

Re: [coreboot] #12: Make coreboot work on a laptop

#12: Make coreboot work on a laptop -+-- Reporter: uwe | Owner: stepan Type: task |Status: assigned Priority: major | Milestone: Going mainstream

Re: [coreboot] #98: Eliminate false positive unknown .. SPI chip matches

(by stepan): Acked-by: Stefan Reinauer [EMAIL PROTECTED] -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/98#comment:2 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #98: Eliminate false positive unknown .. SPI chip matches

-+-- Changes (by stepan): * owner: somebody = stuge * patchstatus: patch needs review = patch is ready to be committed -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/98#comment:3 coreboot http://www.coreboot.org

Re: [coreboot] #98: Eliminate false positive unknown .. SPI chip matches

-+-- Changes (by stuge): * status: new = closed * patchstatus: patch is ready to be committed = patch has been committed * resolution: = fixed Comment: Thanks! Committed in r3562. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/98

[coreboot] #115: Enhance debug printk for pci_device

| -+-- Use dev_path() to have nice debug output patch is run-time tested -- Ticket URL: /trac/ticket/115 coreboot http://www.coreboot.org/ -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman

Re: [coreboot] #115: Enhance debug printk for pci_device

Priority: trivial| Milestone: Component: coreboot | Version: v2 Resolution: | Keywords

Re: [coreboot] #110: Allow for per-device subsystem IDs

: Component: coreboot |Version: v3 Keywords: | Dependencies: Patchstatus: there is no patch | -+-- Comment(by uwe): This should be fixed in v3 since r1045

[coreboot] #116: dtc-parser.tab.c Fehler 127

Version: v3 | Keywords: dtc-parser Dependencies: | Patchstatus: there is no patch ---+ /Desktop/thinclient/coreboot-v3 % make CP build/config.h GEN build/build.h CC build/lib

Re: [coreboot] #116: dtc-parser.tab.c Fehler 127

Version: v3 | Keywords: dtc-parser Dependencies: | Patchstatus: there is no patch ---+ Comment(by stepan): Also, what's your bison version? -- Ticket URL: http://tracker.coreboot.org/trac/coreboot

Re: [coreboot] #116: dtc-parser.tab.c Fehler 127

Version: v3 | Keywords: dtc-parser Dependencies: | Patchstatus: there is no patch ---+ Description changed by stepan: Old description: /Desktop/thinclient/coreboot-v3 % make CP build/config.h

Re: [coreboot] #116: dtc-parser.tab.c Fehler 127

://tracker.coreboot.org/trac/coreboot/ticket/116#comment:2 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #109: flash base autodetection on AMD SC520

-+-- Changes (by stuge): * status: new = closed * patchstatus: patch needs work = patch has been committed * resolution: = fixed Comment: r3790 -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/109#comment:4 coreboot http://www.coreboot.org/ -- coreboot mailing list

[coreboot] #117: flashrom: Check if erase succeeds and exit with error on failure

| --+- -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/117 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #117: flashrom: Check if erase succeeds and exit with error on failure

-+-- Changes (by stuge): * status: new = closed * patchstatus: patch is ready to be committed = patch has been committed * resolution: = fixed Comment: r3797 -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/117#comment:1

Re: [coreboot] #104: flashrom: Change flash drivers to never erase data before writing

| -+-- Changes (by stuge): * owner: somebody = stuge * dependencies: #103 = * milestone: flashrom v1.0 = flashrom v1.1 -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/104#comment:7 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] #100: flashrom: Change start/end -s and -e to -S and -E, and change erase -E to -e.

, with something like -s -n which would specify an inclusive byte range to operate on, AKA partial operation. Depends/duplicate #104. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/100#comment:2 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] #106: flashrom: Add -T to automatically test all flash chip operations

+--- Changes (by stuge): * status: new = closed * dependencies: = #103 * resolution: = duplicate * milestone: flashrom v1.1 = flashrom v1.0 Comment: dup #103 -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/106#comment:4 coreboot http://www.coreboot.org

Re: [coreboot] #103: flashrom: Don't exit() after successful erase; enable testing all operations in one invocation (was: flashrom: Don't exit() after successful erase)

and write back the original, verifying each step. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/103#comment:5 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #104: flashrom: Change flash drivers to not erase in the write function (was: flashrom: Change flash drivers to never erase data before writing)

| ---+ Changes (by stuge): * keywords: erase write = partial erase write * type: defect = enhancement Comment: --8-- [http://www.coreboot.org/pipermail/coreboot/2008-December/042781.html email from Yu Ning FENG] {{{ We are talking about choosing some options from the full list

Re: [coreboot] #107: flashrom: Display test status in -L chip listing

(by stuge): * owner: somebody = stuge * status: new = assigned * patchstatus: there is no patch = patch needs review -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/107#comment:3 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] #104: flashrom: Partial operations; change flash drivers to not erase in the write function (was: flashrom: Change flash drivers to not erase in the write function)

| ---+ -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/104#comment:9 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #107: flashrom: Display test status in -L chip listing

+--- Changes (by stuge): * status: assigned = closed * patchstatus: patch needs review = patch has been committed * resolution: = fixed Comment: r3803 -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/107#comment:4 coreboot http

Re: [coreboot] #105: flashrom: add documentation files (ChangeLog etc) that need to be in the release

+--- Changes (by stepan): * status: new = closed * resolution: = fixed Comment: Thanks, Uwe. It seems svn log provides a sufficient changelog functionality. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/105#comment:4 coreboot http

Re: [coreboot] #102: flashrom: coreboot ROM image file identification heuristic is broken

#102: flashrom: coreboot ROM image file identification heuristic is broken -+-- Reporter: stuge | Owner: stuge Type: defect|Status: new Priority: major

Re: [coreboot] #102: flashrom: coreboot ROM image file identification heuristic is broken

#102: flashrom: coreboot ROM image file identification heuristic is broken -+-- Reporter: stuge | Owner: stuge Type: defect|Status: new Priority: major

Re: [coreboot] #103: flashrom: Don't exit() after successful erase; enable testing all operations in one invocation

simplifying the test procedure from many flashrom+hexdump commands into a single flashrom command is minor, so changing prio back.) -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/103#comment:7 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] #102: flashrom: coreboot ROM image file identification heuristic is broken

#102: flashrom: coreboot ROM image file identification heuristic is broken -+-- Reporter: stuge | Owner: stuge Type: defect|Status: closed Priority: major

Re: [coreboot] #103: flashrom: Don't exit() after successful erase; enable testing all operations in one invocation

+write are totally unclear. If you perform read, erase, write, verify (in that order) it means that you just rewrite ROM contents. That may or may not be desired, but it sure would work for testing read/write/erase operations. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/103

Re: [coreboot] #102: flashrom: coreboot ROM image file identification heuristic is broken

#102: flashrom: coreboot ROM image file identification heuristic is broken -+-- Reporter: stuge | Owner: stuge Type: defect|Status: reopened Priority: major

Re: [coreboot] #102: flashrom: coreboot ROM image file identification heuristic is broken

#102: flashrom: coreboot ROM image file identification heuristic is broken -+-- Reporter: stuge | Owner: stuge Type: defect|Status: new Priority: major

Re: [coreboot] #102: flashrom: coreboot ROM image file identification heuristic is broken

#102: flashrom: coreboot ROM image file identification heuristic is broken -+-- Reporter: stuge | Owner: stuge Type: defect|Status: assigned Priority: major

Re: [coreboot] #103: flashrom: Don't exit() after successful erase; enable testing all operations in one invocation

, and have the tool do one thing at a time. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/103#comment:9 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #102: flashrom: coreboot ROM image file identification heuristic is broken

#102: flashrom: coreboot ROM image file identification heuristic is broken -+-- Reporter: stuge | Owner: stuge Type: defect|Status: closed

Re: [coreboot] #2: Complete tables of supported motherboards

-microzide-cheapest-pill-without- prescription/here/a -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/2#comment:3 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #2: Complete tables of supported motherboards

-unguento-usos/here/a -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/2#comment:4 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #2: Complete tables of supported motherboards

:1845357viagra/a -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/2#comment:5 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #2: Complete tables of supported motherboards

of profit for the owners and for the investors. Plans: 108 % after 1 day 118% after 2 days 128% after 3 days 10% referral commission! http://thewinterprofit.com/?ref=jon -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/2#comment:6 coreboot http://www.coreboot.org

Re: [coreboot] #2: Complete tables of supported motherboards

://justnkldkhsjvd.com/you were joked!/a -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/2#comment:7 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] #2: Complete tables of supported motherboards

and for the investors. Plans: 108 % after 1 day 118% after 2 days 128% after 3 days 10% referral commission! http://thewinterprofit.com/?ref=beo -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/2#comment:8 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org

[coreboot] #118: Flashrom Makefile improvements

. a few improvements and i corrected LD/C-FLAGS usage and link order e.g. for --as-needed. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/118 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] #119: Winbond W39V040FBPZ is not written correctly by flashrom

Calibrating delay loop... OK. No coreboot table found. Found chipset Intel ICH7/ICH7R, enabling flash write... OK. Found chip Winbond W39V040B (512 KB) at physical address 0xfff8. Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0007 at address: 0x0007 Verifying

Re: [coreboot] #119: Winbond W39V040FBPZ is not written correctly by flashrom

was doing nothing at all. I left the system at this state for a whole day, but still nothing happened. Then I tried again using a SST 49LF040 chip on the board (VIA PC2500e) and flashing worked without any problem. Andreas Wanske -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket

Re: [coreboot] #119: Winbond W39V040FBPZ is not written correctly by flashrom

are really problematic. If we try to program them according to their data sheets, they fail sometimes. Any insight is appreciated. No other chip vendor has these problems. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/119#comment:2 coreboot http://www.coreboot.org/ -- coreboot

Re: [coreboot] #119: Winbond W39V040FBPZ is not written correctly by flashrom

about this chip is that by mistake I was successful programming it with an EEPROM programmer using the settings for SST49LF004 (I forgot to change models to the Winbond part) -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/119#comment:3 coreboot http://www.coreboot.org

[coreboot] #120: flashrom failure to read

bytes. Standard output: {{{ Calibrating delay loop... OK. No coreboot table found. Found chipset Intel ICH9R, enabling flash write... tried to set 0xdc to 0x3 on Intel ICH9R failed (WARNING ONLY) FAILED! Found chip Macronix MX25L8005 (1024 KB) at physical address 0xfff0. Reading flash

Re: [coreboot] #120: flashrom failure to read

://www.coreboot.org/Development_Guidelines#Reviews for a full description of how Acked-by-lines work/look.) -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/120#comment:1 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman

Re: [coreboot] #120: flashrom failure to read

results, i.e., disk file full of null bytes, verbose output complains about Opcode 3. Standard output: {{{ Calibrating delay loop... OK. No coreboot table found. Found chipset Intel ICH9R, enabling flash write... tried to set 0xdc to 0x3 on Intel ICH9R failed (WARNING ONLY) FAILED! Found

Re: [coreboot] #120: flashrom failure to read

other problem. I just committed a small change that adds useful debugging in r3862. Please update and resend output from running with -V. -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/120#comment:3 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] #120: flashrom failure to read

://tracker.coreboot.org/trac/coreboot/raw- attachment/ticket/120/fr.ich9prg_ops_fail.patch fr.ich9prg_ops_fail.patch] without fr.ich9lock2-s.patch applied, and post the verbose output. Thanks! -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/120#comment:4 coreboot http://www.coreboot.org

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