Whoa, I don't know how I let this one slip by... Did you manage to get SATA
working, by chance? That was a show stopper for me, but I haven't been able
to diagnose it.
2007/12/6 [EMAIL PROTECTED]:
Initial support for MSI MS-7135 (K8N Neo3) mainboard.
Signed-off-by: Jonathan A. Kollasch [EMAIL
PROTECTED] wrote:
On Fri, Feb 01, 2008 at 12:06:15AM -0800, David Hendricks wrote:
Whoa, I don't know how I let this one slip by... Did you manage to get
SATA
working, by chance? That was a show stopper for me, but I haven't been
able
to diagnose it.
I did not get the second set of two
That's very possible -- My pirq table didn't look nearly as nice as yours!
On Feb 2, 2008 11:45 AM, [EMAIL PROTECTED] wrote:
On Fri, Feb 01, 2008 at 10:29:17PM -0800, David Hendricks wrote:
Have you benchmarked SATA performance? I'm curious if you can run a
quick
time dd kind of benchmark
Hey everyone,
Just thought I'd post a link to the tech talk Stefan, Peter and Ron gave at
Google a couple days ago: http://www.youtube.com/watch?v=X72LgcMpM9k .
The format goes:
1) Ron Minnich, project founder: What is Coreboot, motivation, and
principles of operation.
2) Peter Stuge, long-time
So far so good. I'm looking forward to reading up more on flashrom support,
but I suspect that it will come more or less automatically once all the
hardware is hooked up and the machine is booting linux.
On Wed, Nov 19, 2008 at 2:56 PM, Joseph Smith [EMAIL PROTECTED] wrote:
Well I almost have
On Sun, Mar 15, 2009 at 11:29 AM, Jason Self jason.s...@gmail.com wrote:
There is a fully free software laptop with free software BIOS, firmware,
driver, kernel, software, operating system. It is called Lemote
Yeeloong. You can see it here:
http://www.lemote.com/english/yeeloong.html
On Sat, Mar 21, 2009 at 8:58 PM, Carl-Daniel Hailfinger
c-d.hailfinger.devel.2...@gmx.net wrote:
Could this be something useful for us, especially considering it looks
like a combination of msrtool, inteltool etc?
I'd like to make sure we don't reinvent the wheel here.
Quoting from the
On Tue, Apr 7, 2009 at 12:04 PM, maarten van es
maarten.h.van...@gmail.comwrote:
Hello everyone,
I have just started to try out coreboot, and so far it works great in
qemu. My real target however is the jetway J7F2. I would like a larger
bios chip than the standard 512 kB on this board. Does
On Sat, Apr 11, 2009 at 3:14 PM, ron minnich rminn...@gmail.com wrote:
We just got the notice from Google. There are a lot of applicants
under 18 -- automatic disqualification. Student applicants, please
verify your personal information.
FWIW, if you happen to know some promising high-school
I am having some difficulty booting a FILO (r95) payload using coreboot-v2
(r4291). My target is a via vb7001g, but I'm using the epia-cn target since
the boards are practically identical afaict. The only hardware change I've
made is using a 2MB flash chip. I was able to boot some simple payloads
/rietveld/, which is a
relatively new open-source fork of Google's
Mondrianhttp://www.youtube.com/watch?v=sMql3Di4Kgc#t=25m20scode
review tool, is quite helpful as well though it seems behind RB at the
moment.
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Systems Software Engineer, Google Inc.
--
coreboot mailing
Attached is an lspci dump for the MSI 7135 (K8N Neo3) board. jakllsch did a
v2 port for this board last year. Flashrom works, but only if you do -m
msi:k8n-neo3 for erase and write operations. Uwe suggested posting the lspci
contents in case someone has a few spare cycles to try and implement
On Tue, Jun 23, 2009 at 7:06 PM, Rick Ant rick_...@yahoo.com wrote:
I got this message :
=
boot: hda:/boot/vmlinuz root=/dev/hda initrd=/boot/initrd console=ttyS0
hda: LBA48 524MB: QEMU HARDDISK
Mounted ext2fs
Found Linux version 2.6.16.5 (r...@e-smith) #2 PREEMPT Sat Sep
in this point ?
Thanks
--- On *Tue, 6/23/09, David Hendricks david.hendri...@gmail.com* wrote:
From: David Hendricks david.hendri...@gmail.com
Subject: Re: [coreboot] Which file should I burn?
To: Rick Ant rick_...@yahoo.com
Cc: coreboot@coreboot.org
Date: Tuesday, June 23, 2009, 7:49 PM
On Tue, Jun 23, 2009 at 2:28 AM, Alois Schlögl alois.schlo...@tugraz.atwrote:
The reason for asking is the bug as described here:
http://bugzilla.kernel.org/show_bug.cgi?id=13573
The bug is affecting my research at the university.
It was suggested that a Bios-update could solve the problem.
On Wed, Jun 24, 2009 at 12:30 AM, David Hendricks dhend...@google.comwrote:
On Tue, Jun 23, 2009 at 2:28 AM, Alois Schlögl
alois.schlo...@tugraz.atwrote:
The reason for asking is the bug as described here:
http://bugzilla.kernel.org/show_bug.cgi?id=13573
The bug is affecting my research
.
I use vim and grep. There is no IDE for coreboot development.
Interesting, but do you use any extensions for vim?
ctags are infinitely useful
--
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Fellow vim user
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http
From http://www.intel.com/intelpress/sum_eshl.htm :
*The UEFI Shell requires no platform-level customization. It requires no
drivers beyond those included in the shipping system. This means as the UEFI
Shell is used it becomes less and less likely to be the culprit of bugs
introduced as a part of
Salihun
darmawan.sali...@gmail.com wrote:
Is it to buffer the BIOS contents from SPI flash chip prior to
execution of the very first instruction?
I recall that it's impossible to execute code directly in an SPI chip.
That's correct, afaik.
--
David Hendricks (dhendrix)
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On Tue, Oct 27, 2009 at 2:04 PM, Gregg Levine gregg.drw...@gmail.comwrote:
On Tue, Oct 27, 2009 at 4:51 PM, David Hendricks dhend...@google.com
wrote:
On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun
darmawan.sali...@gmail.com wrote:
What is the BIOS RAM in AMD SB7XX used
. *mplayer
foo.ogg*. This usage model doesn't make sense for Flashrom, so it makes
sense to treat the filename as any other argument and require that it has a
flag preceding it to define the behavior.
/my $0.02
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Thanks for sending the patch out, Amit!
Since I wrote this particular patch, I'll go ahead and do the sign-off on
it:
Signed-off by: David Hendricks (dhend...@google.com)
On Wed, Jul 21, 2010 at 12:00 AM, amit.m...@nuvoton.com wrote:
This is the same patch as before (2010/07/14) just
Carl-Daniel pointed out some whitespace issues with the patch. I ran it thru
the indent -kr -i8 filter and fixed up the register table entries, so the
attached patch should address concerns about whitespace.
On Thu, Jul 22, 2010 at 1:30 PM, David Hendricks dhend...@google.comwrote:
Thanks
after a chip is found.
Signed-off by: David Hendricks (dhend...@google.com)
--
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
Index: superiotool-head/ite.c
===
--- superiotool-head.orig/ite.c
+++ superiotool-head/ite.c
kernel build system then this is not a good place to
start. I do not mean to sound rude, but the Linux and Coreboot build systems
are much more complicated than a make or gcc commands you may be familiar
with from small projects.
--
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc
inside the subdirectories are
called? Please mention the line which does this.
There's no recursive make.
if only ;-)
http://miller.emu.id.au/pmiller/books/rmch/
http://miller.emu.id.au/pmiller/books/rmch/
--
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
--
coreboot
by: Donald Huang (donald.hu...@ite.com.tw)
Signed-off by: Yung-chieh Lo (yj...@google.com)
Signed-off by: David Hendricks (dhend...@google.com)
Dear Donald,
thank you very much for you work. However, it seems the patch didn't arrive
on the mailing list. Can you try sending it again?
Hey
On Sat, Oct 2, 2010 at 3:19 AM, ali hagigat hagigat...@gmail.com wrote:
I understand that this can be frustrating, but it's something that the
coreboot project has no control over.
NDA stands for Non-Disclosure Agreement, which means that
At least you could add some lines about NDA story and
On Mon, Oct 4, 2010 at 12:23 PM, Peter Stuge pe...@stuge.se wrote:
phorsyon wrote:
a minimal and a consumer version of a certificate
As was mentioned, the more certifications there are, the less easy it
is for the market to make use of them.
I don't think we can afford to try to market
-by: David Hendricks dhend...@google.com
--
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
Index: fintek.c
===
--- fintek.c (revision 5953)
+++ fintek.c (working copy)
@@ -122,6 +122,50 @@
{0x30,0xf0,0xf1,0xf4,0xf5
On Tue, Nov 2, 2010 at 12:45 PM, Uwe Hermann u...@hermann-uwe.de wrote:
Hi,
On Mon, Nov 01, 2010 at 01:02:53PM -0700, David Hendricks wrote:
The patch (attached) was tested by a user on IRC who had the F71889FG. I
wrote it using documentation from Fintek's website available here:
http
$0.02
--
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@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
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, and
technically prepared for the topics of interest. We'll also send
confirmation with detailed instructions on how to find the building /
conference room to those who register.
Registration form:
https://spreadsheets.google.com/viewform?formkey=dGRab2s1VHRKNzRDX19pTVVrTjhVTkE6MQ
--
David
[ cc'ing flashrom mailing ]
On Mon, Jan 17, 2011 at 5:39 PM, David Hendricks dhend...@google.comwrote:
Stefan mentioned that he knows several people who he has worked with in the
area, and we're thinking it would be fun to get everyone together for a day
of hacking on Coreboot and related
, 1min form is available @
https://spreadsheets.google.com/viewform?formkey=dGRab2s1VHRKNzRDX19pTVVrTjhVTkE6MQ
P.S. Stefan has 50 8Mbit FWH flash chips to give away!
On Mon, Jan 17, 2011 at 5:46 PM, David Hendricks dhend...@google.comwrote:
[ cc'ing flashrom mailing ]
On Mon, Jan 17, 2011 at 5
seem to be hanging. Network monitors would only indicate that my
SSH shell is the only thing running on the host.
fwiw, svn update works fine for me right now.
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http
disable
it for now.
Signed-off-by: David Hendricks dhend...@google.com
--
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
Index: smsc.c
===
--- smsc.c (revision 6181)
+++ smsc.c (working copy)
@@ -358,6 +358,8
On Wed, Feb 16, 2011 at 5:09 PM, Carl-Daniel Hailfinger
c-d.hailfinger.devel.2...@gmx.net wrote:
Auf 17.02.2011 01:11, David Hendricks schrieb:
Attached is a patch to add support for the SMSC MEC1308 embedded
controller.
Unfortunately, the device ID it conflicts with another SMSC Super
the SMSC code
could do the same :-/
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-512-3445
(last meeting's participants bcc'd since this is pretty short notice)
--
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, you can order mini-PCIe to serial
converters with the Oxford chip such as the Startech MPEX2S952 for about
$60USD. Here's a link:
http://www.amazon.com/2-PORT-Mini-Pci-Express-Card/dp/B003OCRW1Q/ref=sr_1_fkmr3_3?ie=UTF8qid=1303343174sr=8-3-fkmr3
--
David Hendricks (dhendrix)
Systems Software
have enough developers contributing that it's worth moving to
a more advanced SCM. Especially since a lot of changes can linger for days
or weeks since hardware scarcity can often limit the ability of reviewers
and testers.
--
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc
in future, and we will
certainly tweak the ad-hoc messages and formatting some more.
I suggest squelching the Patch set updated messages on the mailing list.
Reviewers will get the notifications anyway, so for those who are not
reviewing a patch those notifications are excessive.
--
David
to Patch history in the upper left corner
3. Choose two patch sets to diff.
4. Hit the update button.
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should get e-mails for comments and
iterations.
(Note: I haven't verified this with Coreboot's gerrit setup)
--
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in
laptops. I think you have a normal SuperIO chip. UCC seems to be a
marketing name from AsRock that means Unlock CPU Core.
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On Thu, Jun 9, 2011 at 9:39 AM, Uwe Hermann u...@hermann-uwe.de wrote:
On Wed, Jun 08, 2011 at 07:24:39PM -0700, David Hendricks wrote:
On Wed, Jun 8, 2011 at 5:16 PM, Peter Stuge pe...@stuge.se wrote:
Paul Menzel wrote:
http://review.coreboot.org/12
opening that URL I see
, three updates
to i945 GMA: restore tft brightness from cmos spawned three different
threads within the span of 10 minutes. It has the same effect on my gmail
inbox as it does on the mailing list archive.
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David Hendricks (dhendrix)
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the
possibility that ASRock changed SPD addressing between board revisions...
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On Sun, Jul 17, 2011 at 12:38 PM, Andrew Bolster m...@andrewbolster.infowrote:
Tom,
Thank you for your response. I'll investigate the SPI angle. Is there any
structure for collecting information like this within the coreboot community
about specific boards for those of us who are more soft
On Tue, Aug 9, 2011 at 5:40 AM, Dsouza, Malcolm
malcolm.dso...@igatepatni.com wrote:
**
1. I am trying to work out an overview of the changes required for a
start; a bird’s eye view of what the changes could turn out to be. What is
the best approach for this?
As Stefan and Corey
On Tue, Aug 30, 2011 at 7:44 PM, Cui Lei neverforget_2...@163.com wrote:
Hi all, I know TPM was supported by FreeBIOS and the FreeBIOS was turned
into linuxBIOS , now linuxBIOS is called coreboot. But it seems that
coreboot now does not provide the TPM support, may be I lost in the source
Unfortunately, as a consumer there isn't a whole lot that can be done. It's
sort of like trying to buy a PC with Linux instead of Windows -- Due to
volume, the cheapest and most readily-available hardware is ironically
likely to have the Microsoft tax built into the pricetag. Similarly, nearly
all
On Sat, Sep 10, 2011 at 1:25 PM, Niklas Cholmkvist towards...@gmail.comwrote:
On the main page http://www.coreboot.org/ which redirects to
http://www.coreboot.org/Welcome_to_coreboot there's lots of information
but I see no get coreboot anywhere. Maybe coreboot is still in its
infant stages
Plumbers Conference talk:
http://linuxplumbersconf.org/ocw/proposals/47
2010 Embedded Linux Conference talk:
http://elinux.org/images/b/b6/ARM_Device_Tree_Status_Report.pdf
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http
/ or another favorite
image hoster.
I'll hopefully upload them tonight (10 hours or so)
BTW -- try to peak under the southbridge heatsink if it's not too much of a
hassle.
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http
:
remote: New Changes:
remote: http://review.coreboot.org/1671 [DRAFT]
remote:
To ssh://dhend...@review.coreboot.org:29418/coreboot
* [new branch] HEAD - refs/drafts/master/test
--
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On Fri, Nov 2, 2012 at 7:42 PM, Peter Stuge pe...@stuge.se wrote:
David Hendricks wrote:
2012-11-02 16:03:59.026509 Running: git log HEAD^1..HEAD
Found topic 'test' from parsing changes.
Is it known how the finding is done?
From what I can tell, one of three ways:
- By default, it uses
Hello Siyuan,
You might find this webpage useful: http://www.phisch.org/website/efiboot/
Have you built Coreboot for your target mainboard or emulator? Coreboot can
load any ELF payload (Payload - Add a payload - An ELF executable payload
and provide the path to your payload).
I have not
On Wed, Dec 5, 2012 at 9:07 PM, WANG Siyuan wangsiyuanb...@gmail.comwrote:
On Wed, Dec 5, 2012 at 6:12 AM, David Hendricks dhend...@google.comwrote:
Hello Siyuan,
You might find this webpage useful:
http://www.phisch.org/website/efiboot/
No code are provided.
Perhaps you can contact
ex post facto, only without the
instructive (perhaps cautionary) early debugging parts. Thankfully this is
the coreboot mailing list, where ugly early debugging is a way of life :-)
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git log.
Actually, I think it would look kind of ugly to do git log src/arch/x86
and see every commit cluttered with some cookie-cutter prefix.
/my $0.02.
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was changed?
- Can we make Jenkins send less verbose messages to the IRC channel so that
it sends out one (instead of two) brief messages indicating a patch's
success or failure?
Any other thoughts?
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On Thu, Jan 31, 2013 at 2:24 PM, Paul Menzel
paulepan...@users.sourceforge.net wrote:
Am Mittwoch, den 30.01.2013, 21:47 +0100 schrieb Peter Stuge:
David Hendricks wrote:
If you wish to focus only on a particular part of the codebase
It's more about getting an overview of what has
/mailman/listinfo/coreboot
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On Wed, Feb 6, 2013 at 3:01 PM, Peter Stuge pe...@stuge.se wrote:
David Hendricks wrote:
David Hendricks (dhend...@chromium.org) just uploaded a new patch set
to gerrit, which you can find at http://review.coreboot.org/2297
-gerrit
commit b115b35c581af7892739afd7c4aaf2250e260f51
and then
iterating makes a great deal of sense.
/my $0.02
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with this model, but in general I
suspect it's best to simply accept the ugly parts rather than diverge from
whatever AMD uses internally.
For more info about AGESA/CIMX and coreboot, see
http://blogs.amd.com/work/2011/02/28/technical-details-coreboot/
--
David Hendricks (dhendrix)
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is on the display, such
as VGABIOS output or the GUI for your OS.
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On Tue, Mar 19, 2013 at 3:41 PM, Paul Menzel
paulepan...@users.sourceforge.net wrote:
Dear coreboot folks,
following up on Ron’s comment to Gerrit item(?) 2695 [1]
We can't break out each and every vendor TLA (Three Letter
Acronym) or we'll be here for years. I understand
, but it seems the board support is present:
http://review.coreboot.org/gitweb?p=coreboot.git;a=tree;f=src/mainboard/amd/parmer;h=468c7303dd73cc6f211997024ad7849d6a7fc8fa;hb=HEAD
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My first intuition is to make clean and rm -f .xcompile, then attempt
to make again. You should not need to make crossgcc manually.
On Wed, Apr 10, 2013 at 10:48 PM, Pradish M P, ERS, HCLTech
pradis...@hcl.com wrote:
Dear coreboot folks
i downloaded the latest source code form coreboot.org
case?
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customization. So in that case it's useful to have a
framework which is flexible enough to account for differences in CPU
implementation, mainboard components, and overall product design.
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are
reading this and would like to see support for it in flashrom.
--
Kind regards/Mit freundlichen Grüßen, Stefan Tauner
___
flashrom mailing list
flash...@flashrom.org
http://www.flashrom.org/mailman/listinfo/flashrom
--
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On Mon, Jun 3, 2013 at 1:57 PM, Alex G. mr.nuke...@gmail.com wrote:
On 06/03/2013 03:10 PM, Oliver Schinagl wrote:
On 06/03/13 16:03, Denis 'GNUtoo' Carikli wrote:
Hi,
On Sun, 2 Jun 2013 20:54:04 -0500
slhac tivistslhactiv...@gmail.com wrote:
Which supported laptop is the most
installed on all Chromebooks.
Is there information about where the spi chips can be found?
Hmmm, I don't know off-hand :-/ If not, we can augment existing pics on the
site you found or get some new ones.
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?
That would be nice! I usually just click on a patch and follow its Depends
On link...
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by changing the SPI address and doing something while flashrom
was running. If that happened, your image may be corrupt and will need to
get a new firmware image from Intel's website and flash it instead.
Good luck!
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coreboot
/CloudAndComputingIC/SuperIO/SuperIOforDesktopandIPC/Documents/W83627UHG_NCT6627UD.pdf
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+# which is much faster on some CPUs.
+ramstage-y += memmove_old.c
+romstage-y += memmove_old.c
+smm-y += memmove_old.c
+else
+ramstage-y += memmove.c
+romstage-y += memmove.c
+smm-y += memmove.c
+endif
+
--
David Hendricks (dhendrix)
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--
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On Fri, Aug 16, 2013 at 2:19 AM, Luke Leighton
luke.leigh...@pathintel.comwrote:
On 16 August 2013 00:16, David Hendricks dhend...@google.com wrote:
Hi Luke,
You may be in luck -- That chipset is similar to a couple others which
are
already supported for the Stumpy and Lumpy ChromeOS
;a=blob_plain;f=src/cpu/samsung/exynos5420/dmc_init_ddr3.c;hb=refs/heads/chromeos-2013.04
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On Mon, Aug 26, 2013 at 12:47 PM, David Hendricks dhend...@google.comwrote:
On Mon, Aug 26, 2013 at 1:13 AM, Patrick Georgi patr...@georgi-clan.dewrote:
Am 26.08.2013 09:12, schrieb Mohit Gupta:
After that I get stuck completely mainly because of RAM initialization
steps as per JEDEC. I am
,
it makes sense to avoid confusing them with the traditional CPU/NB/SB
system architecture.
If you add the src/soc directory, you can move src/cpu/{armltd,ti} into it
as well. We can wait until the next large upstreaming for Exynos stuff
before moving it.
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Systems
it up:
http://www.phoronix.com/scan.php?page=news_itempx=MTI4ODU
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,
is Win7 or Win8 supported?
Win7 has been booted successfully, along with others:
http://www.coreboot.org/SeaBIOS#Windows
2.How to build/create or customize the OS images?
You should not need to customize the OS images.
--
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc
On Sun, Nov 3, 2013 at 11:47 AM, Alex mr.nuke...@gmail.com wrote:
On 11/02/2013 01:57 PM, ron minnich wrote:
[...] If you really want a system you
can trust a bit more, get a Chromebook. The amount of work done in
Chromebooks to protect it is extensive and extends beyond the 386
firmware
you pushed [2].
Thanks,
Paul
[2] http://review.coreboot.org/2998
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David Hendricks (dhendrix)
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that
developers are not bypassing the script and pushing bad results into the
board-status repository, of course)
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is in the blobs repo) that is run before coreboot. We
can only use a timer which is initialized in coreboot's bootblock on this
SoC, so counting begins a few microseconds after coreboot begins.
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David Hendricks (dhendrix)
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to be a
wonderful idea, one that I'd love to see happen some day.
ron
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David Hendricks (dhendrix)
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http
boards we support, that's another
matter.
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David Hendricks (dhendrix)
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On Dec 29, 2013 7:17 PM, ron minnich rminn...@gmail.com wrote:
The functions are wrong in two ways.
on the x86 side, the addr should be a void *. Had we done this long
ago we would have caught some bugs.
On the ARM side, the addr should be first, not last, to be consistent
with other addrs
On Sun, Dec 29, 2013 at 5:06 PM, David Collier-Brown davecb...@gmail.comwrote:
May I request you loudly announce how one checksums one's coreboot,
and in principle other BIOSes, so that one can see if anyone has changed
firmware critical to one's security.
Depends... In general this is not
@coreboot.org
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David Hendricks (dhendrix)
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developer in Munich already.
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David Hendricks (dhendrix)
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On Fri, Jan 10, 2014 at 4:58 PM, mrnuke mr.nuke...@gmail.com wrote:
##
## This file is part of the coreboot project.
##
## Copyright (C) 2014 Alexandru Gagniuc em...@addr.ess
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General
the bootloader doesn't need to be bloated with unnecessary
drivers and tools, and development is focused where it should be.
Perhaps we can call this LinuxBIOS :-)
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David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
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