Hi Martin,
On Tue, Aug 30, 2022 at 03:18:51PM +0300, Martin-??ric Racine wrote:
> On Tue, Aug 30, 2022 at 3:00 PM Peter Zijlstra wrote:
> > On Tue, Aug 30, 2022 at 02:42:04PM +0300, Martin-??ric Racine wrote:
> > > On Fri, Aug 19, 2022 at 3:15 PM Peter Zijlstra
> > > wrote:
> > > >
> > > > On
On Tue, Aug 30, 2022 at 3:00 PM Peter Zijlstra wrote:
> On Tue, Aug 30, 2022 at 02:42:04PM +0300, Martin-Éric Racine wrote:
> > On Fri, Aug 19, 2022 at 3:15 PM Peter Zijlstra wrote:
> > >
> > > On Fri, Aug 19, 2022 at 01:38:27PM +0200, Ben Hutchings wrote:
> > >
> > > > So that puts the whole
On Tue, Aug 30, 2022 at 02:42:04PM +0300, Martin-Éric Racine wrote:
> Greetings,
>
> On Fri, Aug 19, 2022 at 3:15 PM Peter Zijlstra wrote:
> >
> > On Fri, Aug 19, 2022 at 01:38:27PM +0200, Ben Hutchings wrote:
> >
> > > So that puts the whole __FILL_RETURN_BUFFER inside an alternative, and
> > >
Greetings,
On Fri, Aug 19, 2022 at 3:15 PM Peter Zijlstra wrote:
>
> On Fri, Aug 19, 2022 at 01:38:27PM +0200, Ben Hutchings wrote:
>
> > So that puts the whole __FILL_RETURN_BUFFER inside an alternative, and
> > we can't have nested alternatives. That's unfortunate.
>
> Well, both alternatives
On Fri, Aug 19, 2022 at 01:38:27PM +0200, Ben Hutchings wrote:
> So that puts the whole __FILL_RETURN_BUFFER inside an alternative, and
> we can't have nested alternatives. That's unfortunate.
Well, both alternatives end with the LFENCE instruction, so I could pull
it out and do two consequtive
On Fri, Aug 19, 2022 at 10:47:21AM +0200, Peter Zijlstra wrote:
> On Fri, Aug 19, 2022 at 02:33:08AM +0200, Ben Hutchings wrote:
> > From: Ben Hutchings
> >
> > The mitigation for PBRSB includes adding LFENCE instructions to the
> > RSB filling sequence. However, RSB filling is done on some
On Fri, 2022-08-19 at 13:01 +0200, Peter Zijlstra wrote:
> On Fri, Aug 19, 2022 at 10:47:21AM +0200, Peter Zijlstra wrote:
> > On Fri, Aug 19, 2022 at 02:33:08AM +0200, Ben Hutchings wrote:
> > > From: Ben Hutchings
> > >
> > > The mitigation for PBRSB includes adding LFENCE instructions to the
On Fri, Aug 19, 2022 at 2:01 PM Peter Zijlstra wrote:
> I'm not entirly sure what to do here. On the one hand, it's 32bit, so
> who gives a crap, otoh we shouldn't break these ancient chips either I
> suppose.
This is something that I've repeatedly had to bring up, whenever
something breaks
On Fri, 2022-08-19 at 10:47 +0200, Peter Zijlstra wrote:
> On Fri, Aug 19, 2022 at 02:33:08AM +0200, Ben Hutchings wrote:
> > From: Ben Hutchings
> >
> > The mitigation for PBRSB includes adding LFENCE instructions to the
> > RSB filling sequence. However, RSB filling is done on some older CPUs
On Fri, Aug 19, 2022 at 02:33:08AM +0200, Ben Hutchings wrote:
> From: Ben Hutchings
>
> The mitigation for PBRSB includes adding LFENCE instructions to the
> RSB filling sequence. However, RSB filling is done on some older CPUs
> that don't support the LFENCE instruction.
>
Wait; what? There
From: Ben Hutchings
The mitigation for PBRSB includes adding LFENCE instructions to the
RSB filling sequence. However, RSB filling is done on some older CPUs
that don't support the LFENCE instruction.
Define and use a BARRIER_NOSPEC macro which makes the LFENCE
conditional on
The mitigation for PBRSB includes adding LFENCE instructions to the
RSB filling sequence. However, RSB filling is done on some older CPUs
that don't support the LFENCE instruction.
Define and use a BARRIER_NOSPEC macro which makes the LFENCE
conditional on X86_FEATURE_LFENCE_RDTSC, like the
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