This is the format used by the bootloader framebuffer on Apple ARM64
platforms.
Reviewed-by: Thomas Zimmermann
Signed-off-by: Hector Martin
---
drivers/gpu/drm/tiny/simpledrm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tiny/simpledrm.c
Add XRGB emulation support for devices that can only do XRGB2101010.
This is chiefly useful for simpledrm on Apple devices where the
bootloader-provided framebuffer is 10-bit.
Signed-off-by: Hector Martin
---
drivers/gpu/drm/drm_format_helper.c | 64 +
This code is required for both simplefb and simpledrm, so let's move it
into the OF core instead of having it as an ad-hoc initcall in the
drivers.
Acked-by: Thomas Zimmermann
Signed-off-by: Hector Martin
---
drivers/of/platform.c | 4
drivers/video/fbdev/simplefb.c | 21
Hi DRM folks,
This short series makes simpledrm work on Apple M1 (including Pro/Max)
platforms the way simplefb already does, by adding XRGB2101010 support
and making it bind to framebuffers in /chosen the same way simplefb
does.
This avoids breaking the bootloader-provided framebuffer console
syzbot has found a reproducer for the following issue on:
HEAD commit:6f513529296f Merge tag 'for-5.16-rc4-tag' of git://git.ker..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=16499fc5b0
kernel config:
Convert into YAML format into format, which can be validated.
Changes:
- drop panel from example
Signed-off-by: David Heidelberg
---
v2:
- rename patch
- drop possibility for only one compatible string
- add patch for adding compatible to the PX30 dtsi
DCSS can not be built without the DRM_KMS_HELPERs being available.
Select this symbol to disallow this invalid configuration.
Signed-off-by: Lucas Stach
---
drivers/gpu/drm/imx/dcss/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/imx/dcss/Kconfig
This has been pulled in via some other include before, which is no
longer true.
Signed-off-by: Lucas Stach
---
drivers/gpu/drm/imx/dcss/dcss-kms.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/imx/dcss/dcss-kms.c
b/drivers/gpu/drm/imx/dcss/dcss-kms.c
index
On 2021-12-12 00:49:09, Dmitry Baryshkov wrote:
> On Sun, 12 Dec 2021 at 00:35, Marijn Suijten
> wrote:
> > [..]
> > On this note, does it perhaps make more sense to call the "internal"
> > _dpu_encoder_phys_cmd_wait_for_idle function directly, instead of going
> > through the "public"
On Sun, 12 Dec 2021 at 00:35, Marijn Suijten
wrote:
>
> On 2021-12-09 18:02:40, AngeloGioacchino Del Regno wrote:
> > Il 02/10/21 00:33, Dmitry Baryshkov ha scritto:
> > > On 11/09/2021 19:39, AngeloGioacchino Del Regno wrote:
> > >> [..]
> > > I've compared this with the MDP5 driver, where we
From: Anton Bambura
LQ101R1SX03 is compatible with LQ101R1SX01 from software perspective,
document it. The LQ101R1SX03 is a newer revision of LQ101R1SX01, it has
minor differences in hardware pins in comparison to the older version.
The newer version of the panel can be found on Android tablets,
From: Svyatoslav Ryhel
Add definition of the HannStar HSD101PWW2 Rev0-A00/A01 LCD
SuperIPS+ HD panel.
Signed-off-by: Svyatoslav Ryhel
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/panel/panel-simple.c | 28
1 file changed, 28 insertions(+)
diff --git
From: Svyatoslav Ryhel
Add HannStar HSD101PWW2 10.1" WXGA (1280x800) TFT-LCD LVDS panel
to the list of compatibles.
Acked-by: Rob Herring
Signed-off-by: Svyatoslav Ryhel
Signed-off-by: Dmitry Osipenko
---
.../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++
1 file
This series adds support for Sharp LQ101R1SX03 and HannStar HSD101PWW2
display panels that are used by Asus Transformer tablets, which we're
planning to support since 5.17 kernel.
Changelog:
v2: - Added ack from Rob Herring to the HSD101PWW2 binding.
- Updated LQ101R1SX01 binding, like it
On 2021-12-09 18:02:40, AngeloGioacchino Del Regno wrote:
> Il 02/10/21 00:33, Dmitry Baryshkov ha scritto:
> > On 11/09/2021 19:39, AngeloGioacchino Del Regno wrote:
> >> [..]
> > I've compared this with the MDP5 driver, where we always wait for PP_DONE
> > interrupt. Would it be enough to
Testing the stealing of guc ids is hard from user space as we have 64k
guc_ids. Add a selftest, which artificially reduces the number of guc
ids, and forces a steal. Description of test below.
The test creates a spinner which is used to block all subsequent
submissions until it completes. Next, a
A full GT reset can race with the last context put resulting in the
context ref count being zero but the destroyed bit not yet being set.
Remove GEM_BUG_ON in scrub_guc_desc_for_outstanding_g2h that asserts the
destroyed bit must be set in ref count is zero.
Reviewed-by: Daniele Ceraolo Spurio
Let's be paranoid and kick the G2H tasklet, which dequeues messages, if
G2H credits are exhausted.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
Print CT state (H2G + G2H head / tail pointers, credits) on CT
deadlock.
v2:
(John Harrison)
- Add units to debug messages
Reviewed-by: John Harrison
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 9 +
1 file changed, 9 insertions(+)
diff --git
Previously assigned whole guc_id structure (list, spin lock) which is
incorrect, only assign the guc_id.id.
Fixes: 0f7976506de61 ("drm/i915/guc: Rework and simplify locking")
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
1
From: John Harrison
While attempting to debug a CT deadlock issue in various CI failures
(most easily reproduced with gem_ctx_create/basic-files), I was seeing
CPU deadlock errors being reported. This were because the context
destroy loop was blocking waiting on H2G space from inside an IRQ
s/ce/cn/ when grabbing guc_state.lock before calling
clr_context_registered.
Fixes: 0f7976506de61 ("drm/i915/guc: Rework and simplify locking")
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 ++--
1 file changed, 2
Patches 1 & 2 address bugs in stealing of guc_ids and patch 7 tests this
path.
Patches 4-6 address some issues with the CTs exposed by the selftest in
patch 7. Basically if a lot of contexts were all deregistered all at
once, the CT channel could deadlock.
Patch 3 is a small fix that is already
tree: git://anongit.freedesktop.org/drm-intel topic/core-for-CI
head: 4c82fd0506b4cc196a375d1200361fb0c5439acd
commit: b3acf17eafd473e6e8f8f7c5ec7040efaaff22b8 [16/25] Revert "drm/i915:
Don't select BROKEN"
config: powerpc64-randconfig-r015-20211210
compiler: clang version 14.0.0
tree: git://anongit.freedesktop.org/drm-intel topic/core-for-CI
head: 4c82fd0506b4cc196a375d1200361fb0c5439acd
commit: b3acf17eafd473e6e8f8f7c5ec7040efaaff22b8 [16/25] Revert "drm/i915:
Don't select BROKEN"
config: powerpc-randconfig-r035-20211210
compiler: powerpc-linux-gcc (GCC) 11.2.0
On 2021-12-09 11:46 a.m., Michel Dänzer wrote:
From: Michel Dänzer
Move code using the Pipe struct to a new helper function.
Works around[0] this warning (resulting in failure to build a RHEL debug
kernel with Werror enabled):
Hi David,
Am Montag, 6. Dezember 2021, 22:26:50 CET schrieb David Heidelberg:
> Convert into YAML format into format, which can be validated.
>
> Changes:
> - drop panel from example
the patch subject is strange, talking about a "power domain node".
That needs a fix.
Some more things below.
On 09.12.21 11:23, Christian König wrote:
Always waiting for the exclusive fence resulted on some performance
regressions. So try to wait for the shared fences first, then the
exclusive fence should always be signaled already.
v2: fix incorrectly placed "(", add some comment why we do this.
On Fri, Dec 10, 2021 at 07:54:34PM -0500, Felix Kuehling wrote:
> Do you actually need to restore the exact boot-up mode? If you have the same
> framebuffer memory layout (width, height, bpp, stride) the precise display
> timing doesn't really matter. So we "just" need to switch to a mode that's
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