Daniel Stone (1):
drm/atomic: Stable sort for atomic request de-duplication
Dylan Baker (9):
meson: use dictionary kwargs
meson: add override_dependency when possible
meson: switch the meson builtin for symbol visiblity
meson: switch to cc.get_supported_arguments
On 16.02.2022 10:35, Javier Martinez Canillas wrote:
On 2/16/22 10:25, Jani Nikula wrote:
[snip]
I actually wrote said follow-up patches and they were ready to go, but
when I was trying to come up with the right "Fixes" tag I found commit
b792e64021ec ("drm: no need to check return value
On 15/02/2022 16:39, Ceraolo Spurio, Daniele wrote:
On 2/15/2022 1:09 AM, Tvrtko Ursulin wrote:
On 15/02/2022 01:11, Daniele Ceraolo Spurio wrote:
Move initialization of submission-related spinlock, lists and workers to
init_early. This fixes an issue where if the GuC init fails we might
On Tue, 15 Feb 2022 at 16:37, Simon Ser wrote:
>
> On Tuesday, February 15th, 2022 at 15:38, Emil Velikov
> wrote:
>
> > On Tue, 15 Feb 2022 at 13:55, Simon Ser wrote:
> > >
> > > On Tuesday, February 15th, 2022 at 13:04, Emil Velikov
> > > wrote:
> > >
> > > > Greetings everyone,
> > > >
>
On Wed, Feb 16, 2022 at 09:31:03AM +0100, David Hildenbrand wrote:
> On 16.02.22 03:36, Alistair Popple wrote:
> > On Wednesday, 16 February 2022 1:03:57 PM AEDT Jason Gunthorpe wrote:
> >> On Wed, Feb 16, 2022 at 12:23:44PM +1100, Alistair Popple wrote:
> >>
> >>> Device private and device
On Wed, Feb 09, 2022 at 11:19:27AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make sure we don't assign an error pointer to crtc_state->mode_blob
> as that will break all kinds of places that assume either NULL or a
> valid pointer (eg. drm_property_blob_put()).
>
> Reported-by:
On Wed, Feb 16, 2022 at 01:39:33PM +0300, Dmitry Osipenko wrote:
> 09.02.2022 12:53, Sascha Hauer пишет:
> > +static void vop2_plane_atomic_update(struct drm_plane *plane, struct
> > drm_atomic_state *state)
> > +{
> > + struct drm_plane_state *pstate = plane->state;
> > + struct drm_crtc
On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> From: Jouni Högander
>
> Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
> port. Correct offset is 0x64C14.
Why is it PHY_E and not PHY_F?
>
> Fix this by handling PHY_E port seprately.
>
> Signed-off-by: Matt
On Tue, 15 Feb 2022, Andy Shevchenko wrote:
> On Tue, Feb 15, 2022 at 07:14:49PM +0200, Jani Nikula wrote:
>> On Tue, 15 Feb 2022, Andy Shevchenko
>> wrote:
>> > It's hard to parse for-loop which has some magic calculations inside.
>> > Much cleaner to use while-loop directly.
>>
>> I assume
Fix a misspelling of "palette" in a structure member.
Signed-off-by: Geert Uytterhoeven
---
drivers/video/fbdev/au1100fb.c | 2 +-
drivers/video/fbdev/au1100fb.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/fbdev/au1100fb.c
Fix various grammar mistakes in the kerneldoc comments documenting the
drm_mode_fb_cmd2 structure:
- s/is/are/,
- s/8 bit/8-bit/.
Signed-off-by: Geert Uytterhoeven
---
include/uapi/drm/drm_mode.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Fix various spelling and grammar mistakes in the kerneldoc comments
documenting the offsets member in the drm_framebuffer structure:
- s/laytou/layout/,
- Add missing "is",
- s/it/its/.
Signed-off-by: Geert Uytterhoeven
---
include/drm/drm_framebuffer.h | 8
1 file changed, 4
Fix a misspelling of "palette" in a comment.
Signed-off-by: Geert Uytterhoeven
---
include/uapi/linux/fb.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/uapi/linux/fb.h b/include/uapi/linux/fb.h
index 4c14e8be7267761b..3a49913d006c9bf6 100644
---
Fix various grammar mistakes in the kerneldoc comments documenting the
drm_mode_fb_cmd2 structure:
- s/is/are/,
- s/8 bit/8-bit/.
Signed-off-by: Geert Uytterhoeven
---
include/uapi/drm/drm_mode.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
On Wed, Feb 16, 2022 at 11:02:06AM +0200, Jani Nikula wrote:
> On Wed, 16 Feb 2022, Jiapeng Chong wrote:
> > Eliminate the follow smatch warning:
> >
> > drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:4640
> > guc_create_virtual() warn: assigning (-2) to unsigned variable
> >
On Tue, 15 Feb 2022, Doug Anderson wrote:
> Hi,
>
> On Tue, Feb 15, 2022 at 2:20 PM Andrzej Hajda wrote:
>>
>> On 15.02.2022 23:09, Javier Martinez Canillas wrote:
>> > Hello Doug,
>> >
>> > On 2/5/22 01:13, Douglas Anderson wrote:
>> >
>> > [snip]
>> >
>> >> +static void
On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
> On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> > From: Jouni Högander
> >
> > Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
> > port. Correct offset is 0x64C14.
>
> Why is it PHY_E and not PHY_F?
On 2/16/22 10:25, Jani Nikula wrote:
[snip]
>>
>> I actually wrote said follow-up patches and they were ready to go, but
>> when I was trying to come up with the right "Fixes" tag I found commit
>> b792e64021ec ("drm: no need to check return value of debugfs_create
>> functions"). So what's
On 2/16/22 09:40, Geert Uytterhoeven wrote:
> Fix a misspelling of "palette" in a structure member.
>
> Signed-off-by: Geert Uytterhoeven
applied.
Thanks!
Helge
> ---
> drivers/video/fbdev/au1100fb.c | 2 +-
> drivers/video/fbdev/au1100fb.h | 2 +-
> 2 files changed, 2 insertions(+), 2
Am 16.02.22 um 01:38 schrieb Felix Kuehling:
Reference:
https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arrays
CC: Changcheng Deng
Signed-off-by: Felix Kuehling
Reviewed-by: Christian König
---
include/uapi/linux/kfd_ioctl.h | 2 +-
1 file
On Mon, 14 Feb 2022 02:05:30 +, cgel@gmail.com wrote:
> From: "Minghao Chi (CGEL ZTE)"
>
> Use of_device_get_match_data() to simplify the code.
>
>
Applied to drm/drm-misc (drm-misc-next).
Thanks!
Maxime
On Wed, Feb 16, 2022 at 09:36:02AM +, Hogander, Jouni wrote:
> On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
> > On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> > > From: Jouni Högander
> > >
> > > Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
>
On Wed, 16 Feb 2022, Tvrtko Ursulin wrote:
> On 16/02/2022 09:19, Ville Syrjälä wrote:
>> On Wed, Feb 16, 2022 at 11:02:06AM +0200, Jani Nikula wrote:
>>> On Wed, 16 Feb 2022, Jiapeng Chong wrote:
Eliminate the follow smatch warning:
Eliminate the follow smatch warning:
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:4640
guc_create_virtual() warn: assigning (-2) to unsigned variable
've->base.instance'.
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:4641
guc_create_virtual() warn: assigning (-2) to unsigned variable
On Wed, Feb 16, 2022 at 9:55 AM Jani Nikula wrote:
> On Tue, 15 Feb 2022, Andy Shevchenko
> wrote:
> > On Tue, Feb 15, 2022 at 07:14:49PM +0200, Jani Nikula wrote:
> >> On Tue, 15 Feb 2022, Andy Shevchenko
> >> wrote:
> >> > It's hard to parse for-loop which has some magic calculations
On Wed, 16 Feb 2022, Jiapeng Chong wrote:
> Eliminate the follow smatch warning:
>
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:4640
> guc_create_virtual() warn: assigning (-2) to unsigned variable
> 've->base.instance'.
>
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:4641
>
On Mon, Feb 14, 2022 at 02:37:05PM +0100, Javier Martinez Canillas wrote:
> Pull the per-line conversion logic into a separate helper function.
>
> This will allow to do line-by-line conversion in other helpers that
> convert to a gray8 format.
>
> Suggested-by: Thomas Zimmermann
>
On Mon, Feb 14, 2022 at 02:37:07PM +0100, Javier Martinez Canillas wrote:
> This adds a DRM driver for SSD1305, SSD1306, SSD1307 and SSD1309 Solomon
> OLED display controllers.
>
> It's only the core part of the driver and a bus specific driver is needed
> for each transport interface supported
On Mon, Feb 14, 2022 at 02:37:06PM +0100, Javier Martinez Canillas wrote:
> Add support to convert from XR24 to reversed monochrome for drivers that
> control monochromatic display panels, that only have 1 bit per pixel.
>
> The function does a line-by-line conversion doing an intermediate step
>
On Mon, Feb 14, 2022 at 02:37:08PM +0100, Javier Martinez Canillas wrote:
> The ssd130x driver only provides the core support for these devices but it
> does not have any bus transport logic. Add a driver to interface over I2C.
>
> Signed-off-by: Javier Martinez Canillas
> Reviewed-by: Andy
To initialize register NWL_DSI_IRQ_MASK, it's enough to write it
only once in function nwl_dsi_init_interrupts().
Signed-off-by: Liu Ying
---
drivers/gpu/drm/bridge/nwl-dsi.c | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c
Il 15/02/22 23:32, Alyssa Rosenzweig ha scritto:
I'd do the oneliner changing it to 5 and be done with it. That being
said, we have plenty of examples of doing this both ways, so whatever
makes people happy.
Excellent, that's the patch I wrote originally :-)
Dropping this patch, unless Angelo
Add helper functions for calculating FRL capacity and DFM
requirements with given compressed bpp.
v2: Fixed:
-Build warnings/errors: Removed unused variables.
-Checkpatch warnings.
Signed-off-by: Ankit Nautiyal
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/drm_frl_dfm_helper.c | 303
Sparse warns about the following cast in the function
falcon_copy_firmware_image() ...
drivers/gpu/drm/tegra/falcon.c:66:27: warning: cast to restricted __le32
Fix this by casting the firmware data array to __le32 instead of u32.
Signed-off-by: Jon Hunter
---
drivers/gpu/drm/tegra/falcon.c |
On Mon, Feb 14, 2022 at 02:39:35PM +0100, Javier Martinez Canillas wrote:
> The ssd130x DRM driver also makes use of this Device Tree binding to allow
> existing users of the fbdev driver to migrate without the need to change
> their Device Trees.
>
> Add myself as another maintainer of the
On Mon, Feb 14, 2022 at 02:39:15PM +0100, Javier Martinez Canillas wrote:
> To make sure that tools like the get_maintainer.pl script will suggest
> to Cc me if patches are posted for this driver.
>
> Also include the Device Tree binding for the old ssd1307fb fbdev driver
> since the new DRM
On 16/02/2022 09:19, Ville Syrjälä wrote:
On Wed, Feb 16, 2022 at 11:02:06AM +0200, Jani Nikula wrote:
On Wed, 16 Feb 2022, Jiapeng Chong wrote:
Eliminate the follow smatch warning:
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:4640
guc_create_virtual() warn: assigning (-2) to unsigned
Am 15.02.22 um 23:23 schrieb Vivek Kasireddy:
This iterator relies on drm_mm_first_hole() and drm_mm_next_hole()
functions to identify suitable holes for an allocation of a given
size by efficiently traversing the rbtree associated with the given
allocator.
It replaces the for loop in
Hi all,
On Tue, Feb 15, 2022 at 01:07:00PM -0600, Limonciello, Mario wrote:
> On 2/15/2022 01:29, Lukas Wunner wrote:
> > On Mon, Feb 14, 2022 at 06:01:50PM -0600, Mario Limonciello wrote:
> > > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
> > > drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 2
On Wed, Feb 16, 2022 at 9:34 AM Mika Westerberg
wrote:
>
> Hi all,
>
> On Tue, Feb 15, 2022 at 01:07:00PM -0600, Limonciello, Mario wrote:
> > On 2/15/2022 01:29, Lukas Wunner wrote:
> > > On Mon, Feb 14, 2022 at 06:01:50PM -0600, Mario Limonciello wrote:
> > > >
On 2/16/2022 08:44, Alex Deucher wrote:
On Wed, Feb 16, 2022 at 9:34 AM Mika Westerberg
wrote:
Hi all,
On Tue, Feb 15, 2022 at 01:07:00PM -0600, Limonciello, Mario wrote:
On 2/15/2022 01:29, Lukas Wunner wrote:
On Mon, Feb 14, 2022 at 06:01:50PM -0600, Mario Limonciello wrote:
Hi All
Hopefully I've cc'ed all those that have bashed this problem around previously,
or are otherwise linked to DRM bridges.
There have been numerous discussions around how DSI support is currently broken
as it doesn't support initialising the PHY to LP-11 and potentially the clock
lane to HS
DSI sink devices typically want the DSI host powered up and configured
before they are powered up. pre_enable is the place this would normally
happen, but they are called in reverse order from panel/connector towards
the encoder, which is the "wrong" order.
Add a new flag
On 2/14/22 14:37, Javier Martinez Canillas wrote:
> This patch series adds a DRM driver for the Solomon OLED SSD1305, SSD1306,
> SSD1307 and SSD1309 displays. It is a port of the ssd1307fb fbdev driver.
>
> Using the DRM fbdev emulation, all the tests from Geert Uytterhoeven repo
>
On 2022/2/16 21:46, Daniel Stone wrote:
On Wed, 9 Feb 2022 at 15:41, Sui Jingfeng <15330273...@189.cn> wrote:
On 2022/2/9 16:43, Maxime Ripard wrote:
More fundamentally (and this extends to the CMA, caching and VRAM stuff
you explained above), why can't the driver pick the right decision all
Hi,
When using a Lenovo dock, I often get this error message on dmesg:
[drm] *ERROR* mstb 57b5b857 port 1: DPCD read on addr 0x4b0 for
1 bytes NAKed
It's caused by fwupd which tries to read from /dev/drm_dp_aux4
I opened an issue on fwupd:
https://github.com/fwupd/fwupd/issues/4284
On Wed, Feb 16, 2022 at 02:11:54PM +, Hogander, Jouni wrote:
> On Wed, 2022-02-16 at 12:07 +0200, Ville Syrjälä wrote:
> > On Wed, Feb 16, 2022 at 09:36:02AM +, Hogander, Jouni wrote:
> > > On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
> > > > On Tue, Feb 15, 2022 at 11:21:54AM
On Wed, Feb 16, 2022 at 09:34:47PM +0800, Sui Jingfeng wrote:
> On 2022/2/10 00:16, Maxime Ripard wrote:
> > And, to reinstate, we already have a mechanism to set an EDID, and if it
> > wasn't an option, the DT is not the place to store an EDID blob.
>
> Hi,
>
>
> if DT is not the place to
On Wed, 2022-02-16 at 12:07 +0200, Ville Syrjälä wrote:
> On Wed, Feb 16, 2022 at 09:36:02AM +, Hogander, Jouni wrote:
> > On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
> > > On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> > > > From: Jouni Högander
> > > >
> > > >
On Wed, 16 Feb 2022 at 14:13, Sui Jingfeng <15330273...@189.cn> wrote:
> On 2022/2/16 21:46, Daniel Stone wrote:
> > Other systems have this limitation, and Mesa's 'kmsro' concept makes
> > this work transparently, as long as your driver can export dmabufs
> > when running in 'VRAM' mode.
>
> When
On Mon, Feb 14, 2022 at 06:50:36PM +0800, Sui Jingfeng wrote:
>
> On 2022/2/14 18:10, Maxime Ripard wrote:
> > On Sun, Feb 13, 2022 at 10:16:43PM +0800, Sui Jingfeng wrote:
> > > From: suijingfeng
> > >
> > > There is a display controller in loongson's LS2K1000 SoC and LS7A1000
> > > bridge
Hi Mark,
On Mon, 2022-02-07 at 16:14 +0100, Mark Jonas wrote:
> From: Leo Ruan
>
> This commit corrects the printing of the IPU clock error percentage if
> it is between -0.1% to -0.9%. For example, if the pixel clock requested
> is 27.2 MHz but only 27.0 MHz can be achieved the deviation is
On Wed, 9 Feb 2022 at 15:41, Sui Jingfeng <15330273...@189.cn> wrote:
> On 2022/2/9 16:43, Maxime Ripard wrote:
> > More fundamentally (and this extends to the CMA, caching and VRAM stuff
> > you explained above), why can't the driver pick the right decision all
> > the time and why would that be
On 2022/2/10 00:16, Maxime Ripard wrote:
And, to reinstate, we already have a mechanism to set an EDID, and if it
wasn't an option, the DT is not the place to store an EDID blob.
Hi,
if DT is not the place to store EDID blob, why nvidia can do that ?
output->edid =
The exact behaviour of DSI host controllers is not specified,
therefore define it.
Signed-off-by: Dave Stevenson
---
Documentation/gpu/drm-kms-helpers.rst | 7 +++
drivers/gpu/drm/drm_bridge.c | 38 +++
2 files changed, 45 insertions(+)
diff --git
On Wed, Feb 16, 2022 at 11:56:51AM -0500, Felix Kuehling wrote:
> In the case of DEVICE_COHERENT memory, the pfns correspond to real physical
> memory addresses. I don't think they have those PFN_DEV|PFN_MAP bits set.
So do DAX pages. The PTE flag does several things. As this would be
the first
09.02.2022 12:53, Sascha Hauer пишет:
> +static void vop2_plane_atomic_update(struct drm_plane *plane, struct
> drm_atomic_state *state)
> +{
> + struct drm_plane_state *pstate = plane->state;
> + struct drm_crtc *crtc = pstate->crtc;
> + struct vop2_win *win = to_vop2_win(plane);
> +
16.02.2022 14:22, Sascha Hauer пишет:
> On Wed, Feb 16, 2022 at 01:39:33PM +0300, Dmitry Osipenko wrote:
>> 09.02.2022 12:53, Sascha Hauer пишет:
>>> +static void vop2_plane_atomic_update(struct drm_plane *plane, struct
>>> drm_atomic_state *state)
>>> +{
>>> + struct drm_plane_state *pstate
On Sun, Feb 13, 2022 at 02:11:30AM +0800, Sui Jingfeng wrote:
>
> On 2022/2/10 00:16, Maxime Ripard wrote:
> > On Wed, Feb 09, 2022 at 10:38:41PM +0800, Sui Jingfeng wrote:
> > > On 2022/2/9 16:49, Maxime Ripard wrote:
> > > > On Fri, Feb 04, 2022 at 12:04:19AM +0800, Sui Jingfeng wrote:
> > > >
On 14/02/2022 17:06, Alyssa Rosenzweig wrote:
> On Mon, Feb 14, 2022 at 04:23:18PM +, Steven Price wrote:
>> On 11/02/2022 20:27, alyssa.rosenzw...@collabora.com wrote:
>>> From: Alyssa Rosenzweig
>>>
>>> Some Valhall GPUs require resets when encountering bus faults due to
>>> occlusion query
On 14/02/2022 17:01, Alyssa Rosenzweig wrote:
>>> Add the HW_FEATURE_CLEAN_ONLY_SAFE bit based on kbase. When I actually
>>> tried to port the logic from kbase, trivial jobs raised Data Invalid
>>> Faults, so this may depend on other coherency details. It's still useful
>>> to have the bit to
Hi, Dave & Daniel:
This includes:
1. Avoid EPROBE_DEFER loop with external bridge
Regards,
Chun-Kuang.
The following changes since commit e783362eb54cd99b2cac8b3a9aeac942e6f6ac07:
Linux 5.17-rc1 (2022-01-23 10:12:53 +0200)
are available in the git repository at:
Am 2022-02-15 um 21:01 schrieb Jason Gunthorpe:
On Tue, Feb 15, 2022 at 05:49:07PM -0500, Felix Kuehling wrote:
Userspace does
1) mmap(MAP_PRIVATE) to allocate anon memory
2) something to trigger migration to install a ZONE_DEVICE page
3) munmap()
Who decrements the refcout on the
On 2022/2/3 16:50, Krzysztof Kozlowski wrote:
On Thu, 3 Feb 2022 at 09:26, Sui Jingfeng <15330273...@189.cn> wrote:
From: suijingfeng
The display controller is a pci device, its vendor id is 0x0014
its device id is 0x7a06.
The same as your patch 3 - these are not bindings.
Best regards,
revise widebus timing engine programming and enable widebus feature base on chip
Kuogee Hsieh (2):
drm/msm/dpu: revise timing engine programming to support widebus
feature
drm/msm/dp: enable widebus feature for display port
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 14 -
Widebus feature will transmit two pixel data per pixel clock to interface.
Timing engine provides driving force for this purpose. This patch base
on HPG (Hardware Programming Guide) to revise timing engine register
setting to accommodate both widebus and non widebus application. Also
horizontal
Hi,
On Thu, Feb 10, 2022 at 3:58 AM Sankeerth Billakanti
wrote:
>
> Add support for the 14" sharp,lq140m1jw46 eDP panel.
>
> Signed-off-by: Sankeerth Billakanti
> ---
> 00 ff ff ff ff ff ff 00 4d 10 23 15 00 00 00 00
> 35 1e 01 04 a5 1f 11 78 07 de 50 a3 54 4c 99 26
> 0f 50 54 00 00 00 01 01 01
Hi,
On Wed, Feb 16, 2022 at 11:26 AM Doug Anderson wrote:
>
> Hi,
>
> On Thu, Feb 10, 2022 at 3:58 AM Sankeerth Billakanti
> wrote:
> >
> > Add support for sharp LQ140M1JW46 display panel. It is a 14" eDP panel
> > with 1920x1080 display resolution.
> >
> > Signed-off-by: Sankeerth Billakanti
Hi,
On Wed, Feb 16, 2022 at 11:29 AM Doug Anderson wrote:
>
> Hi,
>
> On Thu, Feb 10, 2022 at 3:58 AM Sankeerth Billakanti
> wrote:
> >
> > Add support for the 14" sharp,lq140m1jw46 eDP panel.
> >
> > Signed-off-by: Sankeerth Billakanti
> > ---
> > 00 ff ff ff ff ff ff 00 4d 10 23 15 00 00 00
On 16/02/2022 21:57, Abhinav Kumar wrote:
On 2/10/2022 2:34 AM, Vinod Koul wrote:
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
support by adding hw blocks for DSC
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
Somehow second patch of this series is not
On 2/10/2022 2:34 AM, Vinod Koul wrote:
Later gens of hardware have DSC bits moved to hw_ctl, so configure these
bits so that DSC would work there as well
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
Hi,
On Thu, Feb 10, 2022 at 3:58 AM Sankeerth Billakanti
wrote:
>
> Add support for sharp LQ140M1JW46 display panel. It is a 14" eDP panel
> with 1920x1080 display resolution.
>
> Signed-off-by: Sankeerth Billakanti
> Acked-by: Rob Herring
> Reviewed-by: Stephen Boyd
> ---
>
> Changes in v4:
SLPC unset param H2G only needs one parameter - the id of the
param.
Fixes: 025cb07bebfa ("drm/i915/guc/slpc: Cache platform frequency limits")
Suggested-by: Umesh Nerlige Ramappa
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 2 +-
1 file changed, 1
On Wed, 16 Feb 2022 10:09:14 -0800
Linus Torvalds wrote:
> Byungchul, could you fix those two issues? Some of your reports may
> well be entirely valid, but the hard-to-read hex offsets and the
> knowledge that at least some of them are confused about how
> prepare_to_wait -> wait actually works
On 2/16/2022 9:48 AM, Dmitry Baryshkov wrote:
On Wed, 16 Feb 2022 at 20:34, Kuogee Hsieh wrote:
Widebus feature will transmit two pixel data per pixel clock to interface.
Timing engine provides driving force for this purpose. This patch base
on HPG (Hardware Programming Guide) to revise
Widebus feature will transmit two pixel data per pixel clock to interface.
This feature now is required to be enabled to easy migrant to higher
resolution applications in future. However since some legacy chipsets
does not support this feature, this feature is enabled base on chip's
hardware
On Tue, Feb 15, 2022 at 10:37 PM Damien Le Moal
wrote:
>
> On 2/16/22 13:16, Byungchul Park wrote:
> > [2.051040] ===
> > [2.051406] DEPT: Circular dependency has been detected.
> > [2.051730] 5.17.0-rc1-00014-gcf3441bb2012 #2 Tainted: G
Hi,
On Tue, Feb 15, 2022 at 4:41 PM Brian Norris wrote:
>
> On Tue, Feb 15, 2022 at 3:46 PM Doug Anderson wrote:
> > On Tue, Feb 15, 2022 at 2:52 PM Brian Norris
> > wrote:
> > > It still makes me wonder what the point
> > > of the /dev/drm_dp_aux interface is though, because it seems like
>
在 2022/2/16 18:17, Sui Jingfeng 写道:
From: suijingfeng
The display controller is a pci device, its PCI vendor id is 0x0014
its PCI device id is 0x7a06.
1) In order to let the lsdc kms driver to know which chip the DC is
contained in, we add different compatible for different chip.
2)
On 2/10/2022 2:34 AM, Vinod Koul wrote:
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
support by adding hw blocks for DSC
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
Somehow second patch of this series is not showing up on patchwork in
your REPOST.
On 2/10/2022 2:34 AM, Vinod Koul wrote:
This adds SDM845 DSC blocks into hw_catalog
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
Reviewed-by: Abhinav Kumar
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 20 +++
1 file changed, 20 insertions(+)
diff
On 2/10/2022 2:34 AM, Vinod Koul wrote:
We need to configure the encoder for DSC configuration and calculate DSC
parameters for the given timing so this patch adds that support by
adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
Signed-off-by: Vinod Koul
Minor nit
Widebus feature will transmit two pixel data per pixel clock to interface.
This feature now is required to be enabled to easy migrant to higher
resolution applications in future. However since some legacy chipsets
does not support this feature, this feature is enabled base on chip's
hardware
To improve code readability, this patch replace BIT(x) with
correspond register bit define string
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git
Now we have the access to content of GuC ADS either using iosys_map
API or using a temporary buffer. Remove guc->ads_blob as there shouldn't
be updates using the bare pointer anymore.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele
In the other places in this function, guc->ads_map is being protected
from access when it's not yet set. However the last check is actually
about guc->ads_golden_ctxt_size been set before. These checks should
always match as the size is initialized on the first call to
guc_prep_golden_context(),
Use the saved ads_map to prepare the golden context. One difference from
the init context is that this function can be called before there is a
gem object (and thus the guc->ads_map) to calculare the size of the
golden context that should be allocated for that object.
So in this case the function
Now that the regset list is prepared, convert guc_mmio_reg_state_init()
to use iosys_map to copy the array to the final location and
initialize additional fields in ads.reg_state_list.
v2: Just use an offset instead of temporary iosys_map.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
In certain situations it's useful to be able to write to an
offset of the mapping. Add a dst_offset to iosys_map_memcpy_to().
Cc: Sumit Semwal
Cc: Christian König
Cc: Thomas Zimmermann
Cc: dri-devel@lists.freedesktop.org
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Lucas De Marchi
Use iosys_map to read fields from the dma_blob so access to IO and
system memory is abstracted away.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Atwood
---
Use iosys_map to write the policies update so access to IO and system
memory is abstracted away.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Atwood
---
Add a variant of shmem_read() that takes a iosys_map pointer rather
than a plain pointer as argument. It's mostly a copy __shmem_rw() but
adapting the api and removing the write support since there's currently
only need to use iosys_map as destination.
Reworking __shmem_rw() to share the
Now the map is saved during creation, so use it to initialize the
golden context, reading from shmem and writing to either system or IO
memory.
v2: Do not use a map iterator: add an offset to keep track of
destination
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Add helpers on top of iosys_map_read_field() /
iosys_map_write_field() functions so they always use the right
arguments and make code easier to read.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De
original: https://patchwork.freedesktop.org/series/99378/
v2: https://patchwork.freedesktop.org/series/99711/#rev1,
https://patchwork.freedesktop.org/series/99711/#rev2
Main changes from previous version:
- Unrelated patches to iosys-map conversion have landed
- Remove
Use iosys_map to write the fields ads.capture_*.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 10 +-
1 file changed, 5
Convert intel_guc_ads_create() and initialization to use iosys_map
rather than plain pointer and save it in the guc struct. This will help
with additional updates to the ads_blob after the
creation/initialization by abstracting the IO vs system memory.
Cc: Matt Roper
Cc: Thomas Hellström
Cc:
Use iosys_map_memset() to zero the private data as ADS may be either
on system or IO memory.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c |
Now that all the called functions from __guc_ads_init() are converted to
use ads_map, stop using ads_blob in __guc_ads_init().
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
Use iosys_map to write the fields system_info.mapping_table[][].
Since we already have the info_map around where needed, just use it
instead of going through guc->ads_map.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
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