On Wed, Sep 15, 2021 at 12:29:12PM -0700, John Harrison wrote:
On 9/15/2021 12:24, Belgaumkar, Vinay wrote:
On 9/14/2021 12:51 PM, Lucas De Marchi wrote:
The clflush calls here aren't doing anything since we are not writting
something and flushing the cache lines to be visible to GuC. Here the
On Mon, Sep 20, 2021 at 02:42:09PM -0700, Doug Anderson wrote:
> Hi,
>
> On Sat, Sep 18, 2021 at 1:29 PM Sam Ravnborg wrote:
> >
> > Hi Philip,
> > On Sat, Sep 18, 2021 at 10:21:17AM -0700, Philip Chen wrote:
> > > Implement the first version of AUX support, which will be useful as
> > > we
On Tuesday, 21 September 2021 6:05:30 AM AEST Sierra Guiza, Alejandro (Alex)
wrote:
>
> On 9/20/2021 3:53 AM, Alistair Popple wrote:
> > On Tuesday, 14 September 2021 2:16:01 AM AEST Alex Sierra wrote:
> >> In order to configure device public in test_hmm, two module parameters
> >> should be
https://bugzilla.kernel.org/show_bug.cgi?id=211277
--- Comment #66 from youling...@gmail.com ---
resume failed record video,
https://drive.google.com/drive/folders/1bWMC4ByGvudC9zBk-9Xgamz-shir0pqX?usp=sharing
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https://bugzilla.kernel.org/show_bug.cgi?id=211277
--- Comment #65 from youling...@gmail.com ---
(In reply to James Zhu from comment #63)
> (In reply to youling257 from comment #62)
> > (In reply to James Zhu from comment #61)
> > > (In reply to youling257 from comment #60)
> > > > Created
https://bugzilla.kernel.org/show_bug.cgi?id=211277
--- Comment #64 from youling...@gmail.com ---
Created attachment 298899
--> https://bugzilla.kernel.org/attachment.cgi?id=298899=edit
config-5.15.0-rc2-android-x86_64+
CONFIG_HSA_AMD=y
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On Mon, Sep 20, 2021 at 8:17 PM Tim Gardner wrote:
>
> Coverity complains of a resource leak in ga102_chan_new():
>
> CID 119637 (#7 of 7): Resource leak (RESOURCE_LEAK)
> 13. leaked_storage: Variable chan going out of scope leaks the storage it
> points to.
> 190return ret;
>
>
On 2021-09-15 10:36, Pekka Paalanen wrote:
> On Mon, 16 Aug 2021 15:37:23 +0200
> sebast...@sebastianwick.net wrote:
>
>> On 2021-08-16 14:40, Harry Wentland wrote:
>>> On 2021-08-16 7:10 a.m., Brian Starkey wrote:
On Fri, Aug 13, 2021 at 10:42:12AM +0530, Sharma, Shashank wrote:
On 2021-09-15 10:01, Pekka Paalanen wrote:> On Fri, 30 Jul 2021 16:41:29 -0400
> Harry Wentland wrote:
>
>> Use the new DRM RFC doc section to capture the RFC previously only
>> described in the cover letter at
>> https://patchwork.freedesktop.org/series/89506/
>>
>> v3:
>> * Add sections on
On 8/20/2021 15:44, Matthew Brost wrote:
Update parallel submit doc to point to i915_drm.h
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
Documentation/gpu/rfc/i915_parallel_execbuf.h | 122 --
Documentation/gpu/rfc/i915_scheduler.rst | 4 +-
2
On 8/20/2021 15:44, Matthew Brost wrote:
Introduce 'set parallel submit' extension to connect UAPI to GuC
multi-lrc interface. Kernel doc in new uAPI should explain it all.
IGT: https://patchwork.freedesktop.org/patch/447008/?series=93071=1
media UMD: link to come
Is this link still not
On 8/20/2021 15:44, Matthew Brost wrote:
Set number of engines before attempting to create contexts so the
function free_engines can clean up properly.
Fixes: d4433c7600f7 ("drm/i915/gem: Use the proto-context to handle create
parameters (v5)")
Signed-off-by: Matthew Brost
Cc:
---
From: Rob Clark
Slightly awkward to fish out the display_info when we aren't creating
own connector. But I don't see an obvious better way.
v2: Remove error return with NO_CONNECTOR flag
Signed-off-by: Rob Clark
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 39 ---
1
From: Rob Clark
For the brave new world of bridges not creating their own connectors, we
need to implement the max clock limitation via bridge->mode_valid()
instead of connector->mode_valid().
v2: Drop unneeded connector->mode_valid()
Signed-off-by: Rob Clark
Reviewed-by: Douglas Anderson
From: Rob Clark
For now, since we have a mix of bridges which support this flag, which
which do *not* support this flag, or work both ways, try it once with
NO_CONNECTOR and then fall back to the old way if that doesn't work.
Eventually we can drop the fallback path.
v2: Add missing
From: Rob Clark
Respin of https://www.spinics.net/lists/linux-arm-msm/msg92182.html with
the remaining 3 patches that are not yet merged.
At the end of this series, but drm/msm and ti-sn65dsi86 work in both
combinations, so the two bridge patches can be merged indepdendently of
the msm/dsi
On 8/20/2021 15:44, Matthew Brost wrote:
Display the workqueue status in debugfs for GuC contexts that are in
parent-child relationship.
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 51 ++-
1 file changed, 37 insertions(+), 14
On 8/20/2021 15:44, Matthew Brost wrote:
Update context and full GPU reset to work with multi-lrc. The idea is
parent context tracks all the active requests inflight for itself and
its' children. The parent context owns the reset replaying / canceling
its' -> its
requests as needed.
On Wed, Sep 08, 2021 at 11:02:14AM +0800, Cai Huoqing wrote:
> Fix indentation for the warning-
> wrong indentation: expected 10 but found 8 (indentation)
>
> Signed-off-by: Cai Huoqing
> ---
> .../devicetree/bindings/display/panel/ilitek,ili9341.yaml | 2 +-
> 1 file changed, 1
On Thu, Sep 16, 2021 at 2:31 AM Maxime Ripard wrote:
>
> Hi Dave, Daniel,
>
> Here's the first drm-misc-next PR for 5.16
>
> Thanks!
> Maxime
>
> drm-misc-next-2021-09-16:
> drm-misc-next for $kernel-version:
>
> UAPI Changes:
>
> Cross-subsystem Changes:
> - dma-buf: Avoid a warning with some
On 8/20/2021 15:44, Matthew Brost wrote:
The GuC must receive requests in the order submitted for contexts in a
parent-child relationship to function correctly. To ensure this, insert
a submit fence between the current request and last request submitted
for requests / contexts in a parent child
On 8/20/2021 15:44, Matthew Brost wrote:
Implement multi-lrc submission via a single workqueue entry and single
H2G. The workqueue entry contains an updated tail value for each
request, of all the contexts in the multi-lrc submission, and updates
these values simultaneously. As such, the tasklet
Hi,
On Sat, Sep 18, 2021 at 1:29 PM Sam Ravnborg wrote:
>
> Hi Philip,
> On Sat, Sep 18, 2021 at 10:21:17AM -0700, Philip Chen wrote:
> > Implement the first version of AUX support, which will be useful as
> > we expand the driver to support varied use cases.
> >
> > Signed-off-by: Philip Chen
Hi Sam,
On Sat, Sep 18, 2021 at 1:29 PM Sam Ravnborg wrote:
>
> Hi Philip,
> On Sat, Sep 18, 2021 at 10:21:17AM -0700, Philip Chen wrote:
> > Implement the first version of AUX support, which will be useful as
> > we expand the driver to support varied use cases.
> >
> > Signed-off-by: Philip
On 21/09/20 09:54AM, kernel test robot wrote:
>
> [auto build test ERROR on drm-exynos/exynos-drm-next]
> [also build test ERROR on tegra-drm/drm/tegra/for-next linus/master v5.15-rc2
> next-20210917]
I forgot to #include for those platforms and didn't notice
because I only tried to build for
The only usage of hdmi_8996_pll_ops is to assign its address to the ops
field in the clk_init_data struct, and the only usage of pll_init is to
assign its address to the init field in the clk_hw struct, both which
are pointers to const. Make them const to allow the compiler to put them
in
https://bugzilla.kernel.org/show_bug.cgi?id=211277
--- Comment #63 from James Zhu (jam...@amd.com) ---
(In reply to youling257 from comment #62)
> (In reply to James Zhu from comment #61)
> > (In reply to youling257 from comment #60)
> > > Created attachment 298889 [details]
> > > dmesg5.15.txt
>
On Thu, 2021-09-16 at 12:32 +0200, Hans de Goede wrote:
>
> I'm fine with refactoring this a bit and adding
> an intel_modeset_probe_defer() helper for this, I assume I should also
> move the vga_switcheroo_client_probe_defer(pdev) check there?
>
> As you suggested yourself in your reply to the
On Fri, Sep 17, 2021 at 02:59:42PM +0200, Alexandre Bailon wrote:
> This adds the device tree bindings for the APU DRM driver.
>
> Signed-off-by: Alexandre Bailon
> ---
> .../devicetree/bindings/gpu/mtk,apu-drm.yaml | 38 +++
> 1 file changed, 38 insertions(+)
> create mode
Hi Maxime,
Am Freitag, 17. September 2021, 20:09:25 CEST schrieb Maxime Ripard:
> By depending on devm_drm_panel_bridge_add(), devm_drm_of_get_bridge()
> introduces a circular dependency between the modules drm (where
> devm_drm_of_get_bridge() ends up) and drm_kms_helper (where
>
On Mon, 2021-09-20 at 16:11 +0200, Lukasz Majczak wrote:
> With patch "drm/i915/vbt: Fix backlight parsing for VBT 234+"
> the size of bdb_lfp_backlight_data structure has been increased,
> causing if-statement in the parse_lfp_backlight function
> that comapres this structure size to the one
On Mon, Sep 20, 2021 at 08:42:42AM +0100, Tvrtko Ursulin wrote:
>
> On 20/09/2021 08:38, Jani Nikula wrote:
> > On Mon, 20 Sep 2021, Tvrtko Ursulin wrote:
> > > On 18/09/2021 00:38, Matthew Brost wrote:
> > > > From: Hugh Dickins
> > > >
> > > > 5.15-rc1 crashes with blank screen when booting
On Mon, Sep 20, 2021 at 08:28:13AM +0100, Tvrtko Ursulin wrote:
>
> On 18/09/2021 00:38, Matthew Brost wrote:
> > From: Hugh Dickins
> >
> > 5.15-rc1 crashes with blank screen when booting up on two ThinkPads
> > using i915. Bisections converge convincingly, but arrive at different
> > and
On Thu, 16 Sep 2021 17:55:15 +0300, Mikko Perttunen wrote:
> Add YAML device tree bindings for NVDEC, now in a more appropriate
> place compared to the old textual Host1x bindings.
>
> Signed-off-by: Mikko Perttunen
> ---
> v6:
> * Elaborated description for nvidia,host1x-class.
> * Added
On 9/20/2021 3:53 AM, Alistair Popple wrote:
On Tuesday, 14 September 2021 2:16:01 AM AEST Alex Sierra wrote:
In order to configure device public in test_hmm, two module parameters
should be passed, which correspond to the SP start address of each
device (2) spm_addr_dev0 & spm_addr_dev1. If
On Mon, Sep 20, 2021 at 3:21 PM Arunpravin
wrote:
>
> Replace drm_mm with drm buddy manager for
> VRAM memory management
Would be good to document why we are doing this and what advantages it
brings over the old drm_mm code.
Alex
>
> Signed-off-by: Arunpravin
> ---
>
On Mon, Sep 20, 2021 at 3:21 PM Arunpravin
wrote:
Please prefix the patch subject with drm. E.g.,
drm: Enable buddy memory manager support
Same for the second patch, but make it drm/amdgpu instead.
Alex
>
> Port Intel buddy system manager to drm root folder
> Add CPU mappable/non-mappable
On Wed, Sep 08, 2021 at 05:58:36PM -0500, Tom Lendacky wrote:
> diff --git a/arch/x86/mm/mem_encrypt_identity.c
> b/arch/x86/mm/mem_encrypt_identity.c
> index 470b20208430..eff4d19f9cb4 100644
> --- a/arch/x86/mm/mem_encrypt_identity.c
> +++ b/arch/x86/mm/mem_encrypt_identity.c
> @@ -30,6 +30,7
Replace drm_mm with drm buddy manager for
VRAM memory management
Signed-off-by: Arunpravin
---
.../gpu/drm/amd/amdgpu/amdgpu_res_cursor.h| 78 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 216 ++
3 files
Port Intel buddy system manager to drm root folder
Add CPU mappable/non-mappable region support to the drm buddy manager
Signed-off-by: Arunpravin
---
drivers/gpu/drm/Makefile| 2 +-
drivers/gpu/drm/drm_buddy.c | 465
include/drm/drm_buddy.h | 154
On Fri, 2021-09-17 at 10:08 -0700, Matt Roper wrote:
> From: Venkata Sandeep Dhanalakota
>
> Support for multiple GT's within a single i915 device will be
> arriving
> soon. Since each GT may have its own fusing and require different
> workarounds, we need to make the GT workaround functions
On Thu, Aug 12, 2021 at 1:08 PM Doug Anderson wrote:
>
> Laurent,
>
> On Thu, Aug 12, 2021 at 12:26 PM Laurent Pinchart
> wrote:
> >
> > Hi Rob,
> >
> > Thank you for the patch.
> >
> > On Wed, Aug 11, 2021 at 04:52:50PM -0700, Rob Clark wrote:
> > > From: Rob Clark
> > >
> > > Slightly awkward
Coverity complains of a resource leak in ga102_chan_new():
CID 119637 (#7 of 7): Resource leak (RESOURCE_LEAK)
13. leaked_storage: Variable chan going out of scope leaks the storage it
points to.
190return ret;
Fix this by freeing 'chan' in the error path.
Cc: Ben Skeggs
Cc:
Use resource-managed helpers to make code cleaner and more correct,
properly releasing all resources in case of driver probe error.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/fuse/fuse-tegra.c | 32 ++
drivers/soc/tegra/fuse/fuse-tegra20.c | 33
Memory access must be blocked before hardware reset is asserted and before
power is gated, otherwise a serious hardware fault is inevitable. Add
reset for memory clients to the GR2D, GR3D and Host1x nodes.
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20
Signed-off-by:
MPE, VI, EPP and ISP were never used and we don't have drivers for them.
Since these modules are enabled by default in a device-tree, a device is
created for them, blocking voltage scaling because there is no driver to
bind, and thus, state of PMC driver is never synced. Disable them.
Document new OPP table and power domain properties of the video decoder
hardware.
Reviewed-by: Rob Herring
Acked-by: Hans Verkuil
Signed-off-by: Dmitry Osipenko
---
.../devicetree/bindings/media/nvidia,tegra-vde.yaml | 12
1 file changed, 12 insertions(+)
diff --git
The NAND on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now NAND must be resumed using
runtime PM API in order to initialize the NAND power state. Add runtime PM
and OPP support to the NAND driver.
Acked-by: Miquel Raynal
Signed-off-by:
All device drivers got runtime PM and OPP support. Flip the core domain
support status for Tegra20 and Tegra30 SoCs.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/tegra/pmc.c
The SPI on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now SPI driver must use OPP
API for driving the controller's clock rate because OPP API takes care
of reconfiguring the domain's performance state in accordance to the
rate. Add OPP
Add OPP tables and power domains to all peripheral devices which
support power management on Tegra30 SoC.
Tested-by: Peter Geis # Ouya T30
Tested-by: Matt Merhar # Ouya T30
Signed-off-by: Dmitry Osipenko
---
.../tegra30-asus-nexus7-grouper-common.dtsi |1 +
The PWM on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now PWM must be resumed using
runtime PM API in order to initialize the PWM power state. The PWM clock
rate must be changed using OPP API that will reconfigure the power domain
Device-tree schema doesn't allow domain name to start with a number.
We don't use 3d domain yet in device-trees, so rename it to the name
used by Tegra TRMs: TD, TD2.
Reported-by: David Heidelberg
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 8
1 file changed, 4
CORE power domain uses name of device-tree node, which is inconsistent with
the names of PMC domains. Set the name to "core" to make it consistent.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Currently driver supports legacy power domain API, this patch adds generic
power domain support. This allows us to utilize a modern GENPD API for
newer device-trees.
Tested-by: Peter Geis # Ouya T30
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124
The SDHCI on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now SDHCI must be resumed using
runtime PM API in order to initialize the SDHCI power state. The SDHCI
clock rate must be changed using OPP API that will reconfigure the power
domain
Memory access must be blocked before hardware reset is asserted and before
power is gated, otherwise a serious hardware fault is inevitable. Add
reset for memory clients to the GR2D, GR3D and Host1x nodes.
Tested-by: Peter Geis # Ouya T30
Tested-by: Matt Merhar # Ouya T30
Signed-off-by: Dmitry
Add OPP tables and power domains to all peripheral devices which
support power management on Tegra20 SoC.
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20
Signed-off-by: Dmitry Osipenko
---
.../boot/dts/tegra20-acer-a500-picasso.dts| 1 +
The FUSE controller is enabled at a boot time. Reset it in order to put
hardware and clock into clean and disabled state.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/fuse/fuse-tegra.c | 25 +
drivers/soc/tegra/fuse/fuse.h | 1 +
2 files changed, 26
Depending on hardware version, Tegra SoC may require a higher voltages
during resume from system suspend, otherwise hardware will crash. Set
SoC voltages to a nominal levels during suspend.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/regulators-tegra20.c | 99
Convert NVIDIA Tegra video decoder binding to schema.
Reviewed-by: Rob Herring
Acked-by: Hans Verkuil
Signed-off-by: Dmitry Osipenko
---
.../bindings/media/nvidia,tegra-vde.txt | 64 ---
.../bindings/media/nvidia,tegra-vde.yaml | 107 ++
2 files changed,
Add host1x_channel_stop() which waits till channel becomes idle and then
stops the channel hardware. This is needed for supporting suspend/resume
by host1x drivers since the hardware state is lost after power-gating,
thus the channel needs to be stopped before client enters into suspend.
The Tegra USB controller belongs to the core power domain and we're going
to enable GENPD support for the core domain. Now USB controller must be
resumed using runtime PM API in order to initialize the USB power state.
We already support runtime PM for the CI device, but CI's PM is separated
from
Add OPP and SoC core voltage scaling support to the display controller
driver. This is required for enabling system-wide DVFS on pre-Tegra186
SoCs.
Tested-by: Peter Geis # Ouya T30
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar #
Add runtime power management and support generic power domains.
Tested-by: Peter Geis # Ouya T30
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar # Ouya T30
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gr2d.c | 155
The HDMI on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now HDMI driver must use
OPP API for driving the controller's clock rate because OPP API takes
care of reconfiguring the domain's performance state based on HDMI clock
rate. Add OPP
Document new DVFS OPP table and power domain properties of the Host1x bus
and devices sitting on the bus.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
.../display/tegra/nvidia,tegra20-host1x.txt | 49 +++
1 file changed, 49 insertions(+)
diff --git
The GMI bus on Tegra belongs to the core power domain and we're going to
enable GENPD support for the core domain. Now GMI must be resumed using
runtime PM API in order to initialize the GMI power state. Add runtime PM
and OPP support to the GMI driver.
Signed-off-by: Dmitry Osipenko
---
Add runtime power management and support generic power domains.
Tested-by: Peter Geis # Ouya T30
Tested-by: Paul Fertser # PAZ00 T20
Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar # Ouya T30
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gr3d.c | 388
Hardware must be stopped before system is suspended. Add suspend-resume
callbacks.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/vic.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c
index c02010ff2b7f..359dd77f8b85
The Clock-and-Reset controller resides in a core power domain on NVIDIA
Tegra SoCs. In order to support voltage scaling of the core power domain,
we hook up DVFS-capable clocks to the core GENPD for managing of the
GENPD's performance state based on the clock changes.
Some clocks don't have any
Only couple drivers need to get the -ENODEV error code and majority of
drivers need to explicitly initialize the performance state. Add new
common helper which sets up OPP table for these drivers.
Signed-off-by: Dmitry Osipenko
---
include/soc/tegra/common.h | 24
1
Previously we assumed that devm_tegra_core_dev_init_opp_table() will
be used only by drivers that will always have device with OPP table,
but this is not true anymore. For example now Tegra30 will have OPP table
for PWM, but Tegra20 not and both use the same driver. Hence let's not
print the error
Memory Client should be blocked before hardware reset is asserted in order
to prevent memory corruption and hanging of memory controller.
Document Memory Client resets of Host1x, GR2D and GR3D hardware units.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Osipenko
---
Add runtime PM and OPP support to the Host1x driver. For the starter we
will keep host1x always-on because dynamic power management require a major
refactoring of the driver code since lot's of code paths are missing the
RPM handling and we're going to remove some of these paths in the future.
Document sub-nodes which describe Tegra SoC clocks that require a higher
voltage of the core power domain in order to operate properly on a higher
clock rates. Each node contains a phandle to OPP table and power domain.
The root PLLs and system clocks don't have any specific device dedicated
to
Disable PMC state syncing in order to ensure that we won't break older
kernels once device-trees will be updated with the addition of the power
domains. This also allows to apply device-tree PM patches independently
from the driver patches.
Signed-off-by: Dmitry Osipenko
---
This series adds runtime PM support to Tegra drivers and enables core
voltage scaling for Tegra20/30 SoCs, resolving overheating troubles.
All patches in this series are interdependent and should go via Tegra tree.
Changelog:
v12: - Added r-b from Rob Herring to the host1x binding patch.
Elements of the 'names' array are not changed by the code, constify them
for consistency.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 6 +++---
include/linux/pm_opp.h | 8
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/opp/core.c
On Thu, Sep 09 2021, Jason Gunthorpe wrote:
> Many of the mdev drivers use a simple counter for keeping track of the
> available instances. Move this code to the core code and store the counter
> in the mdev_type. Implement it using correct locking, fixing mdpy.
>
> Drivers provide a
On 9/20/21 2:17 PM, Arnd Bergmann wrote:
From: Arnd Bergmann
The empty unmap_page_from_agp() macro causes a warning when
building with 'make W=1' on a couple of architectures:
drivers/char/agp/generic.c: In function 'agp_generic_destroy_page':
drivers/char/agp/generic.c:1265:28: error:
On Mon, Sep 20, 2021 at 10:33 AM Maxime Ripard wrote:
>
> What I was interested in was more about the context itself, and I'd
> still like an answer on whether it's ok to wait for a review for 5
> months though, or if it's an expectation from now on that we are
> supposed to fix bugs over the
On Mon, Sep 20, 2021 at 10:10:57AM -0700, Linus Torvalds wrote:
> On Mon, Sep 20, 2021 at 5:17 AM Maxime Ripard wrote:
> >
> > I'm sorry, but I find that situation to be a bit ridiculous.
>
> Honestly, the original report about the pulseaudio problem came in
> over two weeks ago, and all you
Hi,
I just noticed that I left some partly old TODOs in the code. Just
ignore these for now. I don't expect this to be the last version so I
will fix/remove them in the next version.
Best,
Markus
On Mon, Sep 20, 2021 at 10:44:24AM +0200, Markus Schneider-Pargmann wrote:
> This patch adds a
With patch "drm/i915/vbt: Fix backlight parsing for VBT 234+"
the size of bdb_lfp_backlight_data structure has been increased,
causing if-statement in the parse_lfp_backlight function
that comapres this structure size to the one retrieved from BDB,
always to fail for older revisions.
This patch
On Mon, Sep 20, 2021 at 05:38:30PM +0200, Greg KH wrote:
> On Mon, Sep 20, 2021 at 08:26:03AM -0700, Zachary Mayhew wrote:
> > Subject: [PATCH] staging: fbtft: add docs for fbtft_write_spi()
>
> Odd, this shouldn't be in the body of the email :(
>
> >
> > This patch adds documentation for
On Mon, Sep 20, 2021 at 06:18:58PM +0200, Greg KH wrote:
> On Mon, Sep 20, 2021 at 09:07:13AM -0700, Zachary Mayhew wrote:
> > On Mon, Sep 20, 2021 at 05:38:30PM +0200, Greg KH wrote:
> > > On Mon, Sep 20, 2021 at 08:26:03AM -0700, Zachary Mayhew wrote:
> > > > Subject: [PATCH] staging: fbtft: add
Subject: [PATCH] staging: fbtft: add docs for fbtft_write_spi()
This patch adds documentation for fbtft_write_spi() to make its
calling context clear and explain what it does.
Signed-off-by: Zachary Mayhew
---
drivers/staging/fbtft/fbtft-io.c | 13 +
1 file changed, 13
On Mon, Sep 20, 2021 at 5:17 AM Maxime Ripard wrote:
>
> I'm sorry, but I find that situation to be a bit ridiculous.
Honestly, the original report about the pulseaudio problem came in
over two weeks ago, and all you seemed to do was to ignore everything
that Sudip said and reported.
THAT is
On Mon, Sep 20, 2021 at 05:35:00PM +0100, Sudip Mukherjee wrote:
> On Mon, Sep 20, 2021 at 4:53 PM Maxime Ripard wrote:
> >
> > On Mon, Sep 20, 2021 at 05:43:33PM +0200, Maxime Ripard wrote:
> > > On Mon, Sep 20, 2021 at 04:47:31PM +0200, Maxime Ripard wrote:
> > > > On Sat, Sep 04, 2021 at
On Mon, 20 Sep 2021, Lukasz Majczak wrote:
> With patch "drm/i915/vbt: Fix backlight parsing for VBT 234+"
> the size of bdb_lfp_backlight_data structure has been increased,
> causing if-statement in the parse_lfp_backlight function
> that comapres this structure size to the one retrieved from
27.08.2021 16:22, Thierry Reding пишет:
> From: Thierry Reding
>
> Hi all,
>
> this is the userspace part of the kernel patches that were recently
> merged into drm-next:
>
> https://patchwork.freedesktop.org/series/92378/
>
> The goal is to provide a userspace implementation of the UAPI
Hi,
On Tue, Sep 14, 2021 at 3:12 PM Linus Walleij wrote:
>
> On Tue, Sep 14, 2021 at 10:22 PM Douglas Anderson
> wrote:
>
> > Version 5 of this series just fixes the panel ID encode macro to be
> > cleaner and adds Jani's review tags.
> >
> > It could possibly be ready to land?
>
> Definitely
On Mon, Sep 20, 2021 at 4:53 PM Maxime Ripard wrote:
>
> On Mon, Sep 20, 2021 at 05:43:33PM +0200, Maxime Ripard wrote:
> > On Mon, Sep 20, 2021 at 04:47:31PM +0200, Maxime Ripard wrote:
> > > On Sat, Sep 04, 2021 at 10:40:29AM +0100, Sudip Mukherjee wrote:
> > > > Hi Maxime,
> > > >
> > > > On
https://bugzilla.kernel.org/show_bug.cgi?id=214029
Erhard F. (erhar...@mailbox.org) changed:
What|Removed |Added
Summary|[NAVI] Several memory leaks |[bisected] [NAVI]
https://bugzilla.kernel.org/show_bug.cgi?id=214029
--- Comment #13 from Erhard F. (erhar...@mailbox.org) ---
Created attachment 298897
--> https://bugzilla.kernel.org/attachment.cgi?id=298897=edit
bisect.log
Verified that the issue still exists in latest v5.15-rc2 and v5.14.6 and did a
bisect:
https://bugzilla.kernel.org/show_bug.cgi?id=214029
Erhard F. (erhar...@mailbox.org) changed:
What|Removed |Added
Attachment #298787|0 |1
is obsolete|
https://bugzilla.kernel.org/show_bug.cgi?id=214029
Erhard F. (erhar...@mailbox.org) changed:
What|Removed |Added
Attachment #298785|0 |1
is obsolete|
On Mon, Sep 20, 2021 at 09:07:13AM -0700, Zachary Mayhew wrote:
> On Mon, Sep 20, 2021 at 05:38:30PM +0200, Greg KH wrote:
> > On Mon, Sep 20, 2021 at 08:26:03AM -0700, Zachary Mayhew wrote:
> > > Subject: [PATCH] staging: fbtft: add docs for fbtft_write_spi()
> >
> > Odd, this shouldn't be in
On Mon, Sep 20, 2021 at 02:17:19PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> The empty unmap_page_from_agp() macro causes a warning when
> building with 'make W=1' on a couple of architectures:
>
> drivers/char/agp/generic.c: In function 'agp_generic_destroy_page':
>
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