> - Respun clock fixes for vc4/hdmi.
I was uneasy with these patches due to the number and size of them at
this point in the cycle. Is there any major problem leaving them until
next? I think fixes needs a hard reset and rebase to rc6 when it's
tagged.
If these are super-urgent fixes then I'd
Hi Linus,
This is the fixes pull for 5.15-rc6.
It has a few scattered msm and i915 fixes, a few core fixes and a
mediatek feature revert.
I've had to pick a bunch of patches into this, as the drm-misc-fixes
tree had a bunch of vc4 patches I wasn't comfortable with sending to
you at least as
On Thu, Oct 14, 2021 at 02:11:34AM +0200, Andi Shyti wrote:
Hi Lucas,
On Wed, Oct 13, 2021 at 05:04:27PM -0700, Lucas De Marchi wrote:
On Wed, Oct 13, 2021 at 12:17:38AM +0200, Andi Shyti wrote:
> From: Andi Shyti
>
> The following interfaces:
>
> i915_wedged
> i915_forcewake_user
>
> are
On 10/14/2021 3:57 PM, Ralph Campbell wrote:
On 10/14/21 11:01 AM, Jason Gunthorpe wrote:
On Thu, Oct 14, 2021 at 10:35:27AM -0700, Ralph Campbell wrote:
I ran xfstests-dev using the kernel boot option to "fake" a pmem device
when I first posted this patch. The tests ran OK (or at least
Hi Pekka,
Thank you for reviewing this patch.
> On Mon, 13 Sep 2021 16:35:26 -0700
> Vivek Kasireddy wrote:
>
> > If a driver supports this capability, it means that there would be an
> > additional signalling mechanism for a page flip completion in addition
> > to out_fence or
Hi Matthew,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on next-20211012]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next airlied/drm-next v5.15-rc5]
[If your
Hey Dan,
On 10/1/2021 5:31 AM, Dan Carpenter wrote:
Hello Sean Paul,
The patch a6bcddbc2ee1: "drm/msm: dsi: Handle dual-channel for 6G as
well" from Jul 25, 2018, leads to the following
Smatch static checker warning:
drivers/gpu/drm/msm/dsi/dsi_host.c:729 dsi_calc_clk_rate_6g()
On Thu, Oct 14, 2021 at 4:06 PM Jason Gunthorpe wrote:
>
> On Thu, Oct 14, 2021 at 12:01:14PM -0700, Dan Williams wrote:
> > > > Does anyone know why devmap is pte_special anyhow?
> >
> > It does not need to be special as mentioned here:
> >
> >
In preparation for GuC pmu stats, add a name to the execlists stats
structure so that it can be differentiated from the GuC stats.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 14 +++---
drivers/gpu/drm/i915/gt/intel_engine_stats.h | 33 +++--
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to the user, GuC shares this info
with i915 for all engines using shared memory. For each engine, this
info contains:
-
15.10.2021 03:45, Stephen Boyd пишет:
> Quoting Dmitry Osipenko (2021-10-14 17:43:49)
>> 15.10.2021 03:16, Stephen Boyd пишет:
>>> Quoting Dmitry Osipenko (2021-09-20 11:11:15)
diff --git
a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
On Thu, Oct 14, 2021 at 09:21:28AM +0100, Tvrtko Ursulin wrote:
On 13/10/2021 01:56, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to
Quoting Dmitry Osipenko (2021-10-14 17:43:49)
> 15.10.2021 03:16, Stephen Boyd пишет:
> > Quoting Dmitry Osipenko (2021-09-20 11:11:15)
> >> diff --git
> >> a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
> >> b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
>
15.10.2021 03:16, Stephen Boyd пишет:
> Quoting Dmitry Osipenko (2021-09-20 11:11:15)
>> diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
>> b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
>> index 459d2a525393..f832abb7f11a 100644
>> ---
On 13/10/2021 17:42, Arnd Bergmann wrote:
From: Arnd Bergmann
When CONFIG_COMMON_CLOCK is disabled, the 8996 specific
phy code is left out, which results in a link failure:
ld: drivers/gpu/drm/msm/hdmi/hdmi_phy.o:(.rodata+0x3f0): undefined reference to
`msm_hdmi_phy_8996_cfg'
This was only
Quoting Dmitry Osipenko (2021-09-20 11:11:15)
> diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
> b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
> index 459d2a525393..f832abb7f11a 100644
> ---
Switch to using bulk regulator API instead of hand coding loops.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 34 +++
drivers/gpu/drm/msm/hdmi/hdmi.h | 6 ++--
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c| 20 -
Merge old hdmi_bridge and hdmi_connector implementations. Use
drm_bridge_connector instead.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Makefile | 2 +-
drivers/gpu/drm/msm/hdmi/hdmi.c | 12 +-
drivers/gpu/drm/msm/hdmi/hdmi.h | 19 ++-
On 10/13/2021 5:08 PM, Andi Shyti wrote:
From: Andi Shyti
The GT has its own properties and in sysfs they should be grouped
in the 'gt/' directory.
Create a 'gt/' directory in sysfs which will contain gt0...gtN
directories related to each tile configured in the GPU. Move the
power
On Wed, Oct 13, 2021 at 2:12 PM Mark Yacoub wrote:
>
> From: Mark Yacoub
>
> [Why]
> drm_atomic_helper_check_crtc now verifies both legacy and non-legacy LUT
> sizes. There is no need to check it within amdgpu_dm_atomic_check.
>
> [How]
> Remove the local call to verify LUT sizes and use DRM
https://bugzilla.kernel.org/show_bug.cgi?id=214725
Bug ID: 214725
Summary: simpledrm and i915 both active after boot
Product: Drivers
Version: 2.5
Kernel Version: 5.14.11
Hardware: All
OS: Linux
Tree:
On 07/10/2021 10:08, Vinod Koul wrote:
When DSC is enabled, we need to configure DSI registers accordingly and
configure the respective stream compression registers.
Add support to calculate the register setting based on DSC params and
timing information and configure these registers.
On Thu, Oct 14, 2021 at 12:01:14PM -0700, Dan Williams wrote:
> > > Does anyone know why devmap is pte_special anyhow?
>
> It does not need to be special as mentioned here:
>
> https://lore.kernel.org/all/CAPcyv4iFeVDVPn6uc=aksyuvkiu3-fk-n16ijvzq3n8ot00...@mail.gmail.com/
I added a remark there
Hi Bjorn,
I love your patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v5.15-rc5 next-20211013]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
Stop using legacy clock names (with _clk suffix) for HDMI and HDMI PHY
device tree nodes.
Signed-off-by: Dmitry Baryshkov
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
On Thu, 14 Oct 2021 at 19:54, Vladimir Zapolskiy
wrote:
>
> Hi Dmitry,
>
> On 10/14/21 4:54 PM, Dmitry Baryshkov wrote:
> > From: Amit Pundir
> >
> > This reverts commit 001ce9785c0674d913531345e86222c965fc8bf4.
> >
> > This upstream commit broke AOSP (post Android 12 merge) build
> > on RB5.
A new warning in clang points out a place in this file where a bitwise
OR is being used with boolean types:
drivers/gpu/drm/i915/intel_pm.c:3066:12: warning: use of bitwise '|' with
boolean operands [-Wbitwise-instead-of-logical]
changed = ilk_increase_wm_latency(dev_priv,
On 10/14/21 11:01 AM, Jason Gunthorpe wrote:
On Thu, Oct 14, 2021 at 10:35:27AM -0700, Ralph Campbell wrote:
I ran xfstests-dev using the kernel boot option to "fake" a pmem device
when I first posted this patch. The tests ran OK (or at least the same
tests passed with and without my patch).
Hi lichenyang,
On Sat, Sep 11, 2021 at 10:31:31AM +0800, lichenyang wrote:
> From: Chenyang Li
>
> This patch adds an initial DRM driver for the Loongson LS7A1000
> bridge chip(LS7A). The LS7A bridge chip contains two display
> controllers, support dual display output. The maximum support for
>
On Wed, 06 Oct 2021 17:21:58 +0200, AngeloGioacchino Del Regno wrote:
> Convert the Silicon Image SiI9234 HDMI/MHL bridge documentation to YAML.
>
> Signed-off-by: AngeloGioacchino Del Regno
>
> ---
> .../bindings/display/bridge/sii9234.txt | 49
>
On Wed, Oct 06, 2021 at 05:04:59PM +0200, AngeloGioacchino Del Regno wrote:
> Convert the Silicon Image SiI8620 HDMI/MHL bridge documentation to YAML.
>
> Signed-off-by: AngeloGioacchino Del Regno
>
> ---
> .../bindings/display/bridge/sil,sii8620.yaml | 93 +++
>
Adding Mikita aswell
On 2021-10-14 4:21 p.m., Bhawanpreet Lakha wrote:
On 2021-10-13 6:25 p.m., Lyude Paul wrote:
Some comments below (also, sorry again for the mixup on the last
review!)
On Tue, 2021-10-12 at 17:58 -0400, Bhawanpreet Lakha wrote:
8b/10b encoding format requires to reserve
On 2021-10-13 6:25 p.m., Lyude Paul wrote:
Some comments below (also, sorry again for the mixup on the last review!)
On Tue, 2021-10-12 at 17:58 -0400, Bhawanpreet Lakha wrote:
8b/10b encoding format requires to reserve the first slot for
recording metadata. Real data transmission starts
W552946ABA is a panel by Wanchanglong. This panel utilizes the Ilitek ILI9881D
controller.
Add this panel's initialzation sequence and timing to ILI9881D driver.
Tested on px30-evb v11
Signed-off-by: Michael Trimarchi
---
drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 238 +-
On Wed, Oct 06, 2021 at 03:52:04PM +0200, AngeloGioacchino Del Regno wrote:
> Convert the Toshiba TC358767 txt documentation to YAML.
>
> Signed-off-by: AngeloGioacchino Del Regno
>
> ---
> .../display/bridge/toshiba,tc358767.txt | 54
> .../display/bridge/toshiba,tc358767.yaml
Hi Cai,
On Thu, Sep 16, 2021 at 06:42:24PM +0800, Cai Huoqing wrote:
> When possible use dev_err_probe help to properly deal with the
> PROBE_DEFER error, the benefit is that DEFER issue will be logged
> in the devices_deferred debugfs file.
> And using dev_err_probe() can reduce code size, and
On Mon, Oct 11, 2021 at 10:12:02PM +0200, Sam Ravnborg wrote:
> Hi AngeloGioacchino,
>
> On Wed, Oct 06, 2021 at 03:51:50PM +0200, AngeloGioacchino Del Regno wrote:
> > Convert the Toshiba TC358764 txt documentation to YAML.
> >
> > Signed-off-by: AngeloGioacchino Del Regno
> >
>
> Thanks for
Hi Cai,
On Thu, Sep 16, 2021 at 03:37:05PM +0800, Cai Huoqing wrote:
> Removed extra whitespace before dev_err_probe() according to coding style.
>
> Signed-off-by: Cai Huoqing
Thanks, applied to drm-misc-next.
Sam
Hi Brian,
On Thu, Sep 23, 2021 at 05:33:52PM -0700, Brian Norris wrote:
> I've tested a few dual-DSI panel drivers which choke if they PROBE_DEFER
> at the wrong time, so I patched those up in patch 1 and 2. Patch 3 fixes
> the other drivers that I couldn't test, but seem to have all the same
>
> -Original Message-
> From: Pekka Paalanen
> Sent: Wednesday, October 13, 2021 12:56 PM
> To: Shankar, Uma
> Cc: Simon Ser ; daniel.vet...@ffwll.ch; intel-
> g...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
> harry.wentl...@amd.com; ville.syrj...@linux.intel.com;
> -Original Message-
> From: Pekka Paalanen
> Sent: Wednesday, October 13, 2021 2:01 PM
> To: Shankar, Uma
> Cc: harry.wentl...@amd.com; ville.syrj...@linux.intel.com; intel-
> g...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
> brian.star...@arm.com;
Hi Wang,
On Wed, Oct 13, 2021 at 07:41:39PM +0800, Wang Hai wrote:
> I got a null-ptr-deref report:
>
> [drm:drm_dev_init [drm]] *ERROR* Cannot allocate anonymous inode: -12
> ==
> BUG: KASAN: null-ptr-deref in iput+0x3c/0x4a0
> ...
Hi Guido,
> > >
> > > + if (ret != -EPROBE_DEFER) {
> > > #ifdef CONFIG_OF
> > > - DRM_ERROR("failed to attach bridge %pOF to encoder %s: %d\n",
> > > - bridge->of_node, encoder->name, ret);
> > > + DRM_ERROR("failed to attach bridge %pOF to encoder %s: %d\n",
> > > +
On Thu, Oct 14, 2021 at 11:45 AM Matthew Wilcox wrote:
>
>
> It would probably help if you cc'd Dan on this.
Thanks.
[..]
>
> On Thu, Oct 14, 2021 at 02:06:34PM -0300, Jason Gunthorpe wrote:
> > On Thu, Oct 14, 2021 at 10:39:28AM -0500, Alex Sierra wrote:
> > > From: Ralph Campbell
> > >
> > >
On Thu, Oct 14, 2021 at 11:42:41AM -0700, John Harrison wrote:
> On 10/14/2021 10:20, Matthew Brost wrote:
> > A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
> > execlists. Doing as little as possible to support this interface for
> > execlists - basically just passing
Hi Dan,
On Wed, Oct 13, 2021 at 11:08:25AM +0300, Dan Carpenter wrote:
> The "label" pointer is used for debug output. The code assumes that it
> is either NULL or valid, but it is never set to NULL. It is either
> valid or uninitialized.
>
> Fixes: 0c275c30176b ("drm/bridge: Add bridge driver
Hi Marek,
On Wed, Oct 13, 2021 at 12:42:52AM +0200, Marek Vasut wrote:
> Add helper function to convert DT "data-mapping" property string value
> into media bus format value, and deduplicate the code in panel-lvds.c
> and lvds-codec.c .
>
> Signed-off-by: Marek Vasut
> Cc: Laurent Pinchart
>
Hi Nikola,
On Mon, Oct 11, 2021 at 11:27:31PM +0200, Nikola Pavlica wrote:
> The model and make of the LCD panel of the Vivax TPC-9150 is unknown,
> hence the panel settings that were retrieved with a FEX dump are named
> after the device NOT the actual panel.
>
> The LCD in question is a 50 pin
It would probably help if you cc'd Dan on this.
As far as I know he's the only person left who cares about GUP on DAX.
On Thu, Oct 14, 2021 at 02:06:34PM -0300, Jason Gunthorpe wrote:
> On Thu, Oct 14, 2021 at 10:39:28AM -0500, Alex Sierra wrote:
> > From: Ralph Campbell
> >
> > ZONE_DEVICE
Hi Anitha,
On Wed, Oct 13, 2021 at 04:36:31PM -0700, Anitha Chrisanthus wrote:
> On KMB, ADV bridge must be programmed and powered on prior to
> MIPI DSI HW initialization.
>
> Fixes: 98521f4d4b4c ("drm/kmb: Mipi DSI part of the display driver")
> Signed-off-by: Anitha Chrisanthus
> ---
>
On 10/14/2021 10:20, Matthew Brost wrote:
A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
execlists. Doing as little as possible to support this interface for
execlists - basically just passing submit fences between each request
generated and virtual engines are not
Hi Anitha,
On Wed, Oct 13, 2021 at 04:36:30PM -0700, Anitha Chrisanthus wrote:
> Check for Overflow bits for layer3 in the irq handler.
>
> Fixes: 7f7b96a8a0a1 ("drm/kmb: Add support for KeemBay Display")
> Signed-off-by: Anitha Chrisanthus
Obvious fix,
Acked-by: Sam Ravnborg
Hi Anitha,
On Wed, Oct 13, 2021 at 04:36:29PM -0700, Anitha Chrisanthus wrote:
> From: Edmund Dea
>
> Due to HW limitations, KMB cannot change height, width, or
> pixel format after initial plane configuration.
>
> v2: removed memset disp_cfg as it is already zero.
>
> Fixes: 7f7b96a8a0a1
On Wed, Oct 13, 2021 at 04:36:28PM -0700, Anitha Chrisanthus wrote:
> From: Edmund Dea
>
> Don't clear the shared DPHY registers common to MIPI Rx and MIPI Tx during
> DSI initialization since this was causing MIPI Rx reset. Rest of the
> writes are bitwise, so will not affect Mipi Rx side.
>
>
On Wed, Oct 13, 2021 at 04:36:27PM -0700, Anitha Chrisanthus wrote:
> KMB only supports single resolution(1080p), this commit checks for
> 1920x1080x60 or 1920x1080x59 in crtc_mode_valid.
> Also, modes with vfp < 4 are not supported in KMB display. This change
> prunes display modes with vfp < 4.
Hi Dmitry,
On 10/14/21 4:54 PM, Dmitry Baryshkov wrote:
From: Amit Pundir
This reverts commit 001ce9785c0674d913531345e86222c965fc8bf4.
This upstream commit broke AOSP (post Android 12 merge) build
on RB5. The device either silently crashes into USB crash mode
after android boot animation or
Hi Anitha,
On Wed, Oct 13, 2021 at 04:36:26PM -0700, Anitha Chrisanthus wrote:
> Use a different value for system clock offset in the
> ppl/llp ratio calculations for clocks higher than 500 Mhz.
>
> Fixes: 98521f4d4b4c ("drm/kmb: Mipi DSI part of the display driver")
> Signed-off-by: Anitha
Hi Oleksij,
On Thu, Oct 14, 2021 at 11:52:02AM +0200, Oleksij Rempel wrote:
> Add compatible and timings for the Innolux G070Y2-T02 panel. It is 7"
> WVGA (800x480) TFT LCD panel with TTL interface and a backlight unit.
>
> Co-Developed-by: Robin van der Gracht
> Signed-off-by: Robin van der
On Thu, Oct 14, 2021 at 08:26:52PM +0200, Sam Ravnborg wrote:
> Hi Gustavo,
> On Thu, Oct 14, 2021 at 11:53:20AM -0500, Gustavo A. R. Silva wrote:
> > Fix the following fallthrough warnings:
> >
> > drivers/video/fbdev/omap/omapfb_main.c:1558:2: warning: unannotated
> > fall-through between
On 10/14/2021 10:20, Matthew Brost wrote:
Enable multi-bb execbuf by enabling the set_parallel extension.
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 3 ---
1 file changed, 3 deletions(-)
diff --git
On 10/14/2021 10:20, Matthew Brost wrote:
Allow multiple batch buffers to be submitted in a single execbuf IOCTL
after a context has been configured with the 'set_parallel' extension.
The number batches is implicit based on the contexts configuration.
This is implemented with a series of loops.
Hi Gustavo,
On Thu, Oct 14, 2021 at 11:53:20AM -0500, Gustavo A. R. Silva wrote:
> Fix the following fallthrough warnings:
>
> drivers/video/fbdev/omap/omapfb_main.c:1558:2: warning: unannotated
> fall-through between switch labels [-Wimplicit-fallthrough]
>case 0:
>^
>
On 10/14/2021 10:19, Matthew Brost wrote:
Introduce 'set parallel submit' extension to connect UAPI to GuC
multi-lrc interface. Kernel doc in new uAPI should explain it all.
IGT: https://patchwork.freedesktop.org/patch/447008/?series=93071=1
media UMD:
Hi Neil,
On Thu, Oct 14, 2021 at 05:26:04PM +0200, Neil Armstrong wrote:
> This implements the necessary change to no more use the embedded
> connector in dw-hdmi and use the dedicated bridge connector driver
> by passing DRM_BRIDGE_ATTACH_NO_CONNECTOR to the bridge attach call.
>
> The
On 10/14/2021 10:19, Matthew Brost wrote:
Add multi-lrc context registration H2G. In addition a workqueue and
process descriptor are setup during multi-lrc context registration as
these data structures are needed for multi-lrc submission.
v2:
(John Harrison)
- Move GuC specific fields into
On Thu, Oct 14, 2021 at 05:26:05PM +0200, Neil Armstrong wrote:
> Rename the cvbs encoder to match the newly introduced meson_encoder_hdmi.
>
> Signed-off-by: Neil Armstrong
Acked-by: Sam Ravnborg
Hi Neil,
with include order fixed and the comment below considered:
Acked-by: Sam Ravnborg
Sam
On Thu, Oct 14, 2021 at 05:26:06PM +0200, Neil Armstrong wrote:
> Drop the local connector and move all callback to bridge funcs in order
> to leverage the generic CVBS diplay connector.
>
On Thu, Oct 14, 2021 at 05:26:03PM +0200, Neil Armstrong wrote:
> Since we allow interlace on the encoder, also allow it on the bridge
> so we can allow interlaced modes when using DRM_BRIDGE_ATTACH_NO_CONNECTOR.
>
> Signed-off-by: Neil Armstrong
Acked-by: Sam Ravnborg
> ---
>
Hi Neil,
I did not verify all the code movements - but it looked correct from a
quick glance.
A few comments below, especially the use of mode_set() should be
addressed as it is deprecated.
Sam
On Thu, Oct 14, 2021 at 05:26:02PM +0200, Neil Armstrong wrote:
> This moves all the
On Thu, Oct 14, 2021 at 10:35:27AM -0700, Ralph Campbell wrote:
> I ran xfstests-dev using the kernel boot option to "fake" a pmem device
> when I first posted this patch. The tests ran OK (or at least the same
> tests passed with and without my patch).
Hmm. I know nothing of xfstests but
Hi Neil,
one comment below. Other than that
Acked-by: Sam Ravnborg
Sam
On Thu, Oct 14, 2021 at 05:26:01PM +0200, Neil Armstrong wrote:
> The initial design was recursive to cover all port/endpoints, but only the
> first layer
> of endpoints should be covered by the components list.
>
The GuC must receive requests in the order submitted for contexts in a
parent-child relationship to function correctly. To ensure this, insert
a submit fence between the current request and last request submitted
for requests / contexts in a parent child relationship. This is
conceptually similar
Add very basic (single submission) multi-lrc selftest.
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 +
.../drm/i915/gt/uc/selftest_guc_multi_lrc.c | 179 ++
.../drm/i915/selftests/i915_live_selftests.h | 1
Implement multi-lrc submission via a single workqueue entry and single
H2G. The workqueue entry contains an updated tail value for each
request, of all the contexts in the multi-lrc submission, and updates
these values simultaneously. As such, the tasklet and bypass path have
been updated to
Introduce 'set parallel submit' extension to connect UAPI to GuC
multi-lrc interface. Kernel doc in new uAPI should explain it all.
IGT: https://patchwork.freedesktop.org/patch/447008/?series=93071=1
media UMD: https://github.com/intel/media-driver/pull/1252
v2:
(Daniel Vetter)
- Add IGT link
Update context and full GPU reset to work with multi-lrc. The idea is
parent context tracks all the active requests inflight for itself and
its children. The parent context owns the reset replaying / canceling
requests as needed.
v2:
(John Harrison)
- Simply loop in find active request
- Add
In GuC parent-child contexts the parent context controls the scheduling,
ensure only the parent does the scheduling operations.
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 13 -
1 file changed, 12 insertions(+), 1
Calling switch_to_kernel_context isn't needed if the engine PM reference
is taken while all user contexts are pinned as if don't have PM ref that
guarantees that all user contexts scheduling is disabled. By not calling
switch_to_kernel_context we save on issuing a request to the engine.
v2:
Add logical engine mapping. This is required for split-frame, as
workloads need to be placed on engines in a logically contiguous manner.
v2:
(Daniel Vetter)
- Add kernel doc for new fields
v3:
(Tvrtko)
- Update comment for new logical_mask field
v4:
(John Harrison)
- Update comment for
Expose logical engine instance to user via query engine info IOCTL. This
is required for split-frame workloads as these needs to be placed on
engines in a logically contiguous order. The logical mapping can change
based on fusing. Rather than having user have knowledge of the fusing we
simply just
A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
execlists. Doing as little as possible to support this interface for
execlists - basically just passing submit fences between each request
generated and virtual engines are not allowed. This is on par with what
is there for
Parallel submission create composite fences (dma_fence_array) for excl /
shared slots in objects. The I915_GEM_BUSY IOCTL checks these slots to
determine the busyness of the object. Prior to patch it only check if
the fence in the slot was a i915_request. Update the check to understand
composite
Enable multi-bb execbuf by enabling the set_parallel extension.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index
For some users of multi-lrc, e.g. split frame, it isn't safe to preempt
mid BB. To safely enable preemption at the BB boundary, a handshake
between parent and child is needed, syncing the set of BBs at the
beginning and end of each batch. This is implemented via custom
emit_bb_start &
If an error occurs in the front end when multi-lrc requests are getting
generated we need to skip these in the backend but we still need to
emit the breadcrumbs seqno. An issues arises because with multi-lrc
breadcrumbs there is a handshake between the parent and children to make
forward progress.
If an object in the excl or shared slot is a composite fence from a
parallel submit and the current request in the conflict tracking is from
the same parallel context there is no need to enforce ordering as the
ordering is already implicit. Make the request conflict tracking
understand this by
Parallel contexts are perma-pinned by the upper layers which makes the
backend implementation rather simple. The parent pins the guc_id and
children increment the parent's pin count on pin to ensure all the
contexts are unpinned before we disable scheduling with the GuC / or
deregister the
Update parallel submit doc to point to i915_drm.h
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
Documentation/gpu/rfc/i915_parallel_execbuf.h | 122 --
Documentation/gpu/rfc/i915_scheduler.rst | 4 +-
2 files changed, 2 insertions(+), 124 deletions(-)
Display the workqueue status in debugfs for GuC contexts that are in
parent-child relationship.
v2:
(John Harrison)
- Output number children in debugfs
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 52 ++-
1 file
Add multi-lrc context registration H2G. In addition a workqueue and
process descriptor are setup during multi-lrc context registration as
these data structures are needed for multi-lrc submission.
v2:
(John Harrison)
- Move GuC specific fields into sub-struct
- Clean up WQ defines
- Add
Allow multiple batch buffers to be submitted in a single execbuf IOCTL
after a context has been configured with the 'set_parallel' extension.
The number batches is implicit based on the contexts configuration.
This is implemented with a series of loops. First a loop is used to find
all the
Assign contexts in parent-child relationship consecutive guc_ids. This
is accomplished by partitioning guc_id space between ones that need to
be consecutive (1/16 available guc_ids) and ones that do not (15/16 of
available guc_ids). The consecutive search is implemented via the bitmap
API.
This
Introduce context parent-child relationship. Once this relationship is
created all pinning / unpinning operations are directed to the parent
context. The parent context is responsible for pinning all of its
children and itself.
This is a precursor to the full GuC multi-lrc implementation but
Hi Neil,
code looks fine. A few improvement proposals to the comments.
With the include order fixed and the comments considered:
Reviewed-by: Sam Ravnborg
Sam
On Thu, Oct 14, 2021 at 05:26:00PM +0200, Neil Armstrong wrote:
> Since this bridge is tied to the connector, it acts like a
Taking a PM reference to prevent intel_gt_wait_for_idle from short
circuiting while a deregister context H2G is in flight. To do this must
issue the deregister H2G from a worker as context can be destroyed from
an atomic context and taking GT PM ref blows up. Previously we took a
runtime PM from
Taking a PM reference to prevent intel_gt_wait_for_idle from short
circuiting while any user context has scheduling enabled. Returning GT
idle when it is not can cause all sorts of issues throughout the stack.
v2:
(Daniel Vetter)
- Add might_lock annotations to pin / unpin function
v3:
(CI)
As discussed in [1] we are introducing a new parallel submission uAPI
for the i915 which allows more than 1 BB to be submitted in an execbuf
IOCTL. This is the implemenation for both GuC and execlists.
In addition to selftests in the series, an IGT is available implemented
in the first 4 patches
Move guc_id allocation under submission state sub-struct as a future
patch will reuse the spin lock as a global submission state lock. Moving
this into sub-struct makes ownership of fields / lock clear.
v2:
(Docs)
- Add comment for submission_state sub-structure
v3:
(John Harrison)
- Fixup
On 10/14/2021 09:41, Matthew Brost wrote:
On Thu, Oct 14, 2021 at 09:43:36AM -0700, John Harrison wrote:
On 10/14/2021 08:32, Matthew Brost wrote:
On Wed, Oct 13, 2021 at 06:02:42PM -0700, John Harrison wrote:
On 10/13/2021 13:42, Matthew Brost wrote:
Introduce 'set parallel submit'
On 10/14/21 10:06 AM, Jason Gunthorpe wrote:
On Thu, Oct 14, 2021 at 10:39:28AM -0500, Alex Sierra wrote:
From: Ralph Campbell
ZONE_DEVICE struct pages have an extra reference count that complicates the
code for put_page() and several places in the kernel that need to check the
reference
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