On 18/07/2023 01:34, Abhinav Kumar wrote:
drm_bridge_hpd_enable()/drm_bridge_hpd_disable() callbacks call into
the respective driver's hpd_enable()/hpd_disable() ops. These ops control
the HPD enable/disable logic which in some cases like MSM can be a
dedicate hardware block to control the HPD.
On 2023-07-17 22:35, Asahi Lina wrote:
> On 18/07/2023 00.55, Christian König wrote:
>> Am 15.07.23 um 16:14 schrieb aly...@rosenzweig.io:
>>> 15 July 2023 at 00:03, "Luben Tuikov" wrote:
On 2023-07-14 05:57, Christian König wrote:
> Am 14.07.23 um 11:49 schrieb Asahi Lina:
>
Hi,
Actually, I'm only a little bit worry about the ast_pm_thaw() code path.
|- ast_pm_thaw()
|-- ast_drm_thaw()
|--- ast_post_gpu()
Except this, all other code path have pci_enable_device() or
pcim_enable_device() called.
So, this patch seems OK.
On 2023/7/12 21:08, Thomas
On Mon, Jul 17, 2023 at 04:52:51PM +0200, Andrzej Hajda wrote:
>
>
> On 17.07.2023 08:22, Su Hui wrote:
> > Clang warning: drivers/gpu/drm/i915/display/intel_tv.c:
> > line 991, column 22 Division by zero.
> > Assuming tv_mode->oversample=1 and (!tv_mode->progressive)=1,
> > then division by
On 2023-07-17 18:45, Asahi Lina wrote:
> On 18/07/2023 02.40, Luben Tuikov wrote:
>> On 2023-07-16 03:51, Asahi Lina wrote:
>>> On 15/07/2023 16.14, Luben Tuikov wrote:
On 2023-07-14 04:21, Asahi Lina wrote:
> drm_sched_fini() currently leaves any pending jobs dangling, which
> causes
Hi,
I have tested this patch on my x86-64(i3-8100, H110 D4L board) + ast2400
discrete BMC card just now,
drm/ast still works on normal case.
But originally this function is called in ast_post_gpu() function.
ast_post_gpu() doesn't happen on my test case.
I know something about the POST
On Sun, Jul 09, 2023 at 07:19:21AM +0300, Dmitry Baryshkov wrote:
> Implement DisplayPort support for the Qualcomm RB5 platform.
>
> Note: while testing this, I had link training issues with several
> dongles with DP connectors. Other DisplayPort-USB-C dongles (with HDMI
> or VGA connectors) work
[AMD Official Use Only - General]
Hi Wenyou,
I think you already got the greenlight(RB from Mario and ACK from me) to land
the change.
Go ahead please.
Evan
> -Original Message-
> From: Yang, WenYou
> Sent: Thursday, July 13, 2023 8:56 AM
> To: Yang, WenYou ; Deucher, Alexander
> ;
This patch will enable VCN FW workaround using
DRM KEY INJECT WORKAROUND method,
which is helping in fixing the secure playback.
Signed-off-by: sguttula
---
Changes in v2:
-updated commit message as per veera's feedback
Changes in v3:
-updated commit message as enabling for 402
-updated the
Hi Jagan,
On Monday, July 17, 2023 2:44 PM Jagan Teki wrote:
> On Mon, Jul 17, 2023 at 11:44 AM Liu Ying wrote:
> >
> > Freescale i.MX93 SoC embeds a Synopsys Designware MIPI DSI host
> > controller and a Synopsys Designware MIPI DPHY. Some configurations
> > and extensions to them are
On 18/07/2023 00.55, Christian König wrote:
Am 15.07.23 um 16:14 schrieb aly...@rosenzweig.io:
15 July 2023 at 00:03, "Luben Tuikov" wrote:
On 2023-07-14 05:57, Christian König wrote:
Am 14.07.23 um 11:49 schrieb Asahi Lina:
On 14/07/2023 17.43, Christian König wrote:
Am 14.07.23 um
Add the device link when panel bridge is attached and delete the link
when panel bridge is detached. The drm device is the consumer while
the panel device is the supplier. This makes sure that the drm device
suspends eariler and resumes later than the panel device, hence resolves
problems where
Hi Alexander,
Thanks for your comments,
>
> Am Montag, 17. Juli 2023, 10:03:49 CEST schrieb Sandor Yu:
> >
> > Achtung externe E-Mail: Öffnen Sie Anhänge und Links nur, wenn Sie
> > wissen, dass diese aus einer sicheren Quelle stammen und sicher sind.
> > Leiten Sie die
Clang warning: drivers/gpu/drm/i915/display/intel_tv.c:
line 991, column 22 Division by zero.
Assuming tv_mode->oversample=1 and (!tv_mode->progressive)=1,
then division by zero will happen.
Fixes: 1bba5543e4fe ("drm/i915: Fix TV encoder clock computation")
Signed-off-by: Su Hui
---
On 2023/7/17 22:52, Andrzej Hajda wrote:
On 17.07.2023 08:22, Su Hui wrote:
Clang warning: drivers/gpu/drm/i915/display/intel_tv.c:
line 991, column 22 Division by zero.
Assuming tv_mode->oversample=1 and (!tv_mode->progressive)=1,
then division by zero will happen.
Fixes: 1bba5543e4fe
On Tue, Jul 18, 2023 at 5:41 AM Lucas De Marchi
wrote:
>
> On Fri, Jul 07, 2023 at 11:41:48AM -0700, Luis Chamberlain wrote:
> >On Tue, Jul 04, 2023 at 12:50:50PM +1000, Dave Airlie wrote:
> >> From: Dave Airlie
> >>
> >> This adds two tags that will go into the module info.
> >>
> >> The first
Hi,
I notice a regression report on Bugzilla [1]. Quoting from it:
> Hi,
>
> After I updated to 6.4 through Archlinux kernel update, suddenly I noticed
> random packet losses on my routers like nodes. I have these networking
> relevant config on my nodes
>
> 1. Using archlinux
> 2. Network
On 2023/7/17 18:25, David Hildenbrand wrote:
On 12.07.23 16:38, Kefeng Wang wrote:
Use the helpers to simplify code.
Signed-off-by: Kefeng Wang
---
fs/proc/task_mmu.c | 24
fs/proc/task_nommu.c | 15 +--
2 files changed, 5 insertions(+), 34
On 7/14/2023 6:38 PM, Dmitry Baryshkov wrote:
On 15/07/2023 03:59, Jessica Zhang wrote:
On 7/14/2023 3:30 PM, Dmitry Baryshkov wrote:
On Fri, 14 Jul 2023 at 22:03, Jessica Zhang
wrote:
On 7/13/2023 6:23 PM, Dmitry Baryshkov wrote:
On 14/07/2023 03:21, Jessica Zhang wrote:
DSI 6G
Hi Matt,
> > > > > + /*
> > > > > + * Aux invalidations on Aux CCS platforms require
> > > > > + * memory traffic is quiesced prior.
> > > > > + */
> > > > > + if ((mode & EMIT_INVALIDATE) && !HAS_FLAT_CCS(engine->i915))
> > > >
> > > > It's a pre-existing mistake in
From: Luc Ma
Signed-off-by: Luc Ma
---
drivers/dma-buf/dma-buf-sysfs-stats.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma-buf/dma-buf-sysfs-stats.c
b/drivers/dma-buf/dma-buf-sysfs-stats.c
index 6cfbbf0720bd..b5b62e40ccc1 100644
---
On Tue, 27 Jun 2023 22:14:15 +0200, Marijn Suijten wrote:
> Bring up the SM6125 DPU now that all preliminary series (such as INTF
> TE) have been merged (for me to test the hardware properly), and most
> other conflicting work (barring ongoing catalog *improvements*) has made
> its way in as
On Fri, 07 Jul 2023 22:39:31 +0300, Dmitry Baryshkov wrote:
> Apply several cleanups to the DPU's core_perf module.
>
> Changes since v2:
> - Dropped perf tuning patches for now (Abhinav)
> - Restored kms variable assignment in dpu_core_perf_crtc_release_bw
> (LKP)
> - Fixed description for
On Tue, 04 Jul 2023 12:01:04 -0400, Jonathan Marek wrote:
> Note that with this, DMA4/DMA5 are still non-functional, but at least
> display *something* in modetest instead of nothing or underflow.
>
>
Applied, thanks!
[1/1] drm/msm/dpu: add missing flush and fetch bits for DMA4/DMA5 planes
On Wed, 12 Jul 2023 15:11:37 +0300, Dmitry Baryshkov wrote:
> Per agreement with Konrad, picked up this patch series.
>
> Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
> another path that needs to be handled to ensure MDSS functions properly,
> namely the "reg bus", a.k.a
Due to a change in the auth flow on MTL, GuC 70.7.0 and newer will only
be able to authenticate HuC 8.5.1 and newer. The plan is to update the 2
binaries synchronously in linux-firmware so that the fw repo always has
a matching pair that works; still, it's better to check in the kernel so
we can
Hello, Geert.
Can you please the following patch and see how many reports you get? Looking
back at your reports, I think some of them probably should be converted to
UNBOUND but we should have a better idea with the adjusted threshold.
Thanks.
>From 8555cbd4b22e5f85eb2bdcb84fd1d1f519a0a0d3 Mon
On Mon, 17 Jul 2023 19:12:16 -0300
Jason Gunthorpe wrote:
> On Mon, Jul 17, 2023 at 01:08:31PM -0600, Alex Williamson wrote:
>
> > What would that mechanism be? We've been iterating on getting the
> > serialization and buffering correct, but I don't know of another means
> > that combines the
On 18/07/2023 02.40, Luben Tuikov wrote:
On 2023-07-16 03:51, Asahi Lina wrote:
On 15/07/2023 16.14, Luben Tuikov wrote:
On 2023-07-14 04:21, Asahi Lina wrote:
drm_sched_fini() currently leaves any pending jobs dangling, which
causes segfaults and other badness when job completion fences are
drm_bridge_hpd_enable()/drm_bridge_hpd_disable() callbacks call into
the respective driver's hpd_enable()/hpd_disable() ops. These ops control
the HPD enable/disable logic which in some cases like MSM can be a
dedicate hardware block to control the HPD.
During probe_defer cases, a connector can
On Mon, Jul 17, 2023 at 01:08:31PM -0600, Alex Williamson wrote:
> What would that mechanism be? We've been iterating on getting the
> serialization and buffering correct, but I don't know of another means
> that combines the notification with a value, so we'd likely end up with
> an eventfd
On Thu, Jul 13, 2023 at 03:06:36PM -0700, Rob Clark wrote:
>
> On Thu, Jul 13, 2023 at 2:39 PM Akhil P Oommen
> wrote:
> >
> > On Fri, Jul 07, 2023 at 06:45:42AM +0300, Dmitry Baryshkov wrote:
> > >
> > > On 07/07/2023 00:10, Rob Clark wrote:
> > > > From: Rob Clark
> > > >
> > > > Since the
Hi Matt,
On Mon, Jul 17, 2023 at 01:27:09PM -0700, Matt Roper wrote:
> On Mon, Jul 17, 2023 at 07:30:59PM +0200, Andi Shyti wrote:
> > Perform some refactoring with the purpose of keeping in one
> > single place all the operations around the aux table
> > invalidation.
> >
> > With this
On Thu, Jul 13, 2023 at 03:25:33PM -0700, Rob Clark wrote:
>
> On Thu, Jul 13, 2023 at 1:06 PM Akhil P Oommen
> wrote:
> >
> > On Thu, Jul 06, 2023 at 02:10:38PM -0700, Rob Clark wrote:
> > >
> > > From: Rob Clark
> > >
> > > It is better to explicitly list it. With the move to opaque
On Mon, Jul 17, 2023 at 11:52:25PM +0200, Andi Shyti wrote:
> Hi Matt,
>
> On Mon, Jul 17, 2023 at 01:31:03PM -0700, Matt Roper wrote:
> > On Mon, Jul 17, 2023 at 10:54:37AM -0700, Matt Roper wrote:
> > > On Mon, Jul 17, 2023 at 07:30:55PM +0200, Andi Shyti wrote:
> > > > From: Jonathan Cavitt
>
Hi Andrzej,
On Mon, Jul 17, 2023 at 09:11:26PM +0200, Andrzej Hajda wrote:
> On 17.07.2023 19:30, Andi Shyti wrote:
> > Perform some refactoring with the purpose of keeping in one
> > single place all the operations around the aux table
> > invalidation.
> >
> > With this refactoring add more
Hi Andrzej,
On Mon, Jul 17, 2023 at 08:21:40PM +0200, Andrzej Hajda wrote:
> On 17.07.2023 19:30, Andi Shyti wrote:
> > In preparation of the next patch allign with the datasheet (BSPEC
> > 47112) with the naming of the pipe control set of flag values.
> > The variable "flags" in
Hi Matt,
On Mon, Jul 17, 2023 at 01:31:03PM -0700, Matt Roper wrote:
> On Mon, Jul 17, 2023 at 10:54:37AM -0700, Matt Roper wrote:
> > On Mon, Jul 17, 2023 at 07:30:55PM +0200, Andi Shyti wrote:
> > > From: Jonathan Cavitt
> > >
> > > All memory traffic must be quiesced before requesting
> > >
Hi,
On Tue, Jul 11, 2023 at 2:12 AM Chen-Yu Tsai wrote:
>
> This panel is found at least on the MT8183-based Juniper Chromebook,
> also known as the Acer Chromebook Spin 311. It matches the common
> delay_200_500_e50 set of delay timings.
>
> Add an entry for it.
>
> Signed-off-by: Chen-Yu Tsai
On 7/7/2023 5:04 PM, Dmitry Baryshkov wrote:
On 08/07/2023 02:52, Kuogee Hsieh wrote:
Incorporating pm runtime framework into DP driver so that power
and clock resource handling can be centralized allowing easier
control of these resources in preparation of registering aux bus
uring probe.
On 7/17/2023 10:22 AM, Dmitry Baryshkov wrote:
On 17/07/2023 20:16, Kuogee Hsieh wrote:
On 7/10/2023 11:13 AM, Dmitry Baryshkov wrote:
On 10/07/2023 19:57, Kuogee Hsieh wrote:
On 7/7/2023 5:11 PM, Dmitry Baryshkov wrote:
On 08/07/2023 02:52, Kuogee Hsieh wrote:
In preparation of moving
On Mon, Jul 17, 2023 at 10:54:37AM -0700, Matt Roper wrote:
> On Mon, Jul 17, 2023 at 07:30:55PM +0200, Andi Shyti wrote:
> > From: Jonathan Cavitt
> >
> > All memory traffic must be quiesced before requesting
> > an aux invalidation on platforms that use Aux CCS.
> >
> > Fixes: 972282c4cf24
On Mon, Jul 17, 2023 at 07:30:59PM +0200, Andi Shyti wrote:
> Perform some refactoring with the purpose of keeping in one
> single place all the operations around the aux table
> invalidation.
>
> With this refactoring add more engines where the invalidation
> should be performed.
>
> Fixes:
On Mon, Jul 17, 2023 at 07:30:58PM +0200, Andi Shyti wrote:
> From: Jonathan Cavitt
>
> For platforms that use Aux CCS, wait for aux invalidation to
> complete by checking the aux invalidation register bit is
> cleared.
>
> Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all
On Fri, Jul 07, 2023 at 11:41:48AM -0700, Luis Chamberlain wrote:
On Tue, Jul 04, 2023 at 12:50:50PM +1000, Dave Airlie wrote:
From: Dave Airlie
This adds two tags that will go into the module info.
The first denotes a group of firmwares, when that tag is present all
MODULE_FIRMWARE lines
On Mon, Jul 17, 2023 at 07:30:57PM +0200, Andi Shyti wrote:
> Enable the CCS_FLUSH bit 13 in the control pipe for render and
> compute engines in platforms starting from Meteor Lake (BSPEC
> 43904 and 47112).
>
> Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all
> engines")
Hi Christian,
I believe that `select DRM_EXEC` is missing on v3d's Kconfig file. If
we don't select it, we will get some compilation errors.
Apart from this problem, I ran some tests on the RPi 4 and didn't see
any problems.
Best Regards,
- Maíra
On 7/12/23 09:47, Christian König wrote:
Just
On 17.07.2023 19:30, Andi Shyti wrote:
Perform some refactoring with the purpose of keeping in one
single place all the operations around the aux table
invalidation.
With this refactoring add more engines where the invalidation
should be performed.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux
On Mon, 17 Jul 2023 10:29:34 +0200
Grzegorz Jaszczyk wrote:
> pt., 14 lip 2023 o 09:05 Christian Brauner napisał(a):
> >
> > On Thu, Jul 13, 2023 at 11:10:54AM -0600, Alex Williamson wrote:
> > > On Thu, 13 Jul 2023 12:05:36 +0200
> > > Christian Brauner wrote:
> > >
> > > > Hey everyone,
Hi André, thanks for review!
On 7/12/23 20:30, André Almeida wrote:
Hi Carlos,
Em 27/06/2023 15:22, Carlos Eduardo Gallo Filho escreveu:
[...]
So, replace each drm_framebuffer_plane_{width,height} and
fb_plane_{width,height} call to drm_format_info_plane_{width,height}
and remove them.
I
On Mon, 17 Jul 2023 at 21:45, Abhinav Kumar wrote:
>
>
>
> On 7/12/2023 3:11 PM, Dmitry Baryshkov wrote:
> > In preparation to refactoring the dpu_core_perf debugfs interface,
> > extract the bandwidth aggregation function from
> > _dpu_core_perf_crtc_update_bus().
> >
> > Signed-off-by: Dmitry
On 17.07.2023 19:30, Andi Shyti wrote:
From: Jonathan Cavitt
For platforms that use Aux CCS, wait for aux invalidation to
complete by checking the aux invalidation register bit is
cleared.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan
All error handling paths go to 'out', except this one. Be consistent and
also branch to 'out' here.
Fixes: c10a652e239e ("drm/i915/selftests: Rework context handling in hugepages
selftests")
Signed-off-by: Christophe JAILLET
---
/!\ Speculative /!\
This patch is based on analysis of the
Thanks for cleaning this.
With Matt's suggestion, this is
Reviewed-by: Nirmoy Das
On 7/17/2023 7:30 PM, Andi Shyti wrote:
In preparation of the next patch allign with the datasheet (BSPEC
47112) with the naming of the pipe control set of flag values.
The variable "flags" in
On 7/12/2023 3:11 PM, Dmitry Baryshkov wrote:
In preparation to refactoring the dpu_core_perf debugfs interface,
extract the bandwidth aggregation function from
_dpu_core_perf_crtc_update_bus().
Signed-off-by: Dmitry Baryshkov
---
Drop the core_perf tag from the subject line.
The debugfs
On 7/12/2023 3:11 PM, Dmitry Baryshkov wrote:
The values in struct dpu_core_perf_tune are fixed per the core perf
mode. Drop the 'tune' values and substitute them with known values when
performing perf management.
Note: min_bus_vote was not used at all, so it is just silently dropped.
On 7/12/2023 3:11 PM, Dmitry Baryshkov wrote:
Simplify dpu_core_perf code by using only dpu_perf_cfg instead of using
full-featured catalog data.
Acked-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 73 ---
Hi, Lucas
Thanks for you guidance!
On 2023/7/17 17:51, Lucas Stach wrote:
Hi Jingfeng,
Am Freitag, dem 23.06.2023 um 18:08 +0800 schrieb Sui Jingfeng:
From: Sui Jingfeng
Because it is not used by the etnaviv_gem_new_impl() function,
no functional change.
I think it would make sense to
On 17.07.2023 19:30, Andi Shyti wrote:
Enable the CCS_FLUSH bit 13 in the control pipe for render and
compute engines in platforms starting from Meteor Lake (BSPEC
43904 and 47112).
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Andi Shyti
Cc:
On 17.07.2023 19:30, Andi Shyti wrote:
In preparation of the next patch allign with the datasheet (BSPEC
47112) with the naming of the pipe control set of flag values.
The variable "flags" in gen12_emit_flush_rcs() is applied as a
set of flags called Bit Group 1.
Define also the Bit Group 0 as
On 7/12/2023 10:03, Ceraolo Spurio, Daniele wrote:
On 7/12/2023 3:03 AM, Andrzej Hajda wrote:
On 11.07.2023 22:31, Daniele Ceraolo Spurio wrote:
Due to a change in the auth flow on MTL, GuC 70.7.0 and newer will only
be able to authenticate HuC 8.5.1 and newer. The plan is to update
the 2
Benjamin,
On Mon, Jun 26, 2023 at 3:49 PM Doug Anderson wrote:
>
> Benjamin,
>
> On Thu, Jun 8, 2023 at 8:37 AM Benjamin Tissoires
> wrote:
> >
> > > +static const struct drm_panel_follower_funcs
> > > i2c_hid_core_panel_follower_funcs = {
> > > + .panel_prepared =
On 7/12/2023 3:11 PM, Dmitry Baryshkov wrote:
dpu_core_perf should not make decisions on the maximum possible core
clock rate. Pass the value from dpu_kms_hw_init().
Signed-off-by: Dmitry Baryshkov
Also mention that with this, you are dropping the now unused core_clk
handle in the
On 7/12/2023 3:11 PM, Dmitry Baryshkov wrote:
This function does nothing, just clears one struct field. Drop it now.
Acked-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 10 --
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h |
On Mon, Jul 17, 2023 at 07:30:56PM +0200, Andi Shyti wrote:
> In preparation of the next patch allign with the datasheet (BSPEC
s/allign/align/
Otherwise,
Reviewed-by: Matt Roper
> 47112) with the naming of the pipe control set of flag values.
> The variable "flags" in gen12_emit_flush_rcs()
On 7/12/2023 3:11 PM, Dmitry Baryshkov wrote:
The dev_pm_opp_set_rate() already contains a call for clk_round_rate for
the passed value. Stop calling it manually from
_dpu_core_perf_get_core_clk_rate(). It is slightly incorrect to call it
this way, as we should round the final calculated
On Mon, Jul 17, 2023 at 07:30:55PM +0200, Andi Shyti wrote:
> From: Jonathan Cavitt
>
> All memory traffic must be quiesced before requesting
> an aux invalidation on platforms that use Aux CCS.
>
> Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all
> engines")
>
On 17.07.2023 14:51, Andi Shyti wrote:
From: Jonathan Cavitt
All memory traffic must be quiesced before requesting
an aux invalidation on platforms that use Aux CCS.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt
Signed-off-by:
On 2023-07-16 03:51, Asahi Lina wrote:
> On 15/07/2023 16.14, Luben Tuikov wrote:
>> On 2023-07-14 04:21, Asahi Lina wrote:
>>> drm_sched_fini() currently leaves any pending jobs dangling, which
>>> causes segfaults and other badness when job completion fences are
>>> signaled after the scheduler
On 17.07.2023 14:51, Andi Shyti wrote:
Fix the 'NV' definition postfix that is supposed to be INV.
Take the chance to also order properly the registers based on
their address and call the GEN12_GFX_CCS_AUX_INV address as
GEN12_CCS_AUX_INV like all the other similar registers.
Remove also VD1,
Hi,
On Mon, Jul 17, 2023 at 07:30:56PM +0200, Andi Shyti wrote:
> In preparation of the next patch allign with the datasheet (BSPEC
> 47112) with the naming of the pipe control set of flag values.
> The variable "flags" in gen12_emit_flush_rcs() is applied as a
> set of flags called Bit Group 1.
In preparation of the next patch allign with the datasheet (BSPEC
47112) with the naming of the pipe control set of flag values.
The variable "flags" in gen12_emit_flush_rcs() is applied as a
set of flags called Bit Group 1.
Define also the Bit Group 0 as bit_group_0 where currently only
Enable the CCS_FLUSH bit 13 in the control pipe for render and
compute engines in platforms starting from Meteor Lake (BSPEC
43904 and 47112).
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Andi Shyti
Cc: Jonathan Cavitt
Cc: Nirmoy Das
Cc: #
Perform some refactoring with the purpose of keeping in one
single place all the operations around the aux table
invalidation.
With this refactoring add more engines where the invalidation
should be performed.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
From: Jonathan Cavitt
For platforms that use Aux CCS, wait for aux invalidation to
complete by checking the aux invalidation register bit is
cleared.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi Shyti
Cc:
From: Jonathan Cavitt
All memory traffic must be quiesced before requesting
an aux invalidation on platforms that use Aux CCS.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi Shyti
Cc: # v5.8+
---
Fix the 'NV' definition postfix that is supposed to be INV.
Take the chance to also order properly the registers based on
their address and call the GEN12_GFX_CCS_AUX_INV address as
GEN12_CCS_AUX_INV like all the other similar registers.
Remove also VD1, VD3 and VE1 registers that don't exist.
Hi,
as there are new hardware directives, we need a little adaptation
for the AUX invalidation sequence.
In this version we support all the engines affected by this
change.
The stable backport has some challenges because the original
patch that this series fixes has had more changes in between.
This patch will enable secure decode playback on VCN4_0_2
Signed-off-by: sguttula
---
Changes in v2:
-updated commit message only enabling for VCN402
-updated the logic as per Leo's feedback
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
On Thu, Jun 29, 2023 at 02:10:58PM -0700, Welty, Brian wrote:
>
> Hi Christian / Thomas,
>
> Wanted to ask if you have explored or thought about adding support in TTM
> such that a ttm_bo could have more than one underlying backing store segment
> (that is, to have a tree of ttm_resources)?
> We
Hi,
On 2023/7/10 15:47, Maxime Ripard wrote:
The new helper to init the locking context allows to remove some
boilerplate.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/tests/vc4_test_pv_muxing.c | 42 --
1 file changed, 19 insertions(+), 23 deletions(-)
On 17/07/2023 20:16, Kuogee Hsieh wrote:
On 7/10/2023 11:13 AM, Dmitry Baryshkov wrote:
On 10/07/2023 19:57, Kuogee Hsieh wrote:
On 7/7/2023 5:11 PM, Dmitry Baryshkov wrote:
On 08/07/2023 02:52, Kuogee Hsieh wrote:
In preparation of moving edp of_dp_aux_populate_bus() to
On 7/10/2023 11:13 AM, Dmitry Baryshkov wrote:
On 10/07/2023 19:57, Kuogee Hsieh wrote:
On 7/7/2023 5:11 PM, Dmitry Baryshkov wrote:
On 08/07/2023 02:52, Kuogee Hsieh wrote:
In preparation of moving edp of_dp_aux_populate_bus() to
dp_display_probe(), move dp_display_request_irq(),
Hi,
On 2023/7/10 15:47, Maxime Ripard wrote:
As we get more and more tests, the locking context initialisation
creates more and more boilerplate, both at creation and destruction.
Let's create a helper that will allocate, initialise a context, and
register kunit actions to clean up once the
Hi,
On 2023/7/10 15:47, Maxime Ripard wrote:
As we get more and more tests, the locking context initialisation
creates more and more boilerplate, both at creation and destruction.
Let's create a helper that will allocate, initialise a context, and
register kunit actions to clean up once the
From: Tvrtko Ursulin
User feedback indicates significant performance gains are possible in
specific games with non default RPS up/down thresholds.
Expose these tunables via sysfs which will allow users to achieve best
performance when running games and best power efficiency elsewhere.
Note
From: Tvrtko Ursulin
In preparation for exposing via sysfs add helpers for managing rps
thresholds.
v2:
* Force sw and hw re-programming on threshold change.
Signed-off-by: Tvrtko Ursulin
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
Reviewed-by: Andi Shyti
---
From: Tvrtko Ursulin
Since 36d516be867c ("drm/i915/gt: Switch to manual evaluation of RPS")
thresholds are invariant so lets move their setting to init time.
Signed-off-by: Tvrtko Ursulin
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
Reviewed-by: Andi Shyti
---
From: Tvrtko Ursulin
Record the default values as preparation for exposing the sysfs controls.
Signed-off-by: Tvrtko Ursulin
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++
drivers/gpu/drm/i915/gt/intel_rps.c | 2
Geert reports that the following NULL pointer dereference happens for him
after commit 49d7d581ceaf ("drm/ssd130x: Don't allocate buffers on each
plane update"):
[drm] Initialized ssd130x 1.0.0 20220131 for 0-003c on minor 0
ssd130x-i2c 0-003c: [drm] surface width(128), height(32), bpp(1)
On Wed, Jul 12, 2023 at 8:57 AM Chen-Yu Tsai wrote:
>
> From: Pin-yen Lin
>
> These two drivers embed a i2c_client in their private driver data, but
> only strict device is actually needed. Replace the i2c_client reference
> with a struct device one.
>
> Signed-off-by: Pin-yen Lin
>
On Mon, 10 Jul 2023 17:12:01 +0800, Chen-Yu Tsai wrote:
> The DRM DP code has macros for the DP HDCP capabilities. Use them in the
> anx7625 driver instead of raw numbers.
>
>
Applied, thanks!
[1/1] drm/bridge: anx7625: Use common macros for HDCP capabilities
On Mon, Jul 10, 2023 at 10:59 AM Chen-Yu Tsai wrote:
>
> The device lock is used to serialize the low level power sequencing
> operations. Since drm_helper_hpd_irq_event() could end up calling
> .atomic_enable, which also calls power sequencing functions through
> runtime PM, this results in a
Am 15.07.23 um 16:14 schrieb aly...@rosenzweig.io:
15 July 2023 at 00:03, "Luben Tuikov" wrote:
On 2023-07-14 05:57, Christian König wrote:
Am 14.07.23 um 11:49 schrieb Asahi Lina:
On 14/07/2023 17.43, Christian König wrote:
Am 14.07.23 um 10:21 schrieb Asahi Lina:
A signaled
On Mon, Jul 17, 2023 at 03:34:13PM +0200, Geert Uytterhoeven wrote:
> Both the patform_driver and mipi_dsi_driver structures contain pointers
> to the match table used, so the custom code to obtain match and match
> data can be replaced by calls to of_device_get_match_data().
>
> Signed-off-by:
Hi,
On 2023/7/10 15:47, Maxime Ripard wrote:
Hi,
Since v6.5-rc1, kunit gained a devm/drmm-like mechanism that makes tests
resources much easier to cleanup.
This series converts the existing tests to use those new actions were
relevant.
Is the word 'were' here means that 'where' relevant ?
On Sat, Jul 15, 2023 at 12:34 PM Thomas Zimmermann wrote:
>
> Hi
>
> Am 14.07.23 um 19:50 schrieb Rob Herring:
> > The DT of_device.h and of_platform.h date back to the separate
> > of_platform_bus_type before it as merged into the regular platform bus.
> > As part of that merge prepping Arm DT
On Mon, 10 Jul 2023 17:09:27 +0800, Chen-Yu Tsai wrote:
> The DRM DP code has macros for the DP power sequencing commands. Use
> them in the anx7625 driver instead of raw numbers.
>
>
Applied, thanks!
[1/1] drm/bridge: anx7625: Use common macros for DP power sequencing commands
On Mon, Jul 17, 2023 at 03:23:20PM +0200, Geert Uytterhoeven wrote:
> Fix misspellings of "semaphore".
>
> Signed-off-by: Geert Uytterhoeven
> Reviewed-by: Hamza Mahfooz
> ---
> v2:
> - Add Reviewed-by.
> ---
> drivers/gpu/drm/i915/i915_request.c | 2 +-
> drivers/gpu/drm/radeon/cik.c
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