the former issue by using the same cycle selection as used in the
I2C_M_RD for the write case.
GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0)
Fixed the latter by waiting on GMBUS_ACTIVE to deassert before disable.
Signed-off-by: Benson Leung ble...@chromium.org
Reviewed-by: Daniel
80 col, spaces around operators and other basic cleanup.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c | 24
1 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915
in the i2c-core using the i2c adapter lock.
This patch adds a mutex to serialize access to the gmbus_xfer routine.
Note: the same mutex serializes both bit banged and native xfers.
Signed-off-by: Yufeng Shen mile...@chromium.org
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915
:
intel_modeset_init()
intel_setup_outputs()
intel_lvds_init()
drm_get_edid()
Is there a way to switch the order of these to events?
Or does it make more sense for the gmbus driver to check a bool irq_enabled,
and choose whether to poll or use the GMBUS interrupt?
... or both?
Daniel
.
However, the driver immediately falls back again to the bit-bang
method, which correctly uses GPIOF, so again, transfers succeed.
However, if gmbus mode is re-enabled and the GPIO fall-back mode is
disabled, then reading an attached monitor's EDID fail.
Signed-off-by: Daniel Kurtz djku
for another patch. We return -ETIMEDOUT if the hardware doesn't
deactivate after the STOP cycle.
This patch also takes advantage (in the write path) of the double-buffered
GMBUS3 data register by writing two 4-byte words before the first wait for
HW_RDY.
Signed-off-by: Daniel Kurtz djku
.
Tested on Sandybridge (gen 6, PCH == CougarPoint) hardware.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/i915_reg.h |1 -
drivers/gpu/drm/i915/intel_i2c.c | 64 ++
2 files changed, 30 insertions(+), 35 deletions(-)
diff --git
in if condition'), but it seems
like the cleanest implementation.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c | 19 ++-
1 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915
such a small write followed by a read. The INDEX can be either one or two
bytes long. The advantage of using such a cycle is that the CPU has
slightly less work to do once the read with INDEX cycle is started.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c
Return -ENXIO if a device NAKs a transaction.
Note: We should return -ETIMEDOUT, too if the transaction times out,
however, that error path is currently handled by the 'bit-bang fallback'.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c |4 +++-
1 files
before
intel_gmbus_get_bus().
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/i915_drv.h|4 +++-
drivers/gpu/drm/i915/intel_bios.c | 10 ++
drivers/gpu/drm/i915/intel_crt.c | 13 ++---
drivers/gpu/drm/i915/intel_drv.h |3 ++-
drivers
On Wed, Mar 7, 2012 at 8:12 PM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, 7 Mar 2012 19:50:47 +0800, Daniel Kurtz djku...@chromium.org wrote:
Return -ENXIO if a device NAKs a transaction.
Note: We should return -ETIMEDOUT, too if the transaction times out,
however, that error path
On Wed, Mar 7, 2012 at 8:17 PM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, 7 Mar 2012 19:50:45 +0800, Daniel Kurtz djku...@chromium.org wrote:
There is no disabled port 0. So, don't even try to initialize/scan
it, etc. This saves a bit of time when initializing the driver, since
On Wed, Mar 7, 2012 at 9:23 PM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, 7 Mar 2012 19:50:43 +0800, Daniel Kurtz djku...@chromium.org
wrote:
According to i915 documentation [1], Port D (DP/HDMI Port D) is
actually gmbus pin pair 6 (gmbus0.2:0 == 110b GPIOF), not 7 (111b).
Pin
for the
review, Chris!), and adds the interrupt patch. There weren't any review
comments for patches 5, 7, or 8 of the first set. Hopefully they will get
more love the second time around :).
Daniel Kurtz (10):
drm/i915/intel_i2c: cleanup
drm/i915/intel_i2c: assign HDMI port D to pin pair 6
such a small write followed by a read. The INDEX can be either one or two
bytes long. The advantage of using such a cycle is that the CPU has
slightly less work to do once the read with INDEX cycle is started.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c
called before
intel_gmbus_get_adapter().
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/i915_drv.h|4 +++-
drivers/gpu/drm/i915/intel_bios.c | 11 +++
drivers/gpu/drm/i915/intel_crt.c | 13 ++---
drivers/gpu/drm/i915/intel_drv.h |3
.
However, the driver immediately falls back again to the bit-bang
method, which correctly uses GPIOF, so again, transfers succeed.
However, if gmbus mode is re-enabled and the GPIO fall-back mode is
disabled, then reading an attached monitor's EDID fail.
Signed-off-by: Daniel Kurtz djku
in the i2c-core using the i2c adapter lock.
This patch adds a mutex to serialize access to the gmbus_xfer routine.
Note: the same mutex serializes both bit banged and native xfers.
Signed-off-by: Yufeng Shen mile...@chromium.org
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915
on Sandybridge (gen 6, PCH == CougarPoint) hardware.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/i915_reg.h |1 -
drivers/gpu/drm/i915/intel_i2c.c | 64 +
2 files changed, 29 insertions(+), 36 deletions(-)
diff --git
Save the GMBUS2 value read while polling for state changes, and then
reuse this value when determining for which reason the loops were exited.
This is a small optimization which saves a couple of bus accesses for
memory mapped IO registers.
Signed-off-by: Daniel Kurtz djku...@chromium.org
Return -ENXIO if a device NAKs a transaction.
Note: We should return -ETIMEDOUT, too if the transaction times out,
however, that error path is currently handled by the 'bit-bang fallback'.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c | 12
80 col, spaces around operators and other basic cleanup.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c | 19 +--
1 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915
from any active gmbus transactions, changing the interrupt
enable is protected by the gmbus transaction mutex.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/i915_drv.h |2 +
drivers/gpu/drm/i915/i915_irq.c | 22 +-
drivers/gpu/drm/i915/i915_reg.h |1
for another patch. We return -ETIMEDOUT if the hardware doesn't
deactivate after the STOP cycle.
This patch also takes advantage (in the write path) of the double-buffered
GMBUS3 data register by writing two 4-byte words before the first wait for
HW_RDY.
Signed-off-by: Daniel Kurtz djku
.
However, the driver immediately falls back again to the bit-bang
method, which correctly uses GPIOF, so again, transfers succeed.
However, if gmbus mode is re-enabled and the GPIO fall-back mode is
disabled, then reading an attached monitor's EDID fail.
Signed-off-by: Daniel Kurtz djku
== CougarPoint) hardware.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/i915_drv.h |1 -
drivers/gpu/drm/i915/i915_reg.h |2 +-
drivers/gpu/drm/i915/intel_i2c.c | 63 ++---
3 files changed, 25 insertions(+), 41 deletions(-)
diff --git
for IDLE before clearing NAK
Daniel Kurtz (11):
drm/i915/intel_i2c: cleanup
drm/i915/intel_i2c: assign HDMI port D to pin pair 6
drm/i915/intel_i2c: use i2c pre/post_xfer functions to setup gpio
xfers
drm/i915/intel_i2c: cleanup gmbus/gpio pin assignments
drm/i915/intel_i2c: allocate
80 col, spaces around operators and other basic cleanup.
Some info message cleanup.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c | 32 +---
1 files changed, 21 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915
such a small write followed by a read. The INDEX can be either one or two
bytes long. The advantage of using such a cycle is that the CPU has
slightly less work to do once the read with INDEX cycle is started.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c
gmbus_func
use .force_bit to determine which i2c functionalities are available,
either i2c_bit_algo.functionality, or its own.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c | 72 +++--
1 files changed, 45 insertions(+), 27 deletions
there is device present on the bus with a given address.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index a04f773
This memory is always allocated, and it is always a fixed size, so just
allocate it along with the rest of the driver state.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
drivers/gpu/drm/i915/intel_i2c.c | 10 --
2 files changed, 1
Save the GMBUS2 value read while polling for state changes, and then
reuse this value when determining for which reason the loops were exited.
This is a small optimization which saves a couple of bus accesses for
memory mapped IO registers.
Signed-off-by: Daniel Kurtz djku...@chromium.org
for another patch. We return -ETIMEDOUT if the hardware doesn't
deactivate after the STOP cycle.
This patch also takes advantage (in the write path) of the double-buffered
GMBUS3 data register by writing two 4-byte words before the first wait for
HW_RDY.
Signed-off-by: Daniel Kurtz djku
a safer default
pin pair.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/i915_drv.h|7 +++
drivers/gpu/drm/i915/intel_bios.c |4 ++--
drivers/gpu/drm/i915/intel_crt.c | 14 --
drivers/gpu/drm/i915/intel_dvo.c |6 +++---
drivers/gpu/drm
On Mon, Mar 26, 2012 at 11:08 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Mar 26, 2012 at 04:47:11PM +0200, Daniel Vetter wrote:
On Mon, Mar 26, 2012 at 10:26:41PM +0800, Daniel Kurtz wrote:
According to i915 documentation [1], Port D (DP/HDMI Port D) is
actually gmbus pin pair 6
On Mon, Mar 26, 2012 at 10:49 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Mar 26, 2012 at 10:26:42PM +0800, Daniel Kurtz wrote:
Instead of rolling our own custom quirk_xfer function, use the bit_algo
pre_xfer and post_xfer functions to setup and teardown bit-banged
i2c transactions
. In these cases, the driver must fall back to using a safer default
port.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/i915_drv.h|7 +++
drivers/gpu/drm/i915/intel_bios.c |4 ++--
drivers/gpu/drm/i915/intel_crt.c | 14 --
drivers/gpu
instead of BUG_ON when an invalid port is requested
Daniel Kurtz (13):
drm/i915/intel_i2c: refactor gmbus_xfer
drm/i915/intel_i2c: cleanup error messages and comments
drm/i915/intel_i2c: assign HDMI port D to pin pair 6
drm/i915/intel_i2c: use i2c pre/post_xfer functions to setup gpio
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c | 11 +++
1 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 30675ce..e6c090b 100644
--- a/drivers/gpu/drm/i915
there is device present on the bus with a given address.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index c12db72..5a94e9b
.
However, the driver immediately falls back again to the bit-bang
method, which correctly uses GPIOF, so again, transfers succeed.
However, if gmbus mode is re-enabled and the GPIO fall-back mode is
disabled, then reading an attached monitor's EDID fail.
Signed-off-by: Daniel Kurtz djku
Split out gmbus_xfer_read/write() helper functions.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c | 151 +++---
1 files changed, 92 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu
This memory is always allocated, and it is always a fixed size, so just
allocate it along with the rest of the driver state.
Signed-off-by: Daniel Kurtz djku...@chromium.org
Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
drivers/gpu/drm/i915
such a small write followed by a read. The INDEX can be either one or two
bytes long. The advantage of using such a cycle is that the CPU has
slightly less work to do once the read with INDEX cycle is started.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c
== CougarPoint) hardware.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/i915_drv.h |3 +-
drivers/gpu/drm/i915/i915_reg.h |2 +-
drivers/gpu/drm/i915/intel_i2c.c | 70 ++---
3 files changed, 29 insertions(+), 46 deletions(-)
diff --git
The GMBUS controller GMBUS3 register is double-buffered. Take advantage
of this by writing two 4-byte words before the first wait for HW_RDY.
This helps keep the GMBUS controller from becoming idle during long writes.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915
Instead of rolling our own custom quirk_xfer function, use the bit_algo
pre_xfer and post_xfer functions to setup and teardown bit-banged
i2c transactions.
Signed-off-by: Daniel Kurtz djku...@chromium.org
Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_i2c.c
a ret variable
to store the wait_for macro return value.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c | 32
1 files changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm
for another patch. We return -ETIMEDOUT if the hardware doesn't
deactivate after the STOP cycle.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c | 30 +++---
1 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu
On Wed, Mar 28, 2012 at 3:14 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, 28 Mar 2012 02:36:17 +0800, Daniel Kurtz djku...@chromium.org wrote:
A common method of probing an i2c bus is trying to do a zero-length write.
Handle this case by checking the length first before decrementing
On Wed, Mar 28, 2012 at 3:02 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, 28 Mar 2012 02:36:22 +0800, Daniel Kurtz djku...@chromium.org wrote:
Save the GMBUS2 value read while polling for state changes, and then
reuse this value when determining for which reason the loops were
.
However, the driver immediately falls back again to the bit-bang
method, which correctly uses GPIOF, so again, transfers succeed.
However, if gmbus mode is re-enabled and the GPIO fall-back mode is
disabled, then reading an attached monitor's EDID fail.
Signed-off-by: Daniel Kurtz djku
Split out gmbus_xfer_read/write() helper functions.
Signed-off-by: Daniel Kurtz djku...@chromium.org
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_i2c.c | 151 +++---
1 files changed, 92 insertions(+), 59 deletions(-)
diff
Signed-off-by: Daniel Kurtz djku...@chromium.org
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_i2c.c | 11 +++
1 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index
Instead of rolling our own custom quirk_xfer function, use the bit_algo
pre_xfer and post_xfer functions to setup and teardown bit-banged
i2c transactions.
Signed-off-by: Daniel Kurtz djku...@chromium.org
Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch
Reviewed-by: Chris Wilson ch...@chris
This memory is always allocated, and it is always a fixed size, so just
allocate it along with the rest of the driver state.
Signed-off-by: Daniel Kurtz djku...@chromium.org
Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
drivers/gpu/drm/i915
in a bad state such that the next transaction may fail.
Also, return -ENXIO if a device NAKs a transaction.
Note: this patch also refactors gmbus_xfer to remove the done label.
Signed-off-by: Daniel Kurtz djku...@chromium.org
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915
The GMBUS controller GMBUS3 register is double-buffered. Take advantage
of this by writing two 4-byte words before the first wait for HW_RDY.
This helps keep the GMBUS controller from becoming idle during long writes.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915
== CougarPoint) hardware.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/i915_drv.h |3 +-
drivers/gpu/drm/i915/i915_reg.h |2 +-
drivers/gpu/drm/i915/intel_i2c.c | 70 ++---
3 files changed, 29 insertions(+), 46 deletions(-)
diff --git
such a small write followed by a read. The INDEX can be either one or two
bytes long. The advantage of using such a cycle is that the CPU has
slightly less work to do once the read with INDEX cycle is started.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c
. In these cases, the driver must fall back to using a safer default
port.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/i915_drv.h|7 +++
drivers/gpu/drm/i915/intel_bios.c |4 ++--
drivers/gpu/drm/i915/intel_crt.c | 14 --
drivers/gpu
remove them.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c |5 -
1 files changed, 0 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 2865313..be2852e 100644
--- a/drivers/gpu/drm
for another patch. We return -ETIMEDOUT if the hardware doesn't
deactivate after the STOP cycle.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c | 30 +++---
1 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu
there is device present on the bus with a given address.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index c12db72
instead of BUG_ON when an invalid port is requested
v5:
* fix bug in handle zero-length writes patch
* remove POSTING_READ() from gmbus transfers
Daniel Kurtz (14):
drm/i915/intel_i2c: refactor gmbus_xfer
drm/i915/intel_i2c: cleanup error messages and comments
drm/i915/intel_i2c: assign
a ret variable
to store the wait_for macro return value.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c | 33 +
1 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu
On Wed, Mar 28, 2012 at 9:05 PM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, 28 Mar 2012 20:51:57 +0800, Daniel Kurtz djku...@chromium.org wrote:
The POSTING_READ() calls were originally added to make sure the writes
were flushed before any timing delays and across loops.
However
in a bad state such that the next transaction may fail.
Also, return -ENXIO if a device NAKs a transaction.
Note: this patch also refactors gmbus_xfer to remove the done label.
Signed-off-by: Daniel Kurtz djku...@chromium.org
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915
there is device present on the bus with a given address.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index c12db72
such a small write followed by a read. The INDEX can be either one or two
bytes long. The advantage of using such a cycle is that the CPU has
slightly less work to do once the read with INDEX cycle is started.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c
it immediately precedes another I915_READ().
Daniel Kurtz (7):
drm/i915/intel_i2c: handle zero-length writes
drm/i915/intel_i2c: use double-buffered writes
drm/i915/intel_i2c: always wait for IDLE before clearing NAK
drm/i915/intel_i2c: use WAIT cycle, not STOP
drm/i915/intel_i2c: use INDEX cycles
a ret variable
to store the wait_for macro return value.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c | 34 ++
1 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu
The GMBUS controller GMBUS3 register is double-buffered. Take advantage
of this by writing two 4-byte words before the first wait for HW_RDY.
This helps keep the GMBUS controller from becoming idle during long writes.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915
The POSTING_READ() calls were originally added to make sure the writes
were flushed before any timing delays and across loops.
Now that the code has settled a bit, let's remove them.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c |3 ---
1 files changed
for another patch. We return -ETIMEDOUT if the hardware doesn't
deactivate after the STOP cycle.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c | 30 +++---
1 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu
On Thu, Mar 29, 2012 at 2:52 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Thu, 29 Mar 2012 02:26:37 +0800, Daniel Kurtz djku...@chromium.org wrote:
It is very common for an i2c device to require a small 1 or 2 byte write
followed by a read. For example, when reading from an i2c EEPROM
On Thu, Mar 29, 2012 at 2:48 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Thu, 29 Mar 2012 02:26:36 +0800, Daniel Kurtz djku...@chromium.org wrote:
The i915 is only able to generate a STOP cycle (i.e. finalize an i2c
transaction) during a DATA or WAIT phase. In other words
On Thu, Mar 29, 2012 at 2:41 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Thu, 29 Mar 2012 02:26:34 +0800, Daniel Kurtz djku...@chromium.org wrote:
The GMBUS controller GMBUS3 register is double-buffered. Take advantage
of this by writing two 4-byte words before the first wait
This patchset addresses a couple of issues with the i915 gmbus
implementation.
v7 adds a final patch to switch to using DRM_ERROR for reporting timeouts.
Daniel Kurtz (8):
drm/i915/intel_i2c: handle zero-length writes
drm/i915/intel_i2c: use double-buffered writes
drm/i915/intel_i2c
there is device present on the bus with a given address.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index c12db72
in a bad state such that the next transaction may fail.
Also, return -ENXIO if a device NAKs a transaction.
Note: this patch also refactors gmbus_xfer to remove the done label.
Signed-off-by: Daniel Kurtz djku...@chromium.org
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915
for another patch. We return -ETIMEDOUT if the hardware doesn't
deactivate after the STOP cycle.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c | 30 +++---
1 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu
such a small write followed by a read. The INDEX can be either one or two
bytes long. The advantage of using such a cycle is that the CPU has
slightly less work to do once the read with INDEX cycle is started.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c
a ret variable
to store the wait_for macro return value.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c | 34 ++
1 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu
The POSTING_READ() calls were originally added to make sure the writes
were flushed before any timing delays and across loops.
Now that the code has settled a bit, let's remove them.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c |3 ---
1 files changed
/IHD_OS_Vol3_Part3.pdf,
section 2.2.2)
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 73431ed..154fedd
would only trigger for transactions 4 bytes after 2 writes
to GMBUS3.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c | 14 +++---
1 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915
On Tue, Apr 10, 2012 at 6:41 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Apr 10, 2012 at 12:37:46PM +0200, Daniel Vetter wrote:
On Fri, Mar 30, 2012 at 07:46:39PM +0800, Daniel Kurtz wrote:
The i915 is only able to generate a STOP cycle (i.e. finalize an i2c
transaction) during a DATA
On Tue, Apr 10, 2012 at 11:03 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Apr 10, 2012 at 06:56:15PM +0800, Daniel Kurtz wrote:
On Tue, Apr 10, 2012 at 6:41 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Apr 10, 2012 at 12:37:46PM +0200, Daniel Vetter wrote:
On Fri, Mar 30, 2012 at 07
On Wed, Apr 11, 2012 at 5:34 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Tue, 10 Apr 2012 17:03:04 +0200, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Apr 10, 2012 at 06:56:15PM +0800, Daniel Kurtz wrote:
On Tue, Apr 10, 2012 at 6:41 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue
Some of these messages can be hit when userspace tries to probe the i2c
with nothing connected or if the driver code tries to do the same. See:
https://bugs.freedesktop.org/show_bug.cgi?id=48248
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c |7
there is device present on the bus with a given address.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/i915/intel_i2c.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index cab879f
On Thu, Apr 12, 2012 at 4:26 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Thu, 12 Apr 2012 02:17:46 +0800, Daniel Kurtz djku...@chromium.org wrote:
On Wed, Apr 11, 2012 at 5:34 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
The last major item on the wishlist is solving how to drive
It is a bit more precise to compute the total number of pixels first and
then divide, rather than multiplying the line pixel count by the
already-rounded line duration.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/drm_irq.c |6 +-
1 files changed, 5 insertions
On Wed, Dec 26, 2012 at 5:01 PM, Daniel Kurtz djku...@chromium.org wrote:
It is a bit more precise to compute the total number of pixels first and
then divide, rather than multiplying the line pixel count by the
already-rounded line duration.
Signed-off-by: Daniel Kurtz djku...@chromium.org
On Wed, Dec 26, 2012 at 5:01 PM, Daniel Kurtz djku...@chromium.org wrote:
It is a bit more precise to compute the total number of pixels first and
then divide, rather than multiplying the line pixel count by the
already-rounded line duration.
Signed-off-by: Daniel Kurtz djku...@chromium.org
If clock_gettime did fail, it would return -1 and set errno.
What we really want to strerror() is the errno.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
xf86drm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/xf86drm.c b/xf86drm.c
index 2a74c80..4791a05 100644
The following minor changes were needed to these headers:
* Convert // comments to /* */
* No , after final member of enum
With these changes, these header files can be included by a program that
is built with gcc options:
-std=c89 -Werror -pedantic
Signed-off-by: Daniel Kurtz djku
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