On Thu, Apr 12, 2012 at 4:26 AM, Chris Wilson
wrote:
> On Thu, 12 Apr 2012 02:17:46 +0800, Daniel Kurtz
> wrote:
>> On Wed, Apr 11, 2012 at 5:34 AM, Chris Wilson
>> wrote:
>> > The last major item on the wishlist is solving how to drive the SDVO i2c
>> > over gmbus. I think it is just a
On Thu, Apr 12, 2012 at 4:26 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Thu, 12 Apr 2012 02:17:46 +0800, Daniel Kurtz djku...@chromium.org wrote:
On Wed, Apr 11, 2012 at 5:34 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
The last major item on the wishlist is solving how to drive
On Wed, Apr 11, 2012 at 5:34 AM, Chris Wilson
wrote:
> On Tue, 10 Apr 2012 17:03:04 +0200, Daniel Vetter wrote:
>> On Tue, Apr 10, 2012 at 06:56:15PM +0800, Daniel Kurtz wrote:
>> > On Tue, Apr 10, 2012 at 6:41 PM, Daniel Vetter wrote:
>> > > On Tue, Apr 10, 2012 at 12:37:46PM +0200, Daniel
On Tue, Apr 10, 2012 at 11:03 PM, Daniel Vetter wrote:
> On Tue, Apr 10, 2012 at 06:56:15PM +0800, Daniel Kurtz wrote:
>> On Tue, Apr 10, 2012 at 6:41 PM, Daniel Vetter wrote:
>> > On Tue, Apr 10, 2012 at 12:37:46PM +0200, Daniel Vetter wrote:
>> >> On Fri, Mar 30, 2012 at 07:46:39PM +0800,
On Thu, Apr 12, 2012 at 02:16:45AM +0800, Daniel Kurtz wrote:
> On Tue, Apr 10, 2012 at 11:03 PM, Daniel Vetter wrote:
> > - atm the debug output is too noisy. I think we can leave the fallback to
> > ?gpio bitbanging at info (or maybe error) level, but all the other
> > ?messages should be tuned
On Thu, 12 Apr 2012 02:16:45 +0800, Daniel Kurtz
wrote:
> On Tue, Apr 10, 2012 at 11:03 PM, Daniel Vetter wrote:
> > - Chris Wilson suggested on irc that we should wait for HW_READY even for
> > ??zero-length writes (and also reads), currently we don't.
>
> I don't think so. We just need to
On Thu, 12 Apr 2012 02:17:46 +0800, Daniel Kurtz
wrote:
> On Wed, Apr 11, 2012 at 5:34 AM, Chris Wilson
> wrote:
> > The last major item on the wishlist is solving how to drive the SDVO i2c
> > over gmbus. I think it is just a matter of massaging in the channel
> > switch as msg[0].
>
> I
On Tue, Apr 10, 2012 at 11:03 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Apr 10, 2012 at 06:56:15PM +0800, Daniel Kurtz wrote:
On Tue, Apr 10, 2012 at 6:41 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Apr 10, 2012 at 12:37:46PM +0200, Daniel Vetter wrote:
On Fri, Mar 30, 2012 at
On Wed, Apr 11, 2012 at 5:34 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Tue, 10 Apr 2012 17:03:04 +0200, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Apr 10, 2012 at 06:56:15PM +0800, Daniel Kurtz wrote:
On Tue, Apr 10, 2012 at 6:41 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue,
On Thu, Apr 12, 2012 at 02:16:45AM +0800, Daniel Kurtz wrote:
On Tue, Apr 10, 2012 at 11:03 PM, Daniel Vetter dan...@ffwll.ch wrote:
- atm the debug output is too noisy. I think we can leave the fallback to
gpio bitbanging at info (or maybe error) level, but all the other
messages should
On Thu, 12 Apr 2012 02:17:46 +0800, Daniel Kurtz djku...@chromium.org wrote:
On Wed, Apr 11, 2012 at 5:34 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
The last major item on the wishlist is solving how to drive the SDVO i2c
over gmbus. I think it is just a matter of massaging in the
On Tue, 10 Apr 2012 17:03:04 +0200, Daniel Vetter wrote:
> On Tue, Apr 10, 2012 at 06:56:15PM +0800, Daniel Kurtz wrote:
> > On Tue, Apr 10, 2012 at 6:41 PM, Daniel Vetter wrote:
> > > On Tue, Apr 10, 2012 at 12:37:46PM +0200, Daniel Vetter wrote:
> > >> On Fri, Mar 30, 2012 at 07:46:39PM +0800,
On Tue, Apr 10, 2012 at 6:41 PM, Daniel Vetter wrote:
> On Tue, Apr 10, 2012 at 12:37:46PM +0200, Daniel Vetter wrote:
>> On Fri, Mar 30, 2012 at 07:46:39PM +0800, Daniel Kurtz wrote:
>> > The i915 is only able to generate a STOP cycle (i.e. finalize an i2c
>> > transaction) during a DATA or WAIT
On Tue, Apr 10, 2012 at 06:56:15PM +0800, Daniel Kurtz wrote:
> On Tue, Apr 10, 2012 at 6:41 PM, Daniel Vetter wrote:
> > On Tue, Apr 10, 2012 at 12:37:46PM +0200, Daniel Vetter wrote:
> >> On Fri, Mar 30, 2012 at 07:46:39PM +0800, Daniel Kurtz wrote:
> >> > The i915 is only able to generate a
On Tue, Apr 10, 2012 at 12:37:46PM +0200, Daniel Vetter wrote:
> On Fri, Mar 30, 2012 at 07:46:39PM +0800, Daniel Kurtz wrote:
> > The i915 is only able to generate a STOP cycle (i.e. finalize an i2c
> > transaction) during a DATA or WAIT phase. In other words, the
> > controller rejects a STOP
On Fri, Mar 30, 2012 at 07:46:39PM +0800, Daniel Kurtz wrote:
> The i915 is only able to generate a STOP cycle (i.e. finalize an i2c
> transaction) during a DATA or WAIT phase. In other words, the
> controller rejects a STOP requested as part of the first transaction in a
> sequence.
>
> Thus,
On Fri, Mar 30, 2012 at 07:46:39PM +0800, Daniel Kurtz wrote:
The i915 is only able to generate a STOP cycle (i.e. finalize an i2c
transaction) during a DATA or WAIT phase. In other words, the
controller rejects a STOP requested as part of the first transaction in a
sequence.
Thus, for the
On Tue, Apr 10, 2012 at 12:37:46PM +0200, Daniel Vetter wrote:
On Fri, Mar 30, 2012 at 07:46:39PM +0800, Daniel Kurtz wrote:
The i915 is only able to generate a STOP cycle (i.e. finalize an i2c
transaction) during a DATA or WAIT phase. In other words, the
controller rejects a STOP
On Tue, Apr 10, 2012 at 6:41 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Apr 10, 2012 at 12:37:46PM +0200, Daniel Vetter wrote:
On Fri, Mar 30, 2012 at 07:46:39PM +0800, Daniel Kurtz wrote:
The i915 is only able to generate a STOP cycle (i.e. finalize an i2c
transaction) during a DATA
On Tue, Apr 10, 2012 at 06:56:15PM +0800, Daniel Kurtz wrote:
On Tue, Apr 10, 2012 at 6:41 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Apr 10, 2012 at 12:37:46PM +0200, Daniel Vetter wrote:
On Fri, Mar 30, 2012 at 07:46:39PM +0800, Daniel Kurtz wrote:
The i915 is only able to generate
On Tue, 10 Apr 2012 17:03:04 +0200, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Apr 10, 2012 at 06:56:15PM +0800, Daniel Kurtz wrote:
On Tue, Apr 10, 2012 at 6:41 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Apr 10, 2012 at 12:37:46PM +0200, Daniel Vetter wrote:
On Fri, Mar 30, 2012
The i915 is only able to generate a STOP cycle (i.e. finalize an i2c
transaction) during a DATA or WAIT phase. In other words, the
controller rejects a STOP requested as part of the first transaction in a
sequence.
Thus, for the first transaction we must always use a WAIT cycle, detect
when the
The i915 is only able to generate a STOP cycle (i.e. finalize an i2c
transaction) during a DATA or WAIT phase. In other words, the
controller rejects a STOP requested as part of the first transaction in a
sequence.
Thus, for the first transaction we must always use a WAIT cycle, detect
when the
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