On Fri, Feb 15, 2019 at 08:59:29PM +0100, Matthias Klose wrote:
> On 15.02.19 15:52, Ian Lance Taylor wrote:
> > This patch by Robin Dapp adds S/390 support to the internal/cpu
> > package. This partially addresses PR 89123. I bootstrapped it on
> > x86_64-pc-linux-gnu, which means little.
Hi!
This is something I've noticed in a s390 change I'll post soon (where it was
even completely unnecessary), but it applies to i386 backend too.
Seems we have lots of .bss global state, 66x 64-byte and 61x 128-byte long
static buffers. Instead of doing
static char buf[128];
...
Hi!
On the following testcase, we've regressed in bar since 8.x, in 8.x
store merging came up with mem = 64-bit constant, but starting with the
change to transform {0,1,2,3,4,5,6,7} char initializers into STRING_CSTs,
we don't do that anymore. The mem = STRING_CST expansion can do that,
but only
Hi!
Both the C and C++ standard guarantee that the argc argument to main is
non-negative, the following patch sets (or adjusts) the corresponding
SSA_NAME_RANGE_INFO. While main is just one, with IPA VRP it can also
propagate etc. I had to change one testcase because it started optimizing
it
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89373
Andrew Pinski changed:
What|Removed |Added
Status|UNCONFIRMED |RESOLVED
Component|c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89373
Bug ID: 89373
Summary: macro expansion not counting braces correctly
Product: gcc
Version: unknown
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component:
On Tue, 2019-02-12 at 15:12 +0100, Richard Biener wrote:
> On Mon, Feb 11, 2019 at 10:46 PM Giuliano Belinassi
> wrote:
> >
> > Hi,
> >
> > I was just wondering what API should I use to spawn threads and
> > control
> > its flow. Should I use OpenMP, pthreads, or something else?
> >
> > My
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On 2/11/19 6:03 PM, Marek Polacek wrote:
On Mon, Feb 11, 2019 at 01:43:36PM -0500, Jason Merrill wrote:
On 2/7/19 6:02 PM, Marek Polacek wrote:
Since r268321 we can call digest_init even in a template, when the compound
literal isn't instantiation-dependent.
Right. And since digest_init
On 2/14/19 4:20 PM, David Malcolm wrote:
On Thu, 2019-02-14 at 17:32 +0100, Jakub Jelinek wrote:
On Thu, Feb 14, 2019 at 11:26:15AM -0500, David Malcolm wrote:
There's an asymmetry in the warning; it's looking for a comparison
of a
LHS expression against an RHS constant 0, spelled as "0".
If
On 2/14/19 7:09 PM, will wray wrote:
Thanks Jason.
Adding this 'else if' condition afterwards seems to work:
else if (BRACE_ENCLOSED_INITIALIZER_P (CONSTRUCTOR_ELT
(stripped_init,0)->value))
{
if (complain & tf_error)
error ("too many braces around scalar
On 2/13/19 4:33 PM, Martin Sebor wrote:
Index: gcc/doc/extend.texi
===
--- gcc/doc/extend.texi (revision 268856)
+++ gcc/doc/extend.texi (working copy)
@@ -12890,6 +12890,22 @@ built-in in this case, because it has no opportuni
On 2/13/19 2:46 PM, Martin Sebor wrote:
The attached patch adds documentation for the __has_attribute (and
__has_cpp_attribute) and __has_include operators added in r215752.
Thanks!
I was a little unsure where to add this, whether the preprocessor
manual or the GCC manual, or both. It seems
On 2/6/19 11:15 AM, Martin Sebor wrote:
[snip]
But whatever. Attached is a change with the subsentences reversed.
This version of the patch is OK.
-Sandra
On 2/6/19 9:16 AM, Martin Sebor wrote:
The manual documents the -Wno-missing-attributes form of the option
as if it was enabled by default, even though it's enabled by -Wall
(I can't get this -Wno- convention straight in my head). I also
got private comments on the documentation of the option
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89123
Ian Lance Taylor changed:
What|Removed |Added
CC||doko at debian dot org
--- Comment
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89277
Ian Lance Taylor changed:
What|Removed |Added
Status|UNCONFIRMED |RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89171
--- Comment #1 from Ian Lance Taylor ---
I don't know what is happening here and I don't have access to a riscv64
machine to test on (there doesn't seem to be one in the compile farm). The
errors are incorrect in that these are not expected
Emulate MMX version of pshufb with SSE version by masking out the bit 3
of the shuffle control byte. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (ssse3_pshufbv8qi3): Changed to
define_insn_and_split. Also allow TARGET_MMX_WITH_SSE.
On Fri, Feb 15, 2019 at 9:50 AM Uros Bizjak wrote:
>
> On Fri, Feb 15, 2019 at 2:58 PM H.J. Lu wrote:
> >
> > On x86-64, since __m64 is returned and passed in XMM registers, we can
> > emulate MMX intrinsics with SSE instructions. To support it, we added
> >
> > #define TARGET_MMX_WITH_SSE
Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA
by default with TARGET_MMX_WITH_SSE.
For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit
mode since MMX intrinsics can be emulated wit SSE.
gcc/
PR target/89021
*
Emulate MMX umulv1siv1di3 with SSE2. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation
support.
(*sse2_umulv1siv1di3): Add SSE2 emulation.
---
gcc/config/i386/mmx.md | 26
Emulate MMX mmx_uavgv8qi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_uavgv8qi3): Also check TARGET_MMX
and TARGET_MMX_WITH_SSE.
(*mmx_uavgv8qi3): Add SSE emulation.
---
gcc/config/i386/mmx.md | 25
Emulate MMX ssse3_phwv4hi3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_phwv4hi3):
Changed to define_insn_and_split to support SSE emulation.
---
With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP
when MMX is disabled.
PR target/89021
* config/i386/mmx.md (mmx_): Renamed to ...
(mmx__1): This.
(mmx_): New expander.
---
gcc/config/i386/mmx.md | 29 -
1 file
Emulate MMX vec_dupv2si with SSE. Add the "Yw" constraint to allow
broadcast from integer register for AVX512BW with TARGET_AVX512VL.
Only SSE register source operand is allowed.
PR target/89021
* config/i386/constraints.md (Yw): New constraint.
* config/i386/mmx.md
From: Uros Bizjak
2019-02-14 Uroš Bizjak
PR target/89021
* config/i386/i386.md (*zero_extendsidi2): Add mmx_isa attribute.
* config/i386/sse.md (*vec_concatv2sf_sse4_1): Ditto.
(*vec_concatv2sf_sse): Ditto.
(*vec_concatv2si_sse4_1): Ditto.
PR target/89021
* config/i386/i386.c (ix86_expand_vector_init_duplicate): Set
mmx_ok to true if TARGET_MMX_WITH_SSE is true.
(ix86_expand_vector_init_one_nonzero): Likewise.
(ix86_expand_vector_init_one_var): Likewise.
This pach enables TM MMX intrinsics with SSE2 when MMX is disabled.
PR target/89021
* config/i386/i386.c (bdesc_tm): Enable MMX intrinsics with
SSE2.
---
gcc/config/i386/i386.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git
Emulate MMX maskmovq with SSE2 maskmovdqu for TARGET_MMX_WITH_SSE by
zero-extending source and mask operands to 128 bits. Handle unmapped
bits 64:127 at memory address by adjusting source and mask operands
together with memory address.
PR target/89021
* config/i386/xmmintrin.h:
Emulate MMX movntq with SSE2 movntidi. Only register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (sse_movntq): Add SSE2 emulation.
---
gcc/config/i386/mmx.md | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git
Emulate MMX abs2 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/sse.md (abs2): Add SSE emulation.
---
gcc/config/i386/sse.md | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/gcc/config/i386/sse.md
Emulate MMX mmx_psadbw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_psadbw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git
Emulate MMX ssse3_pmulhrswv4hi3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/sse.md (*ssse3_pmulhrswv4hi3): Add SSE emulation.
---
gcc/config/i386/sse.md | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff
PR target/89021
* config/i386/mmx.md (MMXMODE:mov): Also allow
TARGET_MMX_WITH_SSE.
(MMXMODE:*mov_internal): Likewise.
(MMXMODE:movmisalign): Likewise.
---
gcc/config/i386/mmx.md | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
There is no V4HI pmulhrsw in AVX512BW and V4HI/V8HI pmulhrsw don't require
AVX2. To support TARGET_MMX_WITH_SSE, replace nonimmediate_operand with
register_pmulhrswmem_operand in _pmulhrsw3.
PR target/89372
* config/i386/predicates.md (register_pmulhrswmem_operand): New.
Emulate MMX ssse3_pmaddubsw with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_pmaddubsw): Add SSE emulation.
---
gcc/config/i386/sse.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git
Emulate MMX ssse3_phdv2si3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_phdv2si3):
Changed to define_insn_and_split to support SSE emulation.
---
Emulate MMX ssse3_psign3 with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_psign3): Add SSE emulation.
---
gcc/config/i386/sse.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git
Emulate MMX version of palignrq with SSE version by concatenating 2
64-bit MMX operands into a single 128-bit SSE operand, followed by
SSE psrldq. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (ssse3_palignrdi): Changed to
Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb
from QImode to SImode. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pmovmskb): Changed to
define_insn_and_split to support SSE emulation.
---
Emulate MMX sse_cvtpi2ps with SSE2 cvtdq2ps, preserving upper 64 bits of
destination XMM register. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (sse_cvtpi2ps): Changed to
define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. Add
Emulate MMX mmx_pinsrw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pinsrw): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(*mmx_pinsrw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 33
Emulate MMX mmx_umulv4hi3_highpart with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_umulv4hi3_highpart): Also check
TARGET_MMX and TARGET_MMX_WITH_SSE.
(*mmx_umulv4hi3_highpart): Add SSE emulation.
---
Emulate MMX pshufw with SSE. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pshufw): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(mmx_pshufw_1): Add SSE emulation.
(*vec_dupv4hi): Changed to define_insn_and_split
Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE.
PR target/89021
* config/i386/sse.md (sse_cvtps2pi): Add SSE emulation.
(sse_cvttps2pi): Likewise.
---
gcc/config/i386/sse.md | 30 ++
1 file changed, 18 insertions(+), 12 deletions(-)
diff
Emulate MMX mmx_uavgv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_uavgv4hi3): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(*mmx_uavgv4hi3): Add SSE emulation.
---
gcc/config/i386/mmx.md | 26
Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_mulv4hi3): Also allow
TARGET_MMX_WITH_SSE.
(mulv4hi3): New.
(*mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. Add SSE
support.
---
Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow
TARGET_MMX_WITH_SSE.
(*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add
SSE support.
---
Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_v4hi3): Also check TARGET_MMX
and TARGET_MMX_WITH_SSE.
(mmx_v8qi3): Likewise.
(smaxmin:v4hi3): New.
Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pextrw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git
Emulate MMX mmx_eq/mmx_gt3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_eq3): Also allow
TARGET_MMX_WITH_SSE.
(*mmx_eq3): Also allow TARGET_MMX_WITH_SSE. Add SSE
support.
(mmx_gt3): Likewise.
---
Emulate MMX mmx_andnot3 with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/mmx.md (mmx_andnot3): Also allow
TARGET_MMX_WITH_SSE. Add SSE support.
---
gcc/config/i386/mmx.md | 18 +++---
1 file changed, 11 insertions(+), 7
Emulate MMX pmaddwd with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE.
(*mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. Add SSE support.
---
gcc/config/i386/mmx.md | 25
Emulate MMX 3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (any_logic:mmx_3): Also allow
TARGET_MMX_WITH_SSE.
(any_logic:3): New.
(any_logic:*mmx_3): Also allow TARGET_MMX_WITH_SSE.
Add SSE support.
Emulate MMX ashr3/3 with SSE. Only SSE register
source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_ashr3): Also allow
TARGET_MMX_WITH_SSE. Add SSE emulation.
(mmx_3): Likewise.
(ashr3): New.
(3): Likewise.
---
Emulate MMX packsswb/packssdw/packuswb with SSE packsswb/packssdw/packuswb
plus moving bits 64:95 to bits 32:63 in SSE register. Only SSE register
source operand is allowed.
2019-02-08 H.J. Lu
Uros Bizjak
PR target/89021
* config/i386/i386-protos.h
Emulate MMX plusminus/sat_plusminus with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (MMXMODEI8): Require TARGET_SSE2 for V1DI.
(plusminus:mmx_3): Check
TARGET_MMX_WITH_SSE.
(sat_plusminus:mmx_3): Likewise.
In 64-bit mode, SSE2 can be used to emulate MMX instructions without
3DNOW. We can use SSE2 to support MMX register modes.
PR target/89021
* config/i386/i386-c.c (ix86_target_macros_internal): Define
__MMX_WITH_SSE__ for TARGET_MMX_WITH_SSE.
* config/i386/i386.c
On x86-64, since __m64 is returned and passed in XMM registers, we can
emulate MMX intrinsics with SSE instructions. To support it, we added
#define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2)
;; Define instruction set of MMX instructions
(define_attr "mmx_isa"
Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX. For MMX punpckhXX,
move bits 64:127 to bits 0:63 in SSE register. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/i386-protos.h (ix86_split_mmx_punpck): New
prototype.
*
On Tue, Feb 05, 2019 at 01:47:57PM +0100, Martin Liška wrote:
>
> gcc/fortran/ChangeLog:
>
> 2019-01-24 Martin Liska
>
> * decl.c (gfc_match_gcc_builtin): Add support for filtering
> of builtin directive based on multilib ABI name.
>
> gcc/testsuite/ChangeLog:
>
> 2019-01-24
This patch by Cherry Zhang changes the Go compiler and runtime to use
__builtin_dwarf_cfa for getcallersp. Currently, the compiler lowers
runtime.getcallersp to __builtin_frame_address(1). In the C side of
the runtime, getcallersp is defined as __builtin_frame_address(0).
They don't match.
One of the tests in g++.dg/asan/asan_oob_test.cc uses unaligned memory
accesses and g++.dg/asan/function-argument-3.C assumes a specific kind of
calling conventions for vectors.
Tested on SPARC64/Linux, applied on the mainline.
2019-02-15 Eric Botcazou
*
This automatically passes -funwind-tables when ASAN is used on Linux, as done
for other architectures, and also adjusts the shadow offset in 64-bit mode.
Tested on SPARC64/Linux, applied on the mainline.
2019-02-15 Eric Botcazou
* config/sparc/linux.h (ASAN_CC1_SPEC): Define.
On 2/15/19 3:46 PM, Eric Botcazou wrote:
I'm ready to commit the patch once it's approved, and have been since
the day the problem was reported.
Maybe CCing whoever approved the previous patch would help?
I just pinged the patch a few minutes ago and CC'd Jason. Sorry
about any trouble this
> I'm ready to commit the patch once it's approved, and have been since
> the day the problem was reported.
Maybe CCing whoever approved the previous patch would help?
--
Eric Botcazou
Snapshot gcc-8-20190215 is now available on
ftp://gcc.gnu.org/pub/gcc/snapshots/8-20190215/
and on various mirrors, see http://gcc.gnu.org/mirrors.html for details.
This snapshot has been generated from the GCC 8 SVN branch
with the following options: svn://gcc.gnu.org/svn/gcc/branches/gcc-8
Ping: https://gcc.gnu.org/ml/gcc-patches/2019-02/msg00857.html
Jason, since you approved the original patch, can you please also
review this one? Due to the Ada test breakage there seems to be
some anxiety about getting the problem corrected soon.
Thanks
Martin
On 2/11/19 6:13 PM, Martin
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89371
Bug ID: 89371
Summary: missed vectorisation with "#pragma omp simd
collapse(2)"
Product: gcc
Version: 8.2.0
Status: UNCONFIRMED
Severity: normal
Hi,
The following (og8 branch) patch added support for
attaching/detaching from dereferenced struct members:
https://gcc.gnu.org/ml/gcc-patches/2019-01/msg01778.html
Unfortunately I made a mistake in the portion of that patch that
inserts new alloc and firstprivate_pointer nodes for the struct
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88512
--- Comment #10 from Jonathan Wakely ---
I've created bug 89370 to request showing the type as std::string.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88512
--- Comment #9 from Jonathan Wakely ---
It's easy for you to say that after looking at the reason it failed and knowing
what the code is trying to do (obviously "insert" modifies the string, so it
can't be const). But the compiler has to try
> > OK, revised patch attached. I have manually verified that it yields the
> > expected result for an array of long doubles on 64-bit SPARC.
> >
> >
> > 2019-02-12 Eric Botcazou
> >
> > * asan.c (asan_expand_mark_ifn): Take into account the alignment of
> > the object to pick the
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89350
Martin Sebor changed:
What|Removed |Added
Status|NEW |ASSIGNED
Assignee|unassigned
On 2/15/19 12:24 AM, Eric Botcazou wrote:
The attached patch removes the assumption introduced earlier today
in my fix for bug 87996 that the valid_constant_size_p argument is
a constant expression. I couldn't come up with a C/C++ test case
where this isn't true but apparently it can happen in
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89368
Ian Lance Taylor changed:
What|Removed |Added
Status|UNCONFIRMED |RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84916
David Malcolm changed:
What|Removed |Added
Target Milestone|9.0 |10.0
--- Comment #4 from David Malcolm
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=60920
Paolo Carlini changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80953
--- Comment #35 from Eric Botcazou ---
> Right: 64-bit Solaris/SPARC uses the full 64-bit address space:
>
> https://docs.oracle.com/cd/E37838_01/html/E66175/advanced-2.
> html#SSFDGadvanced-5
>
> The gap between the low and high parts cannot
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89368
--- Comment #1 from ian at gcc dot gnu.org ---
Author: ian
Date: Fri Feb 15 21:04:58 2019
New Revision: 268948
URL: https://gcc.gnu.org/viewcvs?rev=268948=gcc=rev
Log:
PR go/89368
compiler: write barrier check nil-check policy tweak
This patch to the Go frontend by Than McIntosh tweaks the recipe for
generating writeBarrier loads to insure that the dereference expr is
marked as not requiring a nil check. This should fix gcc PR 89368.
Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed
to mainline.
Ian
On 02/15/19 10:13, Jakub Jelinek wrote:
The first release candidate for GCC 8.3 is available from
https://gcc.gnu.org/pub/gcc/snapshots/8.3.0-RC-20190215/
ftp://gcc.gnu.org/pub/gcc/snapshots/8.3.0-RC-20190215/
and shortly its mirrors. It has been generated from SVN revision 268935.
I
> Hasn't GNAT sorted Ada elements in records (e.g. structures) by size
> since near its initial addition to GCC in the mid-90s? This results in the
> largest elements up front and minimizes the need for alignment gaps.
No, that's a serious misconception, since one of the features of GNAT is to be
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84536
Paolo Carlini changed:
What|Removed |Added
Priority|P4 |P3
Status|UNCONFIRMED
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89077
--- Comment #17 from Harald Anlauf ---
(In reply to Harald Anlauf from comment #16)
> Regarding the unwanted padding with \0, the following patch seems to
> solve the issue with transfer.
Regtested cleanly and submitted here:
The attached patch is the third in a series for the above PR.
This one fixes erroneous padding with garbage characters in some
declaration and initialization expressions.
The issue here was that expr->representation is set when either
Hollerith strings are used or a TRANSFER statement is
Replace "(MODE == V1DImode)" with "(MODE) == V1DImode".
* config/i386/i386.h (VALID_MMX_REG_MODE): Correct the misplaced
')'.
---
gcc/ChangeLog | 5 +
gcc/config/i386/i386.h | 2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89372
Bug ID: 89372
Summary: Incorrect PMULHRSW
Product: gcc
Version: 9.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88944
David Malcolm changed:
What|Removed |Added
Status|UNCONFIRMED |ASSIGNED
Last reconfirmed|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89367
Jakub Jelinek changed:
What|Removed |Added
CC||hubicka at gcc dot gnu.org,
On 15.02.19 15:52, Ian Lance Taylor wrote:
> This patch by Robin Dapp adds S/390 support to the internal/cpu
> package. This partially addresses PR 89123. I bootstrapped it on
> x86_64-pc-linux-gnu, which means little. Committed to mainline.
fails in the -m31 multilib variant with
libtool:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89370
Jonny Grant changed:
What|Removed |Added
CC||jg at jguk dot org
--- Comment #1 from
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88512
--- Comment #12 from Jonny Grant ---
(In reply to Jonathan Wakely from comment #9)
> It's easy for you to say that after looking at the reason it failed and
> knowing what the code is trying to do (obviously "insert" modifies the
> string, so it
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89371
Jakub Jelinek changed:
What|Removed |Added
Keywords||missed-optimization, openmp
On 15/02/2019 19:15, Jim Wilson wrote:
> On Thu, Feb 14, 2019 at 11:33 PM Paulo Matos wrote:
>> Are global variables not supposed to alias each other?
>> If I indeed do that, gcc still won't group loads and stores:
>> https://cx.rv8.io/g/rFjGLa
>
> I meant something like
> struct foo_t x, y;
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88512
--- Comment #11 from Jonathan Wakely ---
There's also Bug 53281
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89370
Bug ID: 89370
Summary: Output std::string in diagnostics instead of
std::__cxx11::basic_string<_CharT, _Traits, _Alloc>
Product: gcc
Version: 9.0
Status: UNCONFIRMED
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87525
Martin Jambor changed:
What|Removed |Added
CC||jamborm at gcc dot gnu.org
--- Comment
On Fri, Feb 15, 2019 at 7:20 PM H.J. Lu wrote:
> > I went through the code again, and looks OK in general, modulo
> > mmx_nonimmediate_operand issue and a couple of minor issues.
> >
> > Please substitute nonimmediate_operand predicate with
> > mmx_nonimmediate_operand in expanders and insn
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