[Bug fortran/111853] f951: Segmentation fault at gfc_expression_rank

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111853 kargl at gcc dot gnu.org changed: What|Removed |Added CC||kargl at gcc dot gnu.org

[PATCH] vect: Cost adjacent vector loads/stores together [PR111784]

Hi, As comments[1][2], this patch is to change the costing way on some adjacent vector loads/stores from costing one by one to costing them together with the total number once. It helps to fix the exposed regression PR111784 on aarch64, as aarch64 specific costing could make different decisions

[PATCH] RISC-V: Optimize consecutive permutation index pattern by vrgather.vi/vx

This patch optimize this following permutation with consecutive patterns index: typedef char vnx16i __attribute__ ((vector_size (16))); #define MASK_16 12, 13, 14, 15, 12, 13, 14, 15, 12, 13, 14, 15, 12, 13, 14, 15 vnx16i __attribute__ ((noinline, noclone)) test_1 (vnx16i x, vnx16i y) {

Re: [PATCH V2 14/14] RISC-V: P14: Adjust and add testcases

OK juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-10-17 19:35 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding Subject: [PATCH V2 14/14] RISC-V: P14: Adjust and add testcases This sub-patch adjust some testcases and add some bugfix testcases. PR

Re: [PATCH V2 13/14] RISC-V: P13: Reorganize functions used to modify RTL

OK juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-10-17 19:34 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding Subject: [PATCH V2 13/14] RISC-V: P13: Reorganize functions used to modify RTL This sub-patch reoriganize the functions that used to modify

Re: [PATCH V2 12/14] RISC-V: P12: Delete riscv-vsetvl.h

OK juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-10-17 19:34 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding Subject: [PATCH V2 12/14] RISC-V: P12: Delete riscv-vsetvl.h This sub-patch delete the unused header file riscv-vsetvl.h since we no need

Re: [PATCH V2 09/14] RISC-V: P9: Cleanup post optimize phase

LGTM. juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-10-17 19:34 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding Subject: [PATCH V2 09/14] RISC-V: P9: Cleanup post optimize phase This sub-patch deletes partial post optimize code(which implement in the

Re: [PATCH V2 08/14] RISC-V: P8: Unified insert and delete of vsetvl insn into Phase 4

LGTM. juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-10-17 19:34 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding Subject: [PATCH V2 08/14] RISC-V: P8: Unified insert and delete of vsetvl insn into Phase 4 This sub-patch move the modification of rtl

Re: [PATCH V2 07/14] RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class

LGTM. juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-10-17 19:34 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding Subject: [PATCH V2 07/14] RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class This patch adjust move the code phase 2 and 3

Re: [PATCH V2 06/14] RISC-V: P6: Add computing reaching definition data flow

Copy and paste the original comments: -/* Compute the local properties of each recorded expression. - - Local properties are those that are defined by the block, irrespective of - other blocks. - - An expression is transparent in a block if its operands are not modified - in the block. -

Re: [PATCH V2 06/14] RISC-V: P6: Add computing reaching definition data flow

compute_vsetvl_lcm_data -> compute_lcm_local_properties juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-10-17 19:34 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding Subject: [PATCH V2 06/14] RISC-V: P6: Add computing reaching definition data flow

Re: [PATCH V2 05/14] RISC-V: P5: combine phase 1 and 2

LGTM on algorithm of local analysis. juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-10-17 19:34 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding Subject: [PATCH V2 05/14] RISC-V: P5: combine phase 1 and 2 This sub-patch combine phase 1 and 2 to use the

Re: [PATCH V2 11/14] RISC-V: P11: Adjust vector_block_info to vsetvl_block_info class

+ const vsetvl_info _header_info () const + { +gcc_assert (!empty_p ()); +return infos.is_empty () ? m_info : infos[0]; + } Change it into get_entry_info (be consistent with mode-switching naming which also uses LCM). + const vsetvl_info _footer_info () const + { +gcc_assert

Re: [PATCH V2 04/14] RISC-V: P4: move method from pass_vsetvl to pre_vsetvl

LGMT this patch. juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-10-17 19:34 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding Subject: [PATCH V2 04/14] RISC-V: P4: move method from pass_vsetvl to pre_vsetvl This sub-patch remove the method about

Re: [PATCH V2 03/14] RISC-V: P3: Refactor vector_infos_manager

+ demand_system dem; + auto_vec vector_block_infos; + + /* data for avl reaching defintion. */ + sbitmap avl_regs; + sbitmap *avl_def_in; + sbitmap *avl_def_out; + sbitmap *reg_def_loc; + + /* data for vsetvl info reaching defintion. */ + vsetvl_info unknow_info; + auto_vec

[Bug c/111856] New: GCC: 14: internal compiler error: in as_a, at machmode.h:381

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111856 Bug ID: 111856 Summary: GCC: 14: internal compiler error: in as_a, at machmode.h:381 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug target/111720] RISC-V: Ugly codegen in RVV

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111720 --- Comment #14 from Li Pan --- Looks like option -fmerge-all-constants doesn't work for this case, as well as RISC-V. For RISC-V, the CLOBBER exists after tree gimple. void test (vuint8m1_t *out) { uint8_t arr[32] = {1, 2, 7, 1, 3, 4, 5,

[Bug c/100532] ICE: tree check: expected class ‘type’, have ‘exceptional’ (error_mark) in useless_type_conversion_p, at gimple-expr.c:259

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100532 Andrew Pinski changed: What|Removed |Added CC||141242068 at smail dot nju.edu.cn ---

[Bug c/111855] GCC: 14: internal compiler error: tree check: expected class 'type', have 'exceptional' (error_mark) in useless_type_conversion_p, at gimple-expr.cc:265

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111855 Andrew Pinski changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug c/111855] GCC: 14: internal compiler error: tree check: expected class 'type', have 'exceptional' (error_mark) in useless_type_conversion_p, at gimple-expr.cc:265

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111855 Andrew Pinski changed: What|Removed |Added Keywords||ice-checking --- Comment #1 from

[Bug c/111855] New: GCC: 14: internal compiler error: tree check: expected class 'type', have 'exceptional' (error_mark) in useless_type_conversion_p, at gimple-expr.cc:265

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111855 Bug ID: 111855 Summary: GCC: 14: internal compiler error: tree check: expected class 'type', have 'exceptional' (error_mark) in useless_type_conversion_p, at gimple-expr.cc:265

[Bug target/111828] rs6000: Parse inline asm string to figure out it requires HTM feature or not.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111828 Kewen Lin changed: What|Removed |Added Priority|P3 |P4 --- Comment #8 from Kewen Lin --- (In

[Bug c++/111854] new (align_val_t) should be ill-formed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111854 TC changed: What|Removed |Added CC||rs2740 at gmail dot com --- Comment #7 from TC

Re: [PATCH V2 00/14] Refactor and cleanup vsetvl pass

Hi Patrick, Thanks a lot for reporting these failes, very important. I'll locate the causes since my previous run was with these parameters: -march=gcv_zvfh_zfh + -cmodel=medany + spike did not encounter these fails. On 2023/10/18 4:25, Patrick O'Neill wrote: Hi Lehua! I ran the gcc

[r14-4629 Regression] FAIL: gcc.dg/vect/vect-simd-clone-18f.c scan-tree-dump-times vect "[\\n\\r] [^\\n]* = foo\\.simdclone" 2 on Linux/x86_64

On Linux/x86_64, 3179ad72f67f31824c444ef30ef171ad7495d274 is the first bad commit commit 3179ad72f67f31824c444ef30ef171ad7495d274 Author: Richard Biener rguent...@suse.de Date: Fri Oct 13 12:32:51 2023 +0200 OMP SIMD inbranch call vectorization for AVX512 style

[Bug modula2/111756] Re-building all-gcc after source changes fails to link

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111756 Gaius Mulley changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug modula2/111756] Re-building all-gcc after source changes fails to link

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111756 --- Comment #9 from CVS Commits --- The releases/gcc-13 branch has been updated by Gaius Mulley : https://gcc.gnu.org/g:bdf4b6f9f2847b7abba5392e271e30f55541935e commit r13-7960-gbdf4b6f9f2847b7abba5392e271e30f55541935e Author: Gaius Mulley

[Bug modula2/111756] Re-building all-gcc after source changes fails to link

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111756 --- Comment #8 from Gaius Mulley --- Created attachment 56135 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56135=edit Proposed fix for gcc-13 This is a patch for gcc-13 adding dependency checking within gcc/m2/Make-lang.in. This patch

Re: [PATCH] LoongArch: Use fcmp.caf.s instead of movgr2cf for zeroing a fcc

在 2023/10/17 下午10:24, WANG Xuerui 写道: On 10/17/23 22:06, Xi Ruoyao wrote: During the review of a LLVM change [1], on LA464 we found that zeroing "an" LLVM change (because the word LLVM is pronounced letter-by-letter) a fcc with fcmp.caf.s is much faster than a movgr2cf from $r0.

[Bug c++/105467] Dependency file produced by C++ modules causes Ninja errors

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105467 Ben Boeckel changed: What|Removed |Added CC||bugzilla.gcc at me dot benboeckel.

[PATCH v1] RISC-V: Remove the type size restriction of vectorizer

From: Pan Li The vectoriable_call has one restriction of the size of data type. Aka DF to DI is allowed but SF to DI isn't. You may see below message when try to vectorize function call like lrintf. void test_lrintf (long *out, float *in, unsigned count) { for (unsigned i = 0; i < count; i++)

Re: [PATCH] RISC-V: Enable more tests for dynamic LMUL and bug fix[PR111832]

Committed. juzhe.zh...@rivai.ai From: Juzhe-Zhong Date: 2023-10-17 15:30 To: gcc-patches CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong Subject: [PATCH] RISC-V: Enable more tests for dynamic LMUL and bug fix[PR111832] Last time, Robin has mentioned that dynamic LMUL will

[Bug target/111832] RISC-V: ICE on dynamic LMUL

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111832 JuzheZhong changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/111832] RISC-V: ICE on dynamic LMUL

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111832 --- Comment #1 from CVS Commits --- The master branch has been updated by Pan Li : https://gcc.gnu.org/g:cf7739d4a6ba0b88068877d14439436c22b57630 commit r14-4700-gcf7739d4a6ba0b88068877d14439436c22b57630 Author: Juzhe-Zhong Date: Tue Oct

[Bug middle-end/110986] [14 Regression] aarch64 has support for conditional not (and vectorized conditional not ) after r14-3110-g7fb65f10285

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110986 --- Comment #21 from Andrew Pinski --- Created attachment 56134 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56134=edit the scalar patterns This adds the scalar patterns which I had talked about before. I have not tested this patch yet

Re: [PATCH 0/3] Add Intel new cpu archs

On Mon, Oct 16, 2023 at 2:25 PM Haochen Jiang wrote: > > Hi all, > > The patches aim to add new cpu archs Clear Water Forest and > Panther Lake. Here comes the documentation: > > https://cdrdv2.intel.com/v1/dl/getContent/671368 > > Also in the patches, I refactored how we detect cpu according to

[Bug target/111828] rs6000: Parse inline asm string to figure out it requires HTM feature or not.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111828 --- Comment #7 from Peter Bergner --- (In reply to Peter Bergner from comment #6) > That said, I think nearly all (all?) HTM usage on Power uses our HTM > built-in functions. Maybe we could remove OPTION_MASK_HTM from the > power8/power9

[Bug target/111828] rs6000: Parse inline asm string to figure out it requires HTM feature or not.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111828 --- Comment #6 from Peter Bergner --- (In reply to Kewen Lin from comment #3) > The motivation of this request is to try our best to make power10 attributed > code inline more power8/power9 attribute code which likely includes some > inline asm

[Bug c++/111842] Unable to disable conversion warning in case of _Float16

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111842 --- Comment #14 from Andrew Pinski --- _Float16 was added in GCC 12 not as an extended floating point type but rather some target specific type which had its own rules and such. GCC 13 was the first release where _Float16 became a real C++23

[Bug c++/111842] Unable to disable conversion warning in case of _Float16

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111842 --- Comment #13 from n.deshmukh at samsung dot com --- (In reply to Jonathan Wakely from comment #12) > (In reply to n.deshm...@samsung.com from comment #5) > > The warning is valid but I wish to suppress it like the other > > conversion

[Bug target/111828] rs6000: Parse inline asm string to figure out it requires HTM feature or not.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111828 --- Comment #5 from Peter Bergner --- (In reply to Jan Wassenberg from comment #4) > I understand the slippery slope concern. But the empty asm string is a > special case, we and others use it (with +r output and memory clobber) to > prevent

[PATCH] libstdc++: testsuite: Enhance codecvt_unicode with tests for length()

We can test codecvt::length() with the same data that we test codecvt::in(). For each call of in() we add another call to length(). Some additional small cosmentic changes are applied. libstdc++-v3/ChangeLog: * testsuite/22_locale/codecvt/codecvt_unicode.h: Test length() ---

[PATCH 2/2] aarch64: Put LR save slot first in more cases

Now that the prologue and epilogue code iterates over saved registers in offset order, we can put the LR save slot first without compromising LDP/STP formation. This isn't worthwhile when shadow call stacks are enabled, since the first two registers are also push/pop candidates, and LR cannot be

[PATCH 1/2] aarch64: Use vecs to store register save order

aarch64_save/restore_callee_saves looped over registers in register number order. This in turn meant that we could only use LDP and STP for registers that were consecutive both number-wise and offset-wise (after unsaved registers are excluded). This patch instead builds lists of the registers

[Bug middle-end/88670] [meta-bug] generic vector extension issues

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88670 Bug 88670 depends on bug 110817, which changed state. Bug 110817 Summary: [14 Regression] wrong code with vector compares and vector lowering https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110817 What|Removed

[Bug tree-optimization/110817] [14 Regression] wrong code with vector compares and vector lowering

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110817 Andrew Pinski changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug tree-optimization/110817] [14 Regression] wrong code with vector compares and vector lowering

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110817 --- Comment #23 from CVS Commits --- The trunk branch has been updated by Andrew Pinski : https://gcc.gnu.org/g:5e4abf4233cd34212680cca700d6438445e6a16a commit r14-4695-g5e4abf4233cd34212680cca700d6438445e6a16a Author: Andrew Pinski Date:

[Bug c++/111854] new (align_val_t) should be ill-formed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111854 --- Comment #6 from Andrew Pinski --- You are mixing up 2 different things. First this is about if the operator new is valid and it is because there is a corresponding placement delete operator (this would be rejected at compile time). Second

[Bug c++/111854] new (align_val_t) should be ill-formed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111854 --- Comment #5 from Andrew Pinski --- Why? as there is: void operator delete(void*, std::size_t, std::align_val_t) noexcept __attribute__((__externally_visible__)); void operator delete[](void*, std::size_t, std::align_val_t) noexcept

[Bug c++/111854] new (align_val_t) should be ill-formed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111854 --- Comment #4 from Barry Revzin --- The standard says this should be ill-formed.

[Bug c++/111854] new (align_val_t) should be ill-formed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111854 Andrew Pinski changed: What|Removed |Added Resolution|--- |INVALID Status|UNCONFIRMED

[Bug c++/111854] new (align_val_t) should be ill-formed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111854 --- Comment #2 from Andrew Pinski --- The reason why is you are using the global operator new here rather than trying the one inside T.

[Bug c++/111854] new (align_val_t) should be ill-formed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111854 --- Comment #1 from Andrew Pinski --- I don't see any issues with this program at compile time (runtime it would be undefined though).

[Bug c++/111854] New: new align_val_t usual deallocation

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111854 Bug ID: 111854 Summary: new align_val_t usual deallocation Product: gcc Version: 13.1.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: c++

[Bug fortran/111853] New: f951: Segmentation fault at gfc_expression_rank

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111853 Bug ID: 111853 Summary: f951: Segmentation fault at gfc_expression_rank Product: gcc Version: 13.2.1 Status: UNCONFIRMED Severity: normal Priority: P3

[Bug c++/111840] =delete("can have a reason")?

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111840 Marek Polacek changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug c++/111840] =delete("can have a reason")?

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111840 --- Comment #3 from CVS Commits --- The trunk branch has been updated by Marek Polacek : https://gcc.gnu.org/g:1fbb7d75abbb050f790d8b43422602ee4b152608 commit r14-4694-g1fbb7d75abbb050f790d8b43422602ee4b152608 Author: Marek Polacek Date:

[Bug c++/55004] [meta-bug] constexpr issues

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55004 Bug 55004 depends on bug 111660, which changed state. Bug 111660 Summary: [14 Regression] Compilation of constexpr function returning enum takes exponential time with -std=c++2a since r14-4140-g6851e3423c2b5e

[Bug c++/111660] [14 Regression] Compilation of constexpr function returning enum takes exponential time with -std=c++2a since r14-4140-g6851e3423c2b5e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111660 Marek Polacek changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

Re: [PATCH] c++: accepts-invalid with =delete("") [PR111840]

On 10/17/23 17:38, Marek Polacek wrote: Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? OK. -- >8 -- r6-2367 added a DECL_INITIAL check to cp_parser_simple_declaration so that we don't emit multiple errors in g++.dg/parse/error57.C. But that means we don't diagnose int f1()

[Bug bootstrap/111852] New: [14 regression] r14-4339-geaa41a6dc127d8 breaks building with gcc 4.8.5

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111852 Bug ID: 111852 Summary: [14 regression] r14-4339-geaa41a6dc127d8 breaks building with gcc 4.8.5 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity:

[Bug c++/111660] [14 Regression] Compilation of constexpr function returning enum takes exponential time with -std=c++2a since r14-4140-g6851e3423c2b5e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111660 --- Comment #13 from CVS Commits --- The trunk branch has been updated by Marek Polacek : https://gcc.gnu.org/g:765c3b8f82d50961008c214ac2113f35e7532aa9 commit r14-4693-g765c3b8f82d50961008c214ac2113f35e7532aa9 Author: Marek Polacek Date:

[PATCH] c++: accepts-invalid with =delete("") [PR111840]

Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? -- >8 -- r6-2367 added a DECL_INITIAL check to cp_parser_simple_declaration so that we don't emit multiple errors in g++.dg/parse/error57.C. But that means we don't diagnose int f1() = delete("george_crumb"); anymore, because fn

[Bug other/110831] [14 regression] gcc.dg/stack-check-3.c ICEs after r14-2822-g499b8079a6419b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110831 seurer at gcc dot gnu.org changed: What|Removed |Added Resolution|--- |FIXED

[pushed] c++: mangling tweaks

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- Most of this is introducing the abi_check function to reduce the verbosity of most places that check -fabi-version. The start_mangling change is to avoid needing to zero-initialize additional members of the mangling globals, though I'm not

[Bug testsuite/111850] [14 regression] gcc.target/powerpc/fold-vec-extract-char.p7.c fails after r14-4664-g04c9cf5c786b94

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111850 Andrew Pinski changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

Re: [PATCH v3 1/2] c++: Initial support for P0847R7 (Deducing This) [PR102609]

On 9/25/23 21:56, waffl3x wrote: On the plus side, I took my time to figure out how to best to pass down information about whether a param is an xobj param. My initial impression on what you were suggesting was to push another node on the front of the list, but I stared at it for a few hours

Re: [PATCH 11/11] aarch64: Add new load/store pair fusion pass.

On Tue, Oct 17, 2023 at 1:52 PM Alex Coplan wrote: > > This adds a new aarch64-specific RTL-SSA pass dedicated to forming load > and store pairs (LDPs and STPs). > > As a motivating example for the kind of thing this improves, take the > following testcase: > > extern double c[20]; > > double

Re: [PATCH v3] c++: Fix compile-time-hog in cp_fold_immediate_r [PR111660]

On Tue, Oct 17, 2023 at 04:49:52PM -0400, Jason Merrill wrote: > On 10/16/23 20:39, Marek Polacek wrote: > > On Sat, Oct 14, 2023 at 01:13:22AM -0400, Jason Merrill wrote: > > > On 10/13/23 14:53, Marek Polacek wrote: > > > > On Thu, Oct 12, 2023 at 09:41:43PM -0400, Jason Merrill wrote: > > > > >

Re: [PATCH v3 1/2] c++: Initial support for P0847R7 (Deducing This) [PR102609]

On 9/25/23 21:56, waffl3x wrote: Also, just a quick update on my copyright assignment, I have sent an e-mail to the FSF and haven't gotten a response yet. From what I was reading, I am confident that it's my preferred option going forward though. Hopefully they get back to me soon. Any

[PATCH 11/11] aarch64: Add new load/store pair fusion pass.

This adds a new aarch64-specific RTL-SSA pass dedicated to forming load and store pairs (LDPs and STPs). As a motivating example for the kind of thing this improves, take the following testcase: extern double c[20]; double f(double x) { double y = x*x; y += c[16]; y += c[17]; y +=

[PATCH 10/11] aarch64: Generalise TFmode load/store pair patterns

This patch generalises the TFmode load/store pair patterns to TImode and TDmode. This brings them in line with the DXmode patterns, and uses the same technique with separate mode iterators (TX and TX2) to allow for distinct modes in each arm of the load/store pair. For example, in combination

Re: [PATCH v3] c++: Fix compile-time-hog in cp_fold_immediate_r [PR111660]

On 10/16/23 20:39, Marek Polacek wrote: On Sat, Oct 14, 2023 at 01:13:22AM -0400, Jason Merrill wrote: On 10/13/23 14:53, Marek Polacek wrote: On Thu, Oct 12, 2023 at 09:41:43PM -0400, Jason Merrill wrote: On 10/12/23 17:04, Marek Polacek wrote: Bootstrapped/regtested on x86_64-pc-linux-gnu,

[PATCH 09/11] aarch64, testsuite: Fix up pr71727.c

The test is trying to check that we don't use q-register stores with -mstrict-align, so actually check specifically for that. This is a prerequisite to avoid regressing: scan-assembler-not "add\tx0, x0, :" with the upcoming ldp fusion pass, as we change where the ldps are formed such that a

[PATCH 08/11] aarch64, testsuite: Tweak sve/pcs/args_9.c to allow stps

With the new ldp/stp pass enabled, there is a change in the codegen for this test as follows: add x8, sp, 16 ptrue p3.h, mul3 str p3, [x8] - str x8, [sp, 8] - str x9, [sp] + stp x9, x8, [sp] ptrue p3.d, vl8 ptrue

[PATCH 07/11] aarch64, testsuite: Prevent stp in lr_free_1.c

The test is looking for individual stores which are able to be merged into stp instructions. The test currently passes -fno-schedule-fusion -fno-peephole2, presumably to prevent these stores from being turned into stps, but this is no longer sufficient with the new ldp/stp fusion pass. As such,

[PATCH 06/11] haifa-sched: Allow for NOTE_INSN_DELETED at start of epilogue

haifa-sched.cc:remove_notes asserts that it lands on a real (non-note) insn after advancing past NOTE_INSN_EPILOGUE_BEG, but with the upcoming post-RA aarch64 load pair pass enabled, we can land on NOTE_INSN_DELETED. This patch adjusts remove_notes to remove these if they occur at the start of

[PATCH 05/11] rtl-ssa: Support for inserting new insns

The upcoming aarch64 load pair pass needs to form store pairs, and can re-order stores over loads when alias analysis determines this is safe. In the case that both mem defs have uses in the RTL-SSA IR, and both stores require re-ordering over their uses, we represent that as (tentative) deletion

[PATCH 04/11] rtl-ssa: Support inferring uses of mem in change_insns

Currently, rtl_ssa::change_insns requires all new uses and defs to be specified explicitly. This turns out to be rather inconvenient for forming load pairs in the new aarch64 load pair pass, as the pass has to determine which mem def the final load pair consumes, and then obtain or create a

[PATCH 03/11] rtl-ssa: Add entry point to allow re-parenting uses

This is needed by the upcoming aarch64 load pair pass, as it can re-order stores (when alias analysis determines this is safe) and thus change which mem def a given use consumes (in the RTL-SSA view, there is no alias disambiguation of memory). Bootstrapped/regtested as a series on

[PATCH 02/11] rtl-ssa: Add drop_memory_access helper

Add a helper routine to access-utils.h which removes the memory access from an access_array, if it has one. Bootstrapped/regtested as a series on aarch64-linux-gnu, OK for trunk? gcc/ChangeLog: * rtl-ssa/access-utils.h (drop_memory_access): New. --- gcc/rtl-ssa/access-utils.h | 11

[PATCH 01/11] rtl-ssa: Fix bug in function_info::add_insn_after

In the case that !insn->is_debug_insn () && next->is_debug_insn (), this function was missing an update of the prev pointer on the first nondebug insn following the sequence of debug insns starting at next. This can lead to corruption of the insn chain, in that we end up with:

[PATCH 00/11] aarch64: Add new load/store pair fusion pass

Hi, This patch series adds a new aarch64-specific RTL-SSA pass for forming load and store pairs (LDPs and STPS). See the cover letter on patch 11/11 for more details on the pass itself. Patch 1/11 fixes a latent bug in RTL-SSA. Patches 2-5 add features to RTL-SSA that are needed by the pass.

[Bug fortran/111851] f951: Segmentation fault at gfc_delete_symtree

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111851 anlauf at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |NEW Keywords|

Re: Complex numbers support: discussions summary

Sylvain, Is this on a branch in your github repository https://github.com/kalray/gcc somewhere ? That would make it easier to test it for me (and probably others). See for instance my mail here (d.d. Thu Oct 5 14:45:05 GMT 2023):

Re: [PATCH] c++: Add missing auto_diagnostic_groups to constexpr.cc

On 10/17/23 12:34, Marek Polacek wrote: On Tue, Oct 17, 2023 at 09:35:21PM +1100, Nathaniel Shead wrote: Marek pointed out in another patch of mine [1] that I was missing an auto_diagnostic_group to correctly associate informative notes with their errors in structured error outputs. This patch

Re: [PATCH V2 00/14] Refactor and cleanup vsetvl pass

Hi Lehua! I ran the gcc testsuite on qemu before/after applying your patches to 305034e3 rv32/64gcv [1]. Baseline    = Summary of gcc testsuite =     | # of unexpected case / # of unique unexpected case     |

[Bug fortran/111851] New: f951: Segmentation fault at gfc_delete_symtree

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111851 Bug ID: 111851 Summary: f951: Segmentation fault at gfc_delete_symtree Product: gcc Version: 13.2.1 Status: UNCONFIRMED Severity: normal Priority: P3

[COMMITTED] RISC-V/testsuite/pr111466.c: update test and expected output

Update the test to potentially generate two SEXT.W instructions: one for incoming function arg, other for function return. But after commit 8eb9cdd14218 ("expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted subreg") the test is not supposed to generate either of them so fix the expected

PING Re: [PATCH v2 RFA] diagnostic: add permerror variants with opt

Ping? On 10/3/23 17:09, Jason Merrill wrote: This revision changes from using DK_PEDWARN for permerror-with-option to using DK_PERMERROR. Tested x86_64-pc-linux-gnu. OK for trunk? -- 8< -- In the discussion of promoting some pedwarns to be errors by default, rather than move them all into

Re: [PATCH v2] RISC-V/testsuite/pr111466.c: update test and expected output

On 10/17/23 12:51, Vineet Gupta wrote: Update the test to potentially generate two SEXT.W instructions: one for incoming function arg, other for function return. But after commit 8eb9cdd14218 ("expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted subreg") the test is not supposed to

[Bug c/111808] [C23] constexpr with excess precision

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111808 --- Comment #7 from joseph at codesourcery dot com --- I think it's reasonable for such a portability issue to be detected only when building for i386, much like a portability issue from code that assumes long is 64-bit would only be detected

[Bug testsuite/111850] New: [14 regression]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111850 Bug ID: 111850 Summary: [14 regression] Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: testsuite Assignee:

[x86 PATCH] PR target/110511: Fix reg allocation for widening multiplications.

This patch contains clean-ups of the widening multiplication patterns in i386.md, and provides variants of the existing highpart multiplication peephole2 transformations (that tidy up register allocation after reload), and thereby fixes PR target/110511, which is a superfluous move instruction.

Re: PR111648: Fix wrong code-gen due to incorrect VEC_PERM_EXPR folding

On Tue, 17 Oct 2023 at 02:40, Richard Sandiford wrote: > > Prathamesh Kulkarni writes: > > On Wed, 11 Oct 2023 at 16:57, Prathamesh Kulkarni > > wrote: > >> > >> On Wed, 11 Oct 2023 at 16:42, Prathamesh Kulkarni > >> wrote: > >> > > >> > On Mon, 9 Oct 2023 at 17:05, Richard Sandiford > >> >

[PATCH v2] RISC-V/testsuite/pr111466.c: update test and expected output

Update the test to potentially generate two SEXT.W instructions: one for incoming function arg, other for function return. But after commit 8eb9cdd14218 ("expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted subreg") the test is not supposed to generate either of them so fix the expected

[Bug c++/111785] [modules] ICE when compiling fmt lib as module

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111785 Patrick Palka changed: What|Removed |Added See Also||https://gcc.gnu.org/bugzill

[Bug bootstrap/111812] [14 regression] Can't build with gcc 4.8.5

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111812 seurer at gcc dot gnu.org changed: What|Removed |Added Status|NEW |RESOLVED

[Bug c/111708] Calling external global function instead of local static function.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111708 --- Comment #9 from CVS Commits --- The master branch has been updated by Martin Uecker : https://gcc.gnu.org/g:1f186f64b8602d74769af4a6250255e51227f744 commit r14-4689-g1f186f64b8602d74769af4a6250255e51227f744 Author: Martin Uecker Date:

[PATCH] RISC-V/testsuite/pr111466.c: fix expected output to not detect SEXT.W

gcc/testsuite/ChangeLog: * gcc.target/riscv/pr111466.c: Change to scan-assembler-not to not detect sext.w. Signed-off-by: Vineet Gupta --- gcc/testsuite/gcc.target/riscv/pr111466.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

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