Hi!
finish_struct already made sure not to call build_bitint_type for
signed _BitInt(2) : 1;
or
signed _BitInt(2) : 0;
bitfields (but instead build a zero precision integral type,
we remove it later), this patch makes sure we do it also for
unsigned _BitInt(1) : 0;
because of the
Hi!
The following testcase ICEs, because group_case_labels_stmt optimizes
switch (a.0_7) [50.00%], case 0: [50.00%], case 2:
[50.00%]>
where L7 block starts with __builtin_unreachable (); to
switch (a.0_7) [50.00%]>
and single label GIMPLE_SWITCH is something the switch expansion refuses
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113255
--- Comment #17 from GCC Commits ---
The master branch has been updated by Richard Biener :
https://gcc.gnu.org/g:5b281946c4b51132caf5e5b64c730fef92dd6123
commit r14-8796-g5b281946c4b51132caf5e5b64c730fef92dd6123
Author: Richard Biener
Date:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113750
Tamar Christina changed:
What|Removed |Added
Assignee|gaius at gcc dot gnu.org |tnfchris at gcc dot
gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113760
--- Comment #3 from Andrew Pinski ---
>From JDK bug report:
> It looks like it only removed
> the warnings for empty declarations at namespace scope. I couldn't find
> anything for other cases, including empty class member declarations.
Yes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113760
Andrew Pinski changed:
What|Removed |Added
See Also||https://gcc.gnu.org/bugzill
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113760
Andrew Pinski changed:
What|Removed |Added
Last reconfirmed||2024-02-05
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113760
Bug ID: 113760
Summary: gcc rejects valid empty-declaration in pedantic mode
Product: gcc
Version: unknown
Status: UNCONFIRMED
Severity: normal
Priority: P3
For SPEC INT 2017, when using upstream GCC (whitout these patches), I get a
coredump when training the peak case, so no data yet. The cause of the core
dump still needs to be investigated.
Typo, SPEC INT 2017 -> SPEC FP 2017
Also There is a bad news, the score of specint 2017 (with these
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113583
--- Comment #11 from JuzheZhong ---
Hi, I think this RVV compiler codegen is that optimal codegen we want for RVV:
https://repo.hca.bsc.es/epic/z/P6QXCc
.LBB0_5:# %vector.body
sub a4, t0, a3
I think it just trigger a latent bug that we didn't encounter.
Hi, Robin. Would you mind give me preprocessed file to reproduce the issue ?
I suspect it triggers latent bug in VSETVL PASS.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2024-02-05 12:36
To: Juzhe-Zhong; gcc-patches
CC:
Yes, this test needs "--enable-checking=rtl" build.
On Mon, Feb 5, 2024 at 11:28 AM Jeff Law wrote:
>
>
> On 2/4/24 20:20, Monk Chiang wrote:
> > gcc/ChangeLog:
> >
> > PR target/113742
> > * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
> > recognizes UNSPEC_AUIPC
On 2/2/24 15:48, Greg McGary wrote:
On 2/1/24 10:24 PM, Jeff Law wrote:
On 2/1/24 18:24, Greg McGary wrote:
However, for a machine where (WORD_REGISTER_OPERATIONS &&
load_extend_op (inner_mode) == SIGN_EXTEND), the high part of a PSoM
is only known at runtime as 0s or 1s. That's the
On 2/4/24 20:26, Jeff Law wrote:
On 2/1/24 18:56, Juzhe-Zhong wrote:
This patch fixes the following:
vsetvli a5,a1,e32,m1,tu,ma
slli a4,a5,2
sub a1,a1,a5
vle32.v v2,0(a0)
add a0,a0,a4
vadd.vv v1,v2,v1
bne
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113757
Andrew Pinski changed:
What|Removed |Added
Keywords|needs-reduction |
--- Comment #6 from Andrew Pinski
Hi Mike,
on 2024/1/6 07:42, Michael Meissner wrote:
> This patch is a prelimianry patch to add the full 1,024 bit dense math
> register> (DMRs) for -mcpu=future. The MMA 512-bit accumulators map onto the
> top of the
> DMR register.
>
> This patch only adds the new 1,024 bit register support.
On 2/4/24 20:20, Monk Chiang wrote:
gcc/ChangeLog:
PR target/113742
* config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr113742.c: New test.
OK. Presumably
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113757
--- Comment #5 from Sam James ---
reduced but with return-type UB:
```
template struct __alloc_traits {
typedef typename _Alloc::value_type _reference;
};
struct LegionAllocator {
typedef int value_type;
};
struct vector {
long size()
On 2/1/24 18:56, Juzhe-Zhong wrote:
This patch fixes the following:
vsetvli a5,a1,e32,m1,tu,ma
sllia4,a5,2
sub a1,a1,a5
vle32.v v2,0(a0)
add a0,a0,a4
vadd.vv v1,v2,v1
bne a1,zero,.L3
vsetivli
gcc/ChangeLog:
PR target/113742
* config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr113742.c: New test.
---
gcc/config/riscv/riscv.cc | 2 +-
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112896
Li Pan changed:
What|Removed |Added
Status|UNCONFIRMED |RESOLVED
Resolution|---
pushed, thanks :)
On Fri, Feb 2, 2024 at 11:59 AM Monk Chiang wrote:
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
> * doc/invoke.texi (RISC-V Options): Add sifive-p450,
> sifive-p670.
>
> gcc/testsuite/ChangeLog:
>
> *
pushed, thanks :)
On Fri, Feb 2, 2024 at 11:59 AM Monk Chiang wrote:
>
> Add sifive p400 series scheduler module. For more information
> see https://www.sifive.com/cores/performance-p450-470.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Include sifive-p400.md.
> *
Xi Ruoyao 于2024年2月5日周一 02:01写道：
>
> We expanded (neg x) to (minus const0 x) for MSA FP vectors, this is
> wrong because -0.0 is not 0 - 0.0. This causes some Python tests to
> fail when Python is built with MSA enabled.
>
> Use the bnegi.df instructions to simply reverse the sign bit instead.
>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106531
Andrew Pinski changed:
What|Removed |Added
Assignee|pinskia at gcc dot gnu.org |unassigned at gcc dot
gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113750
Sam James changed:
What|Removed |Added
Summary|[14 Regression] ICE in vect |[14 Regression] ICE in vect
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113759
--- Comment #5 from Sam James ---
in future, I really need to rename variables too, as it's way easier to see
what's going on then
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113759
--- Comment #4 from Andrew Pinski ---
Reduced slightly further:
```
extern short t[];
int f(int c, int b) {
if (b < 0) __builtin_unreachable();
if (c <= 0) __builtin_unreachable();
int d;
for (; c >= 0; c--)
{
int a = b +
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113759
--- Comment #3 from Sam James ---
reduced:
```
typedef struct {
struct {
struct {
int erRvlcInfo;
short aRvlcScfFwd[];
} aac;
} overlay;
} CAacDecoderCommonData;
int calcRefValFwd_refNrgFwd,
This patch fixes PR target/113690, an ICE-on-valid regression on x86_64
that exhibits with a specific combination of command line options. The
cause is that x86's scalar-to-vector pass converts a chain of instructions
from TImode to V1TImode, but fails to appropriately update the attached
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113759
Jakub Jelinek changed:
What|Removed |Added
Summary|[14 regression] ICE when|[14 regression] ICE when
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113759
--- Comment #1 from Andrew Pinski ---
I suspect r14-8680-g2f14c0dbb78985 .
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113759
Andrew Pinski changed:
What|Removed |Added
CC||pinskia at gcc dot gnu.org
le-default-pie --enable-host-pie --enable-host-bind-now
--enable-default-ssp
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 14.0.1 20240204 (experimental)
2ada8bc53e1924b805d5a623d7ce79b20c2a9feb (Gentoo Hardened 14.0.1 p, commit
3ab6b70bf9ee185da7e092e1df20753cdc35d710)
```
I can reproduce with just g++ -c rvlcconceal.ii -O2.
Snapshot gcc-14-20240204 is now available on
https://gcc.gnu.org/pub/gcc/snapshots/14-20240204/
and on various mirrors, see https://gcc.gnu.org/mirrors.html for details.
This snapshot has been generated from the GCC 14 git branch
with the following options: git://gcc.gnu.org/git/gcc.git branch
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113757
Jakub Jelinek changed:
What|Removed |Added
Ever confirmed|0 |1
Last reconfirmed|
On Sat, Feb 3, 2024 at 6:19 AM Takayuki 'January June' Suwa
wrote:
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
> Add missing ":SI" to the match_operator.
> ---
> gcc/config/xtensa/xtensa.md | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
On Sun, Feb 4, 2024 at 2:20 AM Takayuki 'January June' Suwa
wrote:
>
> After LRA transition, HImode constants that don't fit into signed 12 bits
> are no longer subject to constant synthesis:
>
> /* example */
> void test(void) {
> short foo = 32767;
> __asm__ ("" ::
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113757
--- Comment #3 from Andrew Pinski ---
(In reply to Sam James from comment #1)
> I will try reduce it but my track record with C++ isn't good ;)
I am reducing it too.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113757
Andrew Pinski changed:
What|Removed |Added
Target Milestone|--- |14.0
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113758
Bug ID: 113758
Summary: d: Callee destructor call invalidates the live object,
not the temporary
Product: gcc
Version: 11.0
Status: UNCONFIRMED
Severity:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110987
anlauf at gcc dot gnu.org changed:
What|Removed |Added
CC||anlauf at gcc dot gnu.org,
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113757
--- Comment #2 from Sam James ---
needs -O2 -march=znver2 -fPIC (the znver2 is just an artefact of how I built it
though, didn't bother trying it without w/o preprocessed)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113757
--- Comment #1 from Sam James ---
I will try reduce it but my track record with C++ isn't good ;)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113757
Bug ID: 113757
Summary: [14 regression] ICE when building legion-23.03.0
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
This patch adjusts the costs so that we treat REG and SUBREG expressions
the same for costing.
This was motivated by bt_skip_func and bt_find_func in xz and results in
nearly a 5% improvement in the dynamic instruction count for input #2
and smaller, but definitely visible improvements pretty
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113755
--- Comment #2 from Andrew Pinski ---
I wonder if the wording changed between the time concepts was originally added
to GCC to the finalization of the C++20 standard; which would describe GCC's
behavior.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113755
Andrew Pinski changed:
What|Removed |Added
Ever confirmed|0 |1
Summary|Class without a
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113727
Andrew Pinski changed:
What|Removed |Added
Target Milestone|--- |14.0
Keywords|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113756
Andrew Pinski changed:
What|Removed |Added
Last reconfirmed||2024-02-04
Ever confirmed|0
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113756
Andrew Pinski changed:
What|Removed |Added
Target Milestone|--- |14.0
CC|
We expanded (neg x) to (minus const0 x) for MSA FP vectors, this is
wrong because -0.0 is not 0 - 0.0. This causes some Python tests to
fail when Python is built with MSA enabled.
Use the bnegi.df instructions to simply reverse the sign bit instead.
gcc/ChangeLog:
*
On Sun, 2024-02-04 at 11:19 +0800, chenglulu wrote:
>
> 在 2024/2/2 下午5:55, Xi Ruoyao 写道:
> > We call loongarch_symbol_insns with mode = MAX_MACHINE_MODE sometimes.
> > But in loongarch_symbol_insns:
> >
> > if (LSX_SUPPORTED_MODE_P (mode) || LASX_SUPPORTED_MODE_P (mode))
> > return
On Sun, 2024-02-04 at 11:20 +0800, chenglulu wrote:
>
> 在 2024/2/3 下午4:58, Xi Ruoyao 写道:
> > We expanded (neg x) to (minus const0 x) for LSX FP vectors, this is
> > wrong because -0.0 is not 0 - 0.0. This causes some Python tests to
> > fail when Python is built with LSX enabled.
> >
> > Use
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113750
--- Comment #4 from Iain Sandoe ---
Created attachment 57318
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=57318=edit
gimple for 179t.vect
now there's a mem at the start of bb3 with the label following
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113750
--- Comment #3 from Iain Sandoe ---
Created attachment 57317
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=57317=edit
gimple for 179t.ifcvt
the label seems OK here.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113756
Bug ID: 113756
Summary: Wrong code at -O2 on x86_64-linux-gnu since
r14-2780-g39f117d6c87
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Keywords: wrong-code
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113742
--- Comment #1 from Kito Cheng ---
Thanks, forward and assigned this to our (SiFive) engineer :)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113754
Andrew Pinski changed:
What|Removed |Added
Blocks||107430
Keywords|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113750
Gaius Mulley changed:
What|Removed |Added
CC||gaius at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113755
Bug ID: 113755
Summary: Class without a viable destructor wrongly accepted
Product: gcc
Version: 13.2.1
Status: UNCONFIRMED
Severity: normal
Priority: P3
After LRA transition, HImode constants that don't fit into signed 12 bits
are no longer subject to constant synthesis:
/* example */
void test(void) {
short foo = 32767;
__asm__ ("" :: "r"(foo));
}
;; before
.literal_position
.literal .LC0, 32767
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113754
Bug ID: 113754
Summary: GCC complains when using a type that depends on lambda
Product: gcc
Version: 13.2.1
Status: UNCONFIRMED
Severity: normal
Priority: P3
Pushed to r14-8784.
在 2024/2/2 上午9:42, Li Wei 写道:
This FAIL was introduced from r14-6908. The reason is that when merging
constant vector permutation implementations, the 128-bit matching situation
was not fully considered. In fact, the expansion of 128-bit vectors after
merging only supports
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