On Thu, Jan 20, 2022 at 10:38 AM Andre Simoes Dias Vieira <
andre.simoesdiasvie...@arm.com> wrote:
>
> On 20/01/2022 09:23, Christophe Lyon wrote:
>
>
>
> On Wed, Jan 19, 2022 at 8:03 PM Andre Vieira (lists) via Gcc-patches <
> gcc-patches@gcc.gnu.org> w
On Wed, Jan 19, 2022 at 8:03 PM Andre Vieira (lists) via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
>
> On 13/01/2022 14:56, Christophe Lyon via Gcc-patches wrote:
> > The vmvnq_n* intrinsics and have [u]int[16|32]_t arguments, so use
> > iterator instead of HI in mv
On Wed, Jan 19, 2022 at 7:25 PM Andre Vieira (lists) via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
>
> On 13/01/2022 14:56, Christophe Lyon via Gcc-patches wrote:
> > VPR_REG is the only register in its class, so it should be handled by
> > TARGET_CLASS_LIKELY_SPIL
On Wed, Jan 19, 2022 at 7:18 PM Andre Vieira (lists) via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> Hi Christophe,
>
> On 13/01/2022 14:56, Christophe Lyon via Gcc-patches wrote:
> > At some point during the development of this patch series, it appeared
> > that
Hi André,
On Fri, Jan 14, 2022 at 6:03 PM Andre Vieira (lists) via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> Hi Christophe,
>
> This patch relaxes the addressing modes for the mve full load and stores
> (by full loads and stores I mean non-widening or narrowing loads and
> stores resp).
stage1, so it should still be OK
if they are accepted as-is ?
Thanks,
Christophe
On Thu, Jan 13, 2022 at 3:58 PM Christophe Lyon via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
>
> This is v3 of this patch series, fixing issues I discovered before
> committing v2 (which ha
:
vldrh.16q3, [ip], #14
but the constraint check fails because ip is not a low reg.
This patch replaces LAST_LO_REGNUM by LAST_ARM_REGNUM in
mve_vector_mem_operand and avoids the ICE.
2022-01-13 Christophe Lyon
gcc/
* config/arm/arm.c (mve_vector_mem_operand): Fix handling of V
VPR_REG should be part of ALL_REGS, this patch fixes this omission.
2022-01-13 Christophe Lyon
gcc/
* config/arm/arm.h (REG_CLASS_CONTENTS): Add VPR_REG to ALL_REGS.
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 2416fb5ef64..ea9fb16b9b1 100644
--- a/gcc
This patch covers a few non-load/store builtins where we do not use
the iterator and thus we cannot use .
2022-01-13 Christophe Lyon
gcc/
PR target/100757
PR target/101325
* config/arm/arm-builtins.c (CX_UNARY_UNONE_QUALIFIERS): Use
predicate
This patch covers a few builtins where we do not use the
iterator and thus we cannot use .
For v2di instructions, we keep the HI mode for predicates.
2022-01-13 Christophe Lyon
gcc/
PR target/100757
PR target/101325
* config/arm/arm-builtins.c
This is mostly a mechanical change, only tested by the intrinsics
expansion tests.
2022-01-13 Christophe Lyon
gcc/
PR target/100757
PR target/101325
* config/arm/arm-builtins.c (BINOP_UNONE_NONE_NONE_QUALIFIERS):
Delete
word 1084227584
.word 1082130432 // 4.0f
.word 1082130432
.word 1082130432
.word 1082130432
2022-01-13 Christophe Lyon
PR target/100757
gcc/
* config/arm/arm-protos.h (arm_get_mask_mode): New prototype.
(arm_expand_vector
with the new DB constraint for a constant vector
of booleans.
2022-01-13 Christophe Lyon
Richard Sandiford
gcc/
PR target/100757
PR target/101325
* config/arm/arm-builtins.c (BINOP_PRED_UNONE_UNONE_QUALIFIERS)
(BINOP_PRED_NONE_NONE_QUALIFIERS
ded.
2022-01-13 Christophe Lyon
Richard Sandiford
gcc/
PR target/100757
PR target/101325
* config/aarch64/aarch64-modes.def (VNx16BI, VNx8BI, VNx4BI,
VNx2BI): Update definition.
* config/arm/arm-builtins.c (arm_init_simd_builtin_types
The vmvnq_n* intrinsics and have [u]int[16|32]_t arguments, so use
iterator instead of HI in mve_vmvnq_n_.
2022-01-13 Christophe Lyon
gcc/
* config/arm/mve.md (mve_vmvnq_n_): Use V_elem mode
for operand 1.
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
VPR_REG is the only register in its class, so it should be handled by
TARGET_CLASS_LIKELY_SPILLED_P, which is achieved by calling
default_class_likely_spilled_p. No test fails without this patch, but
it seems it should be implemented.
2022-01-13 Christophe Lyon
gcc/
* config
anyway, to give the register allocator
more freedom.
CLASS_MAX_NREGS and arm_hard_regno_nregs need adjustment to avoid a
regression in gcc.dg/stack-usage-1.c when compiled with -mthumb
-mfloat-abi=hard -march=armv8.1-m.main+mve.fp+fp.dp.
2022-01-13 Christophe Lyon
gcc
so that it
uses add_options_for_arm_v8_1m_mve_fp, like arm_neon_hw does. This
ensures arm_mve_hw passes even if the toolchain does not generate MVE
code by default.
2022-01-13 Christophe Lyon
gcc/testsuite/
PR target/101325
* gcc.target/arm/simd/pr101325.c: New
. In addition, since we should not
need these masks, the tests make sure they are not present.
2022-01-13 Christophe Lyon
gcc/testsuite/
PR target/100757
* gcc.target/arm/simd/pr100757-2.c: New.
* gcc.target/arm/simd/pr100757-3.c: New.
* gcc.target/arm/simd
This patch mainly adds Neon tests similar to existing MVE ones,
to make sure we do not break Neon when fixing MVE.
mve-vcmp-f32-2.c is similar to mve-vcmp-f32.c but uses a conditional
with 2.0f and 3.0f constants to help scan-assembler-times.
2022-01-13 Christophe Lyon
gcc/testsuite
e v2di builtins although existing tests still pass.
Christophe Lyon (15):
arm: Add new tests for comparison vectorization with Neon and MVE
arm: Add tests for PR target/100757
arm: Add tests for PR target/101325
arm: Add GENERAL_AND_VPR_REGS regclass
arm: Add support for V
On Mon, Dec 13, 2021 at 3:29 PM Kyrylo Tkachov via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> Hi all,
>
> This patch adds the +mops architecture extension flag from the 2021 Arm
> Architecture extensions, Armv8.8-a.
> The +mops extensions introduce instructions to accelerate the memcpy,
>
On Mon, Dec 13, 2021 at 3:31 PM Kyrylo Tkachov via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> Hi all,
>
> This second patch in the series adds an inline movmem expansion for
> TARGET_MOPS
> that emits the recommended sequence.
>
> A new param aarch64-mops-memmove-size-threshold is added to
Hi Jakub,
On Thu, Dec 9, 2021 at 4:00 PM Jakub Jelinek via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> On Wed, Dec 08, 2021 at 08:00:03AM +, Iain Sandoe wrote:
> > > On 7 Dec 2021, at 14:50, Jakub Jelinek via Gcc-patches <
> gcc-patches@gcc.gnu.org> wrote:
> > The attached patch should
On Thu, Dec 2, 2021 at 3:38 PM Vladimir Makarov via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
>
> On 2021-12-02 09:29, Jakub Jelinek wrote:
> > On Thu, Dec 02, 2021 at 09:23:20AM -0500, Vladimir Makarov wrote:
> >> On 2021-12-02 09:00, Jakub Jelinek wrote:
> >>> On Thu, Dec 02, 2021 at
On Tue, Nov 23, 2021 at 4:41 PM Jeff Law via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
>
>
> On 11/23/2021 8:26 AM, Christophe LYON via Gcc-patches wrote:
> > Hi!
> >
> > On 23/11/2021 01:26, Jeff Law via Gcc-patches wrote:
> >>
> >>
> &g
Hi!
On 23/11/2021 01:26, Jeff Law via Gcc-patches wrote:
On 11/22/2021 10:22 AM, Marek Polacek via Gcc-patches wrote:
Let's hide [[likely]] behind a macro, to suppress warnings if the
compiler doesn't support it.
Co-authored-by: Jonathan Wakely
Bootstrapped/regtested on
t;
>
>
> I think for AArch32 mapping it back to armv8-a sounds sufficient. Unless
> we have string or math routines in newlib that make use of any ACLE guards
> that are beyond armv8-a …
>
>
>
> Ramana
>
>
>
>
>
> *From: *Richard Earnshaw
> *Date: *Tuesday
Hi,
On Tue, Nov 9, 2021 at 12:36 PM Przemyslaw Wirkus via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> > > > -Original Message-
> > > > From: Przemyslaw Wirkus
> > > > Sent: 18 October 2021 10:37
> > > > To: gcc-patches@gcc.gnu.org
> > > > Cc: Richard Earnshaw ; Ramana
> > > >
On Wed, Nov 10, 2021 at 4:34 PM Kyrylo Tkachov via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> Hi Christophe
>
> > -Original Message-
> > From: Gcc-patches > bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Christophe
> > Lyon via Gcc-
On Wed, Nov 10, 2021 at 1:54 PM Tamar Christina via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> Hi All,
>
> My previous patch missed these tuning structures in arm.c as they
> are not where the rest of the structure are located.
>
> This applies the same default values to silence
), /* dup. */
+COSTS_N_INSNS (2) /* extract. */
But given these fields are not used, maybe a dummy value should be
used instead? (zero?)
2021-11-08 Christophe Lyon
gcc/
* config/arm/arm.c (cortexa9_extra_costs, cortexa8_extra_costs,
cortexa5_extra_costs
Hi Tamar,
On Fri, Oct 29, 2021 at 5:23 PM Richard Sandiford via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> Tamar Christina writes:
> > Hi All,
> >
> > Attached is a new version that fixes the previous SVE fallouts in a new
> way.
> >
> > Ok for master?
>
Looks like you forgot to try to
On 20/10/2021 12:16, Richard Biener via Gcc-patches wrote:
On Wed, 20 Oct 2021, Andre Vieira (lists) wrote:
On 27/09/2021 12:54, Richard Biener via Gcc-patches wrote:
On Mon, 27 Sep 2021, Jirui Wu wrote:
Hi all,
I now use the type based on the specification of the intrinsic
instead of
Hi,
On Tue, Oct 19, 2021 at 11:03 AM liuhongt via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> updated patch:
> 1. Add documents in doc/sourcebuild.texi (Effective-Target Keywords).
> 2. Reduce -novec.c testcases to contain only new failed parted which
> is caused by O2 vectorization.
>
On 15/10/2021 17:08, Richard Sandiford wrote:
Christophe Lyon via Gcc-patches writes:
This patch covers a few builtins where we do not use the
iterator and thus we cannot use .
For v2di instructions, we use the V8BI mode for predicates.
Why V8BI though, when VPRED uses HI?
Hmm.. I used
On 14/10/2021 14:21, Aldy Hernandez via Gcc-patches wrote:
In the path solver, when requesting the range of an SSA for which we
know nothing, we ask the ranger for the range incoming to the path.
We do this by asking for all the incoming ranges to the path entry
block and unioning them.
The
VPR_REG should be part of ALL_REGS, this patch fixes this omission.
2021-10-13 Christophe Lyon
gcc/
* config/arm/arm.h (REG_CLASS_CONTENTS): Add VPR_REG to ALL_REGS.
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index eae1b1cd0fb..fab39d05916 100644
--- a/gcc
This patch covers a few non-load/store builtins where we do not use
the iterator and thus we cannot use .
We need to update the expected code in cde-mve-full-assembly.c because
we now use mve_movv16qi instead of movhi to generate the vmsr
instruction.
2021-10-13 Christophe Lyon
gcc
This patch covers a few builtins where we do not use the
iterator and thus we cannot use .
For v2di instructions, we use the V8BI mode for predicates.
2021-10-13 Christophe Lyon
gcc/
PR target/100757
PR target/101325
* config/arm/arm-builtins.c
This is mostly a mechanical change, only tested by the intrinsics
expansion tests.
2021-10-13 Christophe Lyon
gcc/
PR target/100757
PR target/101325
* config/arm/arm-builtins.c (BINOP_UNONE_NONE_NONE_QUALIFIERS):
Delete
432
.word 1082130432
2021-10-13 Christophe Lyon
PR target/100757
gcc/
* config/arm/arm-protos.h (arm_get_mask_mode): New prototype.
(arm_expand_vector_compare): Update prototype.
* config/arm/arm.c (TARGET_VECTORIZE_GE
On Mon, Oct 11, 2021 at 4:10 PM Richard Sandiford via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> Christophe Lyon via Gcc-patches writes:
> > The vmvnq_n* intrinsics and have [u]int[16|32]_t arguments, so use
> > iterator instead of HI in mve_vmvnq_n_.
> >
>
representation: we keep HImode
for it.
The vector_compare expansion code is updated to use the right VxBI
mode instead of HI for the result.
New mov patterns are introduced to handle the new modes.
2021-10-13 Christophe Lyon
gcc/
PR target/100757
PR target/101325
arguments and return value to the appropriate vector
of booleans (VxBI).
We have to update test_vector_ops_duplicate, because it iterates using
an offset in bytes, where we would need to iterate in bits: we stop
iterating when we reach the end of the vector of booleans.
2021-10-13 Chris
The vmvnq_n* intrinsics and have [u]int[16|32]_t arguments, so use
iterator instead of HI in mve_vmvnq_n_.
2021-10-13 Christophe Lyon
gcc/
* config/arm/mve.md (mve_vmvnq_n_): Use V_elem mode
for operand 1.
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
VPR_REG is the only register in its class, so it should be handled by
TARGET_CLASS_LIKELY_SPILLED_P, which is achieved by calling
default_class_likely_spilled_p. No test fails without this patch, but
it seems it should be implemented.
2021-10-13 Christophe Lyon
gcc/
* config
anyway, to give the register allocator
more freedom.
2021-10-13 Christophe Lyon
gcc/
* config/arm/arm.h (reg_class): Add GENERAL_AND_VPR_REGS.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
so that it
uses add_options_for_arm_v8_1m_mve_fp, like arm_neon_hw does. This
ensures arm_mve_hw passes even if the toolchain does not generate MVE
code by default.
2021-10-13 Christophe Lyon
gcc/testsuite/
PR target/101325
* gcc.target/arm/simd/pr101325.c: New
. In addition, since we should not
need these masks, the tests make sure they are not present.
2021-10-13 Christophe Lyon
gcc/testsuite/
PR target/100757
* gcc.target/arm/simd/pr100757-2.c: New.
* gcc.target/arm/simd/pr100757-3.c: New.
* gcc.target/arm/simd
This patch mainly adds Neon tests similar to existing MVE ones,
to make sure we do not break Neon when fixing MVE.
mve-vcmp-f32-2.c is similar to mve-vcmp-f32.c but uses a conditional
with 2.0f and 3.0f constants to help scan-assembler-times.
2021-10-13 Christophe Lyon
gcc/testsuite
erands. In fact,
patches 11/12 update some STR/LDR qualifiers in a way that breaks
these v2di builtins although existing tests still pass.
Christophe Lyon (14):
arm: Add new tests for comparison vectorization with Neon and MVE
arm: Add tests for PR target/100757
arm: Add tests for PR target/
On 28/09/2021 15:32, Christophe LYON via Gcc-patches wrote:
On 28/09/2021 13:18, Kyrylo Tkachov wrote:
Hi Christophe,
-Original Message-
From: Gcc-patches On Behalf Of Christophe
LYON via Gcc-patches
Sent: 08 September 2021 08:49
To: Richard Earnshaw ; gcc-
patc...@gcc.gnu.org
On 28/09/2021 15:30, Christophe LYON via Gcc-patches wrote:
On 28/09/2021 13:14, Kyrylo Tkachov wrote:
-Original Message-
From: Gcc-patches On Behalf Of Christophe
Lyon via Gcc-patches
Sent: 07 September 2021 10:15
To: gcc-patches@gcc.gnu.org
Subject: [PATCH 03/13] arm: Add test
On 29/09/2021 12:20, Kyrylo Tkachov via Gcc-patches wrote:
Hi all,
Similar to my previous patch for setmem this one does the same for the cpymem
expansion.
We count the number of ops emitted and compare it against the alternative of
just calling
the library function when optimising for
On 28/09/2021 13:18, Kyrylo Tkachov wrote:
Hi Christophe,
-Original Message-
From: Gcc-patches On Behalf Of Christophe
LYON via Gcc-patches
Sent: 08 September 2021 08:49
To: Richard Earnshaw ; gcc-
patc...@gcc.gnu.org
Subject: Re: [PATCH 04/13] arm: Add GENERAL_AND_VPR_REGS regclass
On 28/09/2021 13:14, Kyrylo Tkachov wrote:
-Original Message-
From: Gcc-patches On Behalf Of Christophe
Lyon via Gcc-patches
Sent: 07 September 2021 10:15
To: gcc-patches@gcc.gnu.org
Subject: [PATCH 03/13] arm: Add test for PR target/101325
This test is derived from the one
On 28/09/2021 13:12, Kyrylo Tkachov wrote:
-Original Message-
From: Gcc-patches On Behalf Of Christophe
Lyon via Gcc-patches
Sent: 07 September 2021 10:15
To: gcc-patches@gcc.gnu.org
Subject: [PATCH 02/13] arm: Add tests for PR target/100757
These tests currently trigger an ICE
On 23/09/2021 13:15, Aldy Hernandez via Gcc-patches wrote:
My upcoming improvements to the forward jump threader make it thread
more aggressively. In investigating some "regressions", I noticed
that it has always allowed threading through empty latches and across
loop boundaries. As we have
Ping?
On 13/09/2021 10:33, Christophe LYON via Gcc-patches wrote:
ping?
On 07/09/2021 11:15, Christophe Lyon wrote:
This patch series addresses PR 100757 and 101325 by representing
vectors of predicates (MVE VPR.P0 register) as vectors of booleans
rather than using HImode.
As this implies
On Thu, Sep 16, 2021 at 11:21 AM Richard Earnshaw via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
>
>
> On 16/09/2021 10:12, Christophe LYON via Gcc-patches wrote:
> >
> > On 15/09/2021 18:43, Richard Earnshaw via Gcc-patches wrote:
> >>
> >>
>
On 15/09/2021 18:43, Richard Earnshaw via Gcc-patches wrote:
On 15/09/2021 17:13, Christophe Lyon via Gcc-patches wrote:
On Wed, Sep 15, 2021 at 2:49 PM Richard Earnshaw via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
On 15/09/2021 13:26, Christophe LYON via Gcc-patches wrote:
On Wed, Sep 15, 2021 at 5:39 PM Jason Merrill via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> On Wed, Sep 15, 2021 at 11:37 AM Jeff Law wrote:
>
> >
> >
> > On 9/15/2021 9:31 AM, Jason Merrill via Gcc-patches wrote:
> > > Most any compilation on ARM/AArch64 was warning because the default L1
On Wed, Sep 15, 2021 at 2:49 PM Richard Earnshaw via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
>
>
> On 15/09/2021 13:26, Christophe LYON via Gcc-patches wrote:
> >
> > On 15/09/2021 13:02, Richard Earnshaw wrote:
> >>
> >>
> >> On 2
On 15/09/2021 13:02, Richard Earnshaw wrote:
On 26/08/2021 16:53, Christophe Lyon via Gcc-patches wrote:
g++.dg/eh/arm-vfp-unwind.C uses an asm statement relying on
double-precision FPU support, but does not make sure it is actually
supported by the target.
Check (__ARM_FP & 8) to en
On Wed, Sep 15, 2021 at 12:25 PM Richard Earnshaw via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
>
>
> On 14/09/2021 08:56, Christophe LYON via Gcc-patches wrote:
> >
> > On 10/09/2021 15:16, Jason Merrill via Gcc-patches wrote:
> >> OK, time to finis
On 10/09/2021 15:16, Jason Merrill via Gcc-patches wrote:
OK, time to finish this up. The main change relative to the last patch I sent
to the list is dropping the -finterference-tune flag and making that behavior
the default. Any more comments?
The last missing piece of the C++17
On Mon, Sep 13, 2021 at 4:40 PM Jakub Jelinek wrote:
> On Mon, Sep 13, 2021 at 01:57:52PM +0200, Christophe Lyon wrote:
> > > --- gcc/testsuite/c-c++-common/gomp/atomic-29.c.jj 2021-09-10
> > > 11:47:17.093164041 +0200
> > > +++ gcc/testsuite/c-c++-comm
On Fri, Sep 10, 2021 at 8:47 PM Jakub Jelinek via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> Hi!
>
> This patch implements OpenMP 5.1 atomics (with clarifications from
> upcoming 5.2).
> The most important changes are that it is now possible to write (for C/C++,
> for Fortran it was possible
On Fri, Sep 10, 2021 at 6:32 PM Jeff Law via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
>
>
> On 9/10/2021 7:53 AM, Aldy Hernandez via Gcc-patches wrote:
> >
> >
> > On 9/10/21 3:16 PM, Michael Matz wrote:
> >> Hi,
> >>
> >> On Fri, 10 Sep 2021, Aldy Hernandez via Gcc-patches wrote:
> >>
> >>>
ping?
On 07/09/2021 11:15, Christophe Lyon wrote:
This patch series addresses PR 100757 and 101325 by representing
vectors of predicates (MVE VPR.P0 register) as vectors of booleans
rather than using HImode.
As this implies a lot of mostly mechanical changes, I have tried to
split the patches
ping?
On 08/09/2021 10:49, Christophe Lyon wrote:
When running the testsuite under Windows, we noticed failures in
testcase which attempt to match compiler error messages containing the
name of the executable.
For instance, gcc.dg/analyzer/signal-4a.c tries to match 'cc1:' which
obviously
ping?
On 06/09/2021 09:23, Christophe LYON wrote:
ping?
On 26/08/2021 17:53, Christophe Lyon wrote:
g++.dg/eh/arm-vfp-unwind.C uses an asm statement relying on
double-precision FPU support, but does not make sure it is actually
supported by the target.
Check (__ARM_FP & 8) to en
On 10/09/2021 00:49, Qing Zhao via Gcc-patches wrote:
Hi, FYI
I just committed the following patch to gcc upstream:
https://gcc.gnu.org/pipermail/gcc-cvs/2021-September/353195.html
Hi,
Several of the new tests fail on arm and aarch64 with -mabi=ilp32.
On arm:
removes the .exe suffix from various toolchain executables
to avoid this problem.
2021-09-08 Christophe Lyon
Torbjörn SVENSSON
gcc/testsuite/
* lib/prune.exp (prune_gcc_output): Remove .exe suffix from
toolchain executables names.
---
gcc/testsuite/lib
On 07/09/2021 15:35, Richard Earnshaw wrote:
On 07/09/2021 13:05, Christophe LYON wrote:
On 07/09/2021 11:42, Richard Earnshaw wrote:
On 07/09/2021 10:15, Christophe Lyon via Gcc-patches wrote:
At some point during the development of this patch series, it appeared
that in some cases
On 07/09/2021 11:42, Richard Earnshaw wrote:
On 07/09/2021 10:15, Christophe Lyon via Gcc-patches wrote:
At some point during the development of this patch series, it appeared
that in some cases the register allocator wants “VPR or general”
rather than “VPR or general or FP” (which
This patch covers a few non-load/store builtins where we do not use
the iterator and thus we cannot use .
We need to update the expected code in cde-mve-full-assembly.c because
we now use mve_movv16qi instead of movhi to generate the vmsr
instruction.
2021-09-02 Christophe Lyon
gcc
, this patch introduces problems with:
mve_vldrdq_gather_base_z_v2di
mve_vldrdq_gather_base_wb_z_v2di
mve_vldrdq_gather_base_nowb_z_v2di
mve_vstrdq_scatter_base_wb_p_v2di
2021-09-02 Christophe Lyon
gcc/
PR target/100757
PR target/101325
* config/arm/arm-builtins.c
This is mostly a mechanical change, only tested by the intrinsics
expansion tests.
2021-09-02 Christophe Lyon
gcc/
PR target/100757
PR target/101325
* config/arm/arm-builtins.c (BINOP_UNONE_NONE_NONE_QUALIFIERS):
Delete
From: Christophe Lyon
The problem in this PR is that we call VPSEL with a mask of vector
type instead of HImode. This happens because operand 3 in vcond_mask
is the pre-computed vector comparison and has vector type.
This patch fixes it by implementing TARGET_VECTORIZE_GET_MASK_MODE,
returning
representation: we keep HImode
for it.
The vector_compare expansion code is updated to use the right VxBI
mode instead of HI for the result.
New mov patterns are introduced to handle the new modes.
2021-09-01 Christophe Lyon
gcc/
PR target/100757
PR target/101325
arguments and return value to the appropriate vector
of booleans (VxBI).
We have to update test_vector_ops_duplicate, because it iterates using
an offset in bytes, where we would need to iterate in bits: we stop
iterating when we reach the end of the vector of booleans.
2021-09-01 Chris
The vmvnq_n* intrinsics and have [u]int[16|32]_t arguments, so use
iterator instead of HI in mve_vmvnq_n_.
2021-09-03 Christophe Lyon
gcc/
* config/arm/mve.md (mve_vmvnq_n_): Use V_elem mode
for operand 1.
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
VPR_REG is the only register in its class, so it should be handled by
TARGET_CLASS_LIKELY_SPILLED_P. No test fails without this patch, but
it seems it should be implemented.
2021-09-01 Christophe Lyon
gcc/
* config/arm/arm.c (arm_class_likely_spilled_p): Handle VPR_REG.
diff
This patch mainly adds Neon tests similar to existing MVE ones,
to make sure we do not break Neon when fixing MVE.
mve-vcmp-f32-2.c is similar to mve-vcmp-f32.c but uses a conditional
with 2.0f and 3.0f constants to help scan-assembler-times.
2021-09-01 Christophe Lyon
gcc/testsuite
. In addition, since we should not
need these masks, the tests make sure they are not present.
2021-09-01 Christophe Lyon
gcc/testsuite/
PR target/100757
* gcc.target/arm/simd/pr100757-2.c: New.
* gcc.target/arm/simd/pr100757-3.c: New.
* gcc.target/arm/simd
anyway, to give the register allocator
more freedom.
2021-09-01 Christophe Lyon
gcc/
* config/arm/arm.h (reg_class): Add GENERAL_AND_VPR_REGS.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise. Add VPR_REG to ALL_REGS.
diff --git a/gcc/config/arm
such code (and it will need a new
arm_v8_1m_mve_hw or similar effective-target).
2021-09-01 Christophe Lyon
gcc/testsuite/
PR target/101325
* gcc.target/arm/simd/pr101325.c: New.
diff --git a/gcc/testsuite/gcc.target/arm/simd/pr101325.c
b/gcc/testsuite/gcc.target/arm/simd
which I am not sure: vctp,
vpnot, load-gather and store-scatter with v2di operands. In fact,
patches 11/12 update some STR/LDR qualifiers in a way that breaks
these v2di builtins although existing tests still pass.
Christophe Lyon (13):
arm: Add new tests for comparison vectorization with Neon
ping?
On 26/08/2021 17:53, Christophe Lyon wrote:
g++.dg/eh/arm-vfp-unwind.C uses an asm statement relying on
double-precision FPU support, but does not make sure it is actually
supported by the target.
Check (__ARM_FP & 8) to ensure this.
2021-08-26 Christophe Lyon
gcc/tests
On Mon, Sep 6, 2021 at 7:21 AM Sandra Loosemore
wrote:
> On 9/5/21 7:29 PM, H.J. Lu wrote:
> > On Sun, Sep 5, 2021 at 11:02 AM Sandra Loosemore
> > wrote:
> >>
> >> On 9/5/21 7:31 AM, H.J. Lu wrote:
> >>> On Sat, Sep 4, 2021 at 7:31 PM Sandra Loosemore <
> san...@codesourcery.com> wrote:
>
On 03/09/2021 10:35, Prathamesh Kulkarni via Gcc-patches wrote:
On Thu, 2 Sept 2021 at 14:32, Christophe Lyon
wrote:
On Tue, Aug 24, 2021 at 10:17 AM Kyrylo Tkachov wrote:
-Original Message-
From: Prathamesh Kulkarni
Sent: 24 August 2021 09:01
To: Christophe Lyon
Cc: Kyrylo
Hi,
On Thu, Aug 19, 2021 at 7:29 PM Sandra Loosemore
wrote:
> On 7/27/21 5:07 AM, Tobias Burnus wrote:
> > Hi Sandra, hi Thomas, hi all,
> >
> > @Thomas K: Comments about the following - and of course to the
> > testsuite itself - are highly welcome.
> >
> > In my opinion, the testsuite LGTM
On Tue, Aug 24, 2021 at 10:17 AM Kyrylo Tkachov
wrote:
>
>
> > -Original Message-
> > From: Prathamesh Kulkarni
> > Sent: 24 August 2021 09:01
> > To: Christophe Lyon
> > Cc: Kyrylo Tkachov ; gcc Patches > patc...@gcc.gnu.org>
> &
On Mon, Aug 30, 2021 at 8:27 AM Jakub Jelinek via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> On Wed, Aug 25, 2021 at 12:14:09PM +0200, Marcel Vollweiler wrote:
> > Add support for device-modifiers for 'omp target device'.
> >
> > 'device_num' and 'ancestor' are now parsed on target device
On Wed, Sep 1, 2021 at 7:09 AM Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:
> On 30/08/2021 14:01, Sebastian Huber wrote:
> > Do not declare abort in "libgcc/unwind-arm-common.inc" since it is
> already
> > provided by "tsystem.h". It fixes the following build error:
> >
> > In
On 31/08/2021 18:33, Roger Sayle wrote:
My apologies for the inconvenience. My recent patch to preserve
SUBREG_PROMOTED_VAR_P on (extend:HI (subreg/s:QI (reg:SI))), and other
places in the middle-end, has broken the build on several targets.
The change to convert_modes inadvertently used the
On 29/08/2021 09:46, Roger Sayle wrote:
SUBREG_PROMOTED_VAR_P is a mechanism for tracking that a partial subreg
is correctly zero-extended or sign-extended in the parent register. For
example, the RTL (subreg/s/v:QI (reg/v:SI 23 [ x ]) 0) indicates that the
byte x is zero extended in reg:SI
Hi,
On Tue, Aug 17, 2021 at 10:43 AM Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:
> abort() is used in gcc_assert() and gcc_unreachable() which is used by
> target
> libraries such as libgcov.a. This patch changes the abort() definition
> under
> certain conditions. If
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