Re: [PATCH v2] Target-independent store forwarding avoidance.

On 6/11/24 7:52 AM, Philipp Tomsich wrote: On Tue, 11 Jun 2024 at 15:37, Jeff Law wrote: On 6/11/24 1:22 AM, Richard Biener wrote: Absolutely. But forwarding from a smaller store to a wider load is painful from a hardware standpoint and if we can avoid it from a codegen standpoint

Re: [PATCH v1] Test: Move target independent test cases to gcc.dg/torture

On 6/11/24 12:19 AM, pan2...@intel.com wrote: From: Pan Li The test cases of pr115387 are target independent, at least x86 and riscv are able to reproduce. Thus, move these cases to the gcc.dg/torture. The below test suites are passed. 1. The rv64gcv fully regression test. 2. The x86

Re: [PATCH v2] Target-independent store forwarding avoidance.

On 6/11/24 1:22 AM, Richard Biener wrote: Absolutely. But forwarding from a smaller store to a wider load is painful from a hardware standpoint and if we can avoid it from a codegen standpoint, we should. Note there's also the possibility to increase the distance between the store and

[committed] [RISC-V] Drop dead test

of the non-Zfa sequences in this space that we'd write new tests for those as well (execution tests in particular). So dropping this test. Jeffcommit 95161c6abfbd7ba9fab0b538ccc885f5980efbee Author: Jeff Law Date: Mon Jun 10 22:39:40 2024 -0600 [committed] [RISC-V] Drop dead round_32 test

[gcc r15-1172] [committed] [RISC-V] Drop dead round_32 test

https://gcc.gnu.org/g:95161c6abfbd7ba9fab0b538ccc885f5980efbee commit r15-1172-g95161c6abfbd7ba9fab0b538ccc885f5980efbee Author: Jeff Law Date: Mon Jun 10 22:39:40 2024 -0600 [committed] [RISC-V] Drop dead round_32 test This test is no longer useful. It doesn't test what

Re: [PATCH v3 0/3] RISC-V: Add basic Zaamo and Zalrsc support

On 6/10/24 3:46 PM, Patrick O'Neill wrote: The A extension has been split into two parts: Zaamo and Zalrsc. This patch adds basic support by making the A extension imply Zaamo and Zalrsc. Zaamo/Zalrsc spec: https://github.com/riscv/riscv-zaamo-zalrsc/tags Ratification:

Re: [PATCH v3 0/3] RISC-V: Add basic Zaamo and Zalrsc support

On 6/10/24 6:15 PM, Andrea Parri wrote: On Mon, Jun 10, 2024 at 02:46:54PM -0700, Patrick O'Neill wrote: The A extension has been split into two parts: Zaamo and Zalrsc. This patch adds basic support by making the A extension imply Zaamo and Zalrsc. Zaamo/Zalrsc spec:

Re: [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match

On 6/10/24 7:28 PM, Li, Pan2 wrote: Hi Sam, This testcases ICEs for me on x86-64 too (without your patch) with just -O2. Can you move it out of the riscv suite? (I suspect the other fails on x86-64 too). Sure thing, but do you have any suggestion about where should I put these 2 cases?

[to-be-committed] [RISC-V] Improve (1 << N) | C for rv64

Another improvement for generating Zbs instructions. In this case we're looking at stuff like (1 << N) | C where N varies and C is a single bit constant. In this pattern the (1 << N) happens in SImode, but is zero extended out to DImode before the bit manipulation. The fact that we're

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object

https://gcc.gnu.org/g:08a6582277f62c1b5873dfa4d385a2b2e8843d8f commit 08a6582277f62c1b5873dfa4d385a2b2e8843d8f Author: Raphael Zinsly Date: Mon Jun 10 14:16:16 2024 -0600 [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object bext is defined as (src >> n)

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Just the testsuite bits from:

https://gcc.gnu.org/g:1d97b9d17699ea5fdd0945b8ce8aecda79829ff4 commit 1d97b9d17699ea5fdd0945b8ce8aecda79829ff4 Author: Pan Li Date: Mon Jun 10 14:13:38 2024 -0600 Just the testsuite bits from: [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match When

[gcc r15-1168] [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object

https://gcc.gnu.org/g:9aaf29b9ba5ffe332220d002ddde85d96fd6657d commit r15-1168-g9aaf29b9ba5ffe332220d002ddde85d96fd6657d Author: Raphael Zinsly Date: Mon Jun 10 14:16:16 2024 -0600 [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object bext is defined as

Re: [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match

On 6/10/24 8:49 AM, pan2...@intel.com wrote: When enabled the PHI handing for COND_EXPR, we need to insert the gcall to replace the PHI node. Unfortunately, I made a mistake that insert the gcall to before the last stmt of the bb. See below gimple, the PHI is located at no.1 but we

[gcc r15-1167] [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match

https://gcc.gnu.org/g:d03ff3fd3e2da1352a404e3c53fe61314569345c commit r15-1167-gd03ff3fd3e2da1352a404e3c53fe61314569345c Author: Pan Li Date: Mon Jun 10 14:13:38 2024 -0600 [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match When enabled the PHI handing for

Re: [PATCH] Move array_bounds warnings into it's own pass.

On 6/10/24 1:24 PM, Andrew MacLeod wrote: The array bounds warning pass was originally attached to the VRP pass because it wanted to leverage the context sensitive ranges available there. With ranger, we can make it a pass of its own for very little cost. This patch does that. It removes

Re: [PATCH v2] Target-independent store forwarding avoidance.

On 6/10/24 12:27 PM, Philipp Tomsich wrote: This change is what I briefly hinted as "the complete solution" that we had on the drawing board when we briefly talked last November in Santa Clara. I haven't any recollection of that part of the discussion, but I was a bit frazzled as you

Re: [PATCH v2] Target-independent store forwarding avoidance.

On 6/10/24 1:55 AM, Manolis Tsamis wrote: There was an older submission of a load-pair specific pass but this is a complete reimplementation and indeed significantly more general. Apart from being target independant, it addresses a number of important restrictions and can handle multiple

Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

On 6/10/24 8:52 AM, Li, Pan2 wrote: Not sure if below float eq implement in sail-riscv is useful or not, but looks like some special handling for nan, as well as snan. https://github.com/riscv/sail-riscv/blob/master/c_emulator/SoftFloat-3e/source/f32_eq.c Yes, but it's symmetrical, which

Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

On 6/10/24 10:16 AM, Demin Han wrote: Hi， I‘m on vacation rencently. I will return in a few days and summit new patch with the test. No problem. Enjoy your vacation, this can certainly wait until you return. jeff

Re: [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match

On 6/10/24 8:49 AM, pan2...@intel.com wrote: From: Pan Li When enabled the PHI handing for COND_EXPR, we need to insert the gcall to replace the PHI node. Unfortunately, I made a mistake that insert the gcall to before the last stmt of the bb. See below gimple, the PHI is located at

Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

On 6/10/24 1:33 AM, Robin Dapp wrote: But isn't canonicalization of EQ/NE safe, even for IEEE NaN and +-0.0? target = (a == b) ? x : y target = (a != b) ? y : x Are equivalent, even for IEEE IIRC. Yes, that should be fine. My concern was not that we do a canonicalization but that we

[to-be-committed][RISC-V] Generate bclr more often for rv64

Another of Raphael's patches to improve our ability to safely generate a Zbs instruction, bclr in this instance. In this case we have something like ~(1 << N) & C where N is variable, but C is a constant. If C has 33 or more leading zeros, then no matter what bit we clear via bclr, the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object

https://gcc.gnu.org/g:c5c054c429ac5a4d1a665d6e5e4634973dffae5a commit c5c054c429ac5a4d1a665d6e5e4634973dffae5a Author: Raphael Zinsly Date: Mon Jun 10 07:03:00 2024 -0600 [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object bext is defined as (src >> n)

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] FreeBSD: Stop linking _p libs for -pg as of FreeBSD 14

https://gcc.gnu.org/g:7cf4c1e16755f7adab3bff983d980d6ae0b9a6f3 commit 7cf4c1e16755f7adab3bff983d980d6ae0b9a6f3 Author: Andreas Tobler Date: Sun Jun 9 23:18:04 2024 +0200 FreeBSD: Stop linking _p libs for -pg as of FreeBSD 14 As of FreeBSD version 14, FreeBSD no longer provides

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Fix false-positive uninitialized variable

https://gcc.gnu.org/g:e0a5507e6888f85e2ff53aff76c67293890bed85 commit e0a5507e6888f85e2ff53aff76c67293890bed85 Author: Jeff Law Date: Sun Jun 9 09:17:55 2024 -0600 [committed] [RISC-V] Fix false-positive uninitialized variable Andreas noted we were getting an uninit warning after

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates.

https://gcc.gnu.org/g:21b9c1625d9178475ebbb7d524923e421a93906d commit 21b9c1625d9178475ebbb7d524923e421a93906d Author: Roger Sayle Date: Sat Jun 8 19:47:08 2024 -0600 [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates. This patch tweaks RTL

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement .SAT_SUB for unsigned scalar int

https://gcc.gnu.org/g:d63ee880aa3931d37fe73570d3a41952daafd8ee commit d63ee880aa3931d37fe73570d3a41952daafd8ee Author: Pan Li Date: Wed Jun 5 16:42:05 2024 +0800 RISC-V: Implement .SAT_SUB for unsigned scalar int As the middle support of .SAT_SUB committed, implement the

[gcc r15-1164] [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object

https://gcc.gnu.org/g:3472c1b500cf9184766237bfd3d102aa8451b99f commit r15-1164-g3472c1b500cf9184766237bfd3d102aa8451b99f Author: Raphael Zinsly Date: Mon Jun 10 07:03:00 2024 -0600 [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object bext is defined as

[to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object

bext is defined as (src >> n) & 1. With that formulation, particularly the "&1" means the result is implicitly zero extended. So we can safely use it on SI objects for rv64 without the need to do any explicit extension. This patch adds the obvious pattern and a few testcases. I think one

[committed] [RISC-V] Fix false-positive uninitialized variable

is the obvious fix. Pushed to the trunk. Jeff commit 932c6f8dd8859afb13475c2de466bd1a159530da Author: Jeff Law Date: Sun Jun 9 09:17:55 2024 -0600 [committed] [RISC-V] Fix false-positive uninitialized variable Andreas noted we were getting an uninit warning after the recent constant

[gcc r15-1123] [committed] [RISC-V] Fix false-positive uninitialized variable

https://gcc.gnu.org/g:932c6f8dd8859afb13475c2de466bd1a159530da commit r15-1123-g932c6f8dd8859afb13475c2de466bd1a159530da Author: Jeff Law Date: Sun Jun 9 09:17:55 2024 -0600 [committed] [RISC-V] Fix false-positive uninitialized variable Andreas noted we were getting an uninit

Re: [to-be-committed] [RISC-V] Use Zbkb for general 64 bit constants when profitable

On 6/7/24 11:49 AM, Andreas Schwab wrote: In file included from ../../gcc/rtl.h:3973, from ../../gcc/config/riscv/riscv.cc:31: In function 'rtx_def* init_rtx_fmt_ee(rtx, machine_mode, rtx, rtx)', inlined from 'rtx_def* gen_rtx_fmt_ee_stat(rtx_code, machine_mode, rtx,

Re: [PATCH] ifcvt.cc: Prevent excessive if-conversion for conditional moves

On 6/9/24 5:28 AM, YunQiang Su wrote: YunQiang Su 于2024年6月9日周日 18:25写道： gcc/ChangeLog: * ifcvt.cc (cond_move_process_if_block): Consider the result of targetm.noce_conversion_profitable_p() when replacing the original sequence with the converted one. THanks. I

Re: [PING] [contrib] validate_failures.py: fix python 3.12 escape sequence warnings

On 6/9/24 5:45 AM, Gabi Falk wrote: Hi, On Sat, Jun 08, 2024 at 03:34:02PM -0600, Jeff Law wrote: On 5/14/24 8:12 AM, Gabi Falk wrote: Hi, This one still needs review: https://inbox.sourceware.org/gcc-patches/20240415233833.104460-1-gabif...@gmx.com/ I think I just ACK'd an equivalent

Re: [PATCH v2] Target-independent store forwarding avoidance.

On 6/7/24 4:31 PM, Jeff Law wrote: I've actually added it to my tester just to see if there's any fallout. It'll take a week to churn through the long running targets that bootstrap in QEMU, but the crosses should have data Monday. The first round naturally didn't trigger anything because

Re: [PATCH] [tree-prof] skip if errors were seen [PR113681]

On 4/15/24 10:03 PM, Alexandre Oliva wrote: On Mar 29, 2024, Alexandre Oliva wrote: On Mar 22, 2024, Jeff Law wrote: On 3/9/24 2:11 AM, Alexandre Oliva wrote: ipa_tree_profile asserts that the symtab is in IPA_SSA state, but we don't reach that state and ICE if e.g. ipa-strub passes

Re: [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates.

On 1/18/24 12:54 PM, Roger Sayle wrote: This patch tweaks RTL expansion of multi-word shifts and rotates to use PLUS rather than IOR for disjunctive operations. During expansion of these operations, the middle-end creates RTL like (X<>C2) where the constants C1 and C2 guarantee that bits

[gcc r15-1120] [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates.

https://gcc.gnu.org/g:2277f987979445f4390a5c6e092d79e04814d641 commit r15-1120-g2277f987979445f4390a5c6e092d79e04814d641 Author: Roger Sayle Date: Sat Jun 8 19:47:08 2024 -0600 [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates. This patch

Re: [RFC/RFA] [PATCH 08/12] Add a new pass for naive CRC loops detection

On 5/29/24 5:12 AM, Mariam Arutunian wrote: IIRC we looked at the problem of canonicalizing the loop into a form where we didn't necessarily have conditional blocks, instead we had branchless sequences for the conditional xor and dealing with the high bit in the crc.  My

Re: [RFC/RFA] [PATCH 01/12] Implement internal functions for efficient CRC computation

On 5/27/24 7:51 AM, Mariam Arutunian wrote: I carefully reviewed the indentation of the code using different editors and viewers, and everything appeared correct. I double-checked the specific sections mentioned, and they also looked right. In this reply message I see that it's not

Re: [RFC/RFA] [PATCH 08/12] Add a new pass for naive CRC loops detection

On 6/4/24 7:41 AM, Mariam Arutunian wrote: /Mariam, your thoughts on whether or not those two phases could handle a loop with two CRC calculations inside, essentially creating two calls to our new builtins? / / / It is feasible, but it would likely demand considerable effort and

Re: [PING] [contrib] validate_failures.py: fix python 3.12 escape sequence warnings

On 5/14/24 8:12 AM, Gabi Falk wrote: Hi, This one still needs review: https://inbox.sourceware.org/gcc-patches/20240415233833.104460-1-gabif...@gmx.com/ I think I just ACK'd an equivalent patch from someone else this week. jeff

Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

On 3/1/24 1:12 AM, Demin Han wrote: Hi juzhe, I also thought it’s related to commutive firstly. Following things make me to do the removal: 1.No tests fails in regression 2.When I write if (a == 2) and if (2 == a), the results are same GCC canonicalizes comparisons so that constants

Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

On 2/29/24 11:27 PM, demin.han wrote: We can unify eqne and other comparison operations. Tested on RV32 and RV64 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond * config/riscv/vector.md (@pred_eqne_scalar): Remove patterns

Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

On 5/16/24 1:21 PM, Robin Dapp wrote: Can eqne pattern removal patches be committed firstly? Please first make sure you test with corner cases, NaNs in particular. I'm pretty sure we don't have any test cases for those. But isn't canonicalization of EQ/NE safe, even for IEEE NaN and

Re: [PATCH 0/2] fix RISC-V zcmp popretz [PR113715]

On 6/5/24 8:42 PM, Fei Gao wrote: But let's back up and get a good explanation of what the problem is. Based on patch 2/2 it looks like we have lost an assignment to the return register. To someone not familiar with this code, it sounds to me like we've made a mistake earlier and we're now

Re: [PATCH] haifa-sched: Avoid the fusion priority of the fused insn to affect the subsequent insn sequence.

On 6/6/24 8:51 PM, Jin Ma wrote: I am very sorry that I did not check the commit information carefully. The statement is somewhat inaccurate. When the insn 1 and 2, 3 and 4 can be fusioned, then there is the following sequence: ;;    insn | ;;      1  | sp=sp-0x18 ;;  +   2  |

Re: How to target a processor with very primitive addressing modes?

On 6/8/24 10:45 AM, Paul Koning via Gcc wrote: On Jun 8, 2024, at 5:32 AM, Mikael Pettersson via Gcc wrote: On Thu, Jun 6, 2024 at 8:59 PM Dimitar Dimitrov wrote: Have you tried defining TARGET_LEGITIMIZE_ADDRESS for your target? From a quick search I see that the iq2000 and rx

Re: Reverted recent patches to resource.cc

On 5/29/24 8:07 PM, Jeff Law wrote: On 5/29/24 7:28 PM, Hans-Peter Nilsson wrote: From: Hans-Peter Nilsson Date: Mon, 27 May 2024 19:51:47 +0200 2: Does not depend on 1, but corrects an incidentally found wart: find_basic_block calls fails too often.  Replace it with "modern&

Re: How to target a processor with very primitive addressing modes?

On 6/8/24 3:32 AM, Mikael Pettersson via Gcc wrote: On Thu, Jun 6, 2024 at 8:59 PM Dimitar Dimitrov wrote: Have you tried defining TARGET_LEGITIMIZE_ADDRESS for your target? From a quick search I see that the iq2000 and rx backends are rewriting some PLUS expression addresses with insn

Re: [RFC/RFA] [PATCH 03/12] RISC-V: Add CRC expander to generate faster CRC.

On 6/8/24 1:53 AM, Richard Sandiford wrote: I realise there are many ways of writing this out there though, so that's just a suggestion. (And only lightly tested.) FWIW, we could easily extend the interface to work on wide_ints if we ever need it for N>63. I think there's constraints

Re: [PATCH v2 3/3] RISC-V: Add Zalrsc amo-op patterns

On 6/3/24 3:53 PM, Patrick O'Neill wrote: All amo patterns can be represented with lrsc sequences. Add these patterns as a fallback when Zaamo is not enabled. gcc/ChangeLog: * config/riscv/sync.md (atomic_): New expand pattern. (amo_atomic_): Rename amo pattern.

Re: [PATCH v2 2/3] RISC-V: Add Zalrsc and Zaamo testsuite support

On 6/3/24 3:53 PM, Patrick O'Neill wrote: Convert testsuite infrastructure to use Zalrsc and Zaamo rather than A. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-a-6-amo-add-1.c: Use Zaamo rather than A. * gcc.target/riscv/amo-table-a-6-amo-add-2.c: Ditto. *

Re: [PATCH v2 1/3] RISC-V: Add basic Zaamo and Zalrsc support

On 6/3/24 3:53 PM, Patrick O'Neill wrote: The A extension has been split into two parts: Zaamo and Zalrsc. This patch adds basic support by making the A extension imply Zaamo and Zalrsc. Zaamo/Zalrsc spec: https://github.com/riscv/riscv-zaamo-zalrsc/tags Ratification:

Re: [PATCH v2] Target-independent store forwarding avoidance.

On 6/6/24 4:10 AM, Manolis Tsamis wrote: This pass detects cases of expensive store forwarding and tries to avoid them by reordering the stores and using suitable bit insertion sequences. For example it can transform this: strbw2, [x1, 1] ldr x0, [x1] # Expensive

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 3

https://gcc.gnu.org/g:4b3c0b3380d38553e76bbf01e1ac5b3f66dc3d5c commit 4b3c0b3380d38553e76bbf01e1ac5b3f66dc3d5c Author: Pan Li Date: Mon Jun 3 10:24:47 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 3 After the middle-end support the form 3 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 1

https://gcc.gnu.org/g:efe00579c04e02b6132c678962ce8050c8759bee commit efe00579c04e02b6132c678962ce8050c8759bee Author: Pan Li Date: Wed May 29 14:15:45 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 1 After the middle-end support the form 1 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Regenerate opt urls.

https://gcc.gnu.org/g:4f20feccf708ff7a7af5d776ca87d4995ef46f76 commit 4f20feccf708ff7a7af5d776ca87d4995ef46f76 Author: Robin Dapp Date: Thu Jun 6 09:32:28 2024 +0200 RISC-V: Regenerate opt urls. I wasn't aware that I needed to regenerate the opt urls when adding an option.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 5

https://gcc.gnu.org/g:1a6d2ed7fbd20bfa3079da4700eb591f2abaa395 commit 1a6d2ed7fbd20bfa3079da4700eb591f2abaa395 Author: Pan Li Date: Mon Jun 3 10:43:10 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 5 After the middle-end support the form 5 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 2

https://gcc.gnu.org/g:6f5119eed91a2ec0708e38c9f2e5d58169a3f53e commit 6f5119eed91a2ec0708e38c9f2e5d58169a3f53e Author: Pan Li Date: Mon Jun 3 09:35:49 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 2 After the middle-end support the form 2 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 4

https://gcc.gnu.org/g:b93df02d58c0c448c4b524c07bdf5f3d7c305378 commit b93df02d58c0c448c4b524c07bdf5f3d7c305378 Author: Pan Li Date: Mon Jun 3 10:33:15 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 4 After the middle-end support the form 4 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Simplify (AND (ASHIFTRT A imm) mask) to (LSHIFTRT A imm) for vector mode.

https://gcc.gnu.org/g:e46fc82745c1a917ade318222d514c881c68ce1a commit e46fc82745c1a917ade318222d514c881c68ce1a Author: liuhongt Date: Fri Apr 19 10:29:34 2024 +0800 Simplify (AND (ASHIFTRT A imm) mask) to (LSHIFTRT A imm) for vector mode. When mask is (1 << (prec - imm) - 1)

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Introduce -mvector-strict-align.

https://gcc.gnu.org/g:0e0b666a30f53364292432903b68febd85a3e114 commit 0e0b666a30f53364292432903b68febd85a3e114 Author: Robin Dapp Date: Tue May 28 21:19:26 2024 +0200 RISC-V: Introduce -mvector-strict-align. this patch disables movmisalign by default and introduces the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add Zfbfmin extension

https://gcc.gnu.org/g:f11cbf2edfbd9615cf0d8519bd7a570a2ae00397 commit f11cbf2edfbd9615cf0d8519bd7a570a2ae00397 Author: Xiao Zeng Date: Wed May 15 13:56:42 2024 +0800 RISC-V: Add Zfbfmin extension 1 In the previous patch, the libcall for BF16 was implemented:

Re: [PATCH] expmed: TRUNCATE value1 if needed in store_bit_field_using_insv

On 6/5/24 8:57 AM, YunQiang Su wrote: Richard Sandiford 于2024年6月5日周三 22:14写道： YunQiang Su writes: PR target/113179. In `store_bit_field_using_insv`, we just use SUBREG if value_mode = op_mode, while in some ports, a sign_extend will be needed, such as MIPS64: If either GPR rs or

Re: [V2 PATCH] Simplify (AND (ASHIFTRT A imm) mask) to (LSHIFTRT A imm) for vector mode.

On 6/4/24 10:22 PM, liuhongt wrote: Can you add a testcase for this? I don't mind if it's x86 specific and does a bit of asm scanning. Also note that the context for this patch has changed, so it won't automatically apply. So be extra careful when updating so that it goes into the right

Re: [PATCH] Record edge true/false value for gcov

On 6/4/24 6:26 AM, Jørgen Kvalsvik wrote: Make gcov aware which edges are the true/false to more accurately reconstruct the CFG. There are plenty of bits left in arc_info and it opens up for richer reporting. gcc/ChangeLog: * gcov-io.h (GCOV_ARC_TRUE): New.

Re: [PATCH] expmed: TRUNCATE value1 if needed in store_bit_field_using_insv

On 6/5/24 8:14 AM, Richard Sandiford wrote: YunQiang Su writes: PR target/113179. In `store_bit_field_using_insv`, we just use SUBREG if value_mode = op_mode, while in some ports, a sign_extend will be needed, such as MIPS64: If either GPR rs or GPR rt does not contain sign-extended

Re: [PATCH 0/2] fix RISC-V zcmp popretz [PR113715]

On 6/5/24 1:47 AM, Fei Gao wrote: On 2024-06-05 14:36  Kito Cheng wrote: Thanks for fixing this issue, and I am wondering doest it possible to fix that without introduce target hook? I ask that because...GCC 14 also has this bug, but I am not sure it's OK to introduce new target hook for

Re: [PATCH 0/2] fix RISC-V zcmp popretz [PR113715]

On 6/5/24 12:36 AM, Kito Cheng wrote: Thanks for fixing this issue, and I am wondering doest it possible to fix that without introduce target hook? I ask that because...GCC 14 also has this bug, but I am not sure it's OK to introduce new target hook for release branch? or would you suggest we

Re: Which GCC version start to support RISC-V RVV1.0

On 6/4/24 8:51 PM, Erick Kuo-Chen Huang(黃國鎭) via Gcc-help wrote: Hi, We would like to know which GCC version start to support RISC-V RVV1.0 ? We appreciate for your help. gcc-14. Jeff

Re: [PATCH-1v2] fwprop: Replace rtx_cost with insn_cost in try_fwprop_subst_pattern [PR113325]

On 6/5/24 3:08 AM, Richard Sandiford wrote: HAO CHEN GUI writes: Hi, This patch replaces rtx_cost with insn_cost in forward propagation. In the PR, one constant vector should be propagated and replace a pseudo in a store insn if we know it's a duplicated constant vector. It reduces the

Re: [PATCH v4] RISC-V: Introduce -mvector-strict-align.

On 5/28/24 1:19 PM, Robin Dapp wrote: Hi, this patch disables movmisalign by default and introduces the -mno-vector-strict-align option to override it and re-enable movmisalign. For now, generic-ooo is the only uarch that supports misaligned vector access. The patch also adds a

Re: [PATCH] Don't simplify NAN/INF or out-of-range constant for FIX/UNSIGNED_FIX.

On 5/26/24 7:08 PM, liuhongt wrote: Update in V2: Guard constant folding for overflow value in fold_convert_const_int_from_real with flag_trapping_math. Add -fno-trapping-math to related testcases which warn for overflow in conversion from floating point to integer. Bootstrapped and

Re: [PATCH-1] fwprop: Replace rtx_cost with insn_cost in try_fwprop_subst_pattern [PR113325]

On 1/25/24 6:16 PM, HAO CHEN GUI wrote: Hi, This patch replaces rtx_cost with insn_cost in forward propagation. In the PR, one constant vector should be propagated and replace a pseudo in a store insn if we know it's a duplicated constant vector. It reduces the insn cost but not rtx cost.

Re: [PATCH 1/2] Simplify (AND (ASHIFTRT A imm) mask) to (LSHIFTRT A imm) for vector mode.

On 5/23/24 8:25 PM, Hongtao Liu wrote: CC for review. On Tue, May 21, 2024 at 1:12 PM liuhongt wrote: When mask is (1 << (prec - imm) - 1) which is used to clear upper bits of A, then it can be simplified to LSHIFTRT. i.e Simplify (and:v8hi (ashifrt:v8hi A 8) (const_vector 0xff

Re: [PATCH] Add config file so b4 uses inbox.sourceware.org automatically

On 5/23/24 9:49 AM, Jonathan Wakely wrote: It looks like my patch[1] to make b4 figure this out automagically won't be accepted, so this makes it work for GCC. A similar commit could be done for each project hosted on sourceware.org if desired. [1]

Re: [PATCH v2] RISC-V: Add Zfbfmin extension

On 6/1/24 1:45 AM, Xiao Zeng wrote: 1 In the previous patch, the libcall for BF16 was implemented: 2 Riscv provides Zfbfmin extension, which completes the "Scalar BF16 Converts":

Re: [PATCH] RISC-V: Add min/max patterns for ifcvt.

On 6/3/24 11:03 AM, Palmer Dabbelt wrote: +;; Provide a minmax pattern for ifcvt to match. +(define_insn "*_cmp_3" +  [(set (match_operand:X 0 "register_operand" "=r") +    (if_then_else:X +    (bitmanip_minmax_cmp_op +    (match_operand:X 1 "register_operand" "r") +   

Re: [PATCH] check_GNU_style: Use raw strings.

On 5/31/24 1:38 PM, Robin Dapp wrote: Hi, this silences some warnings when using check_GNU_style. I didn't expect this to have any bootstrap or regtest impact but I still ran it on x86 - no change. Regards Robin contrib/ChangeLog: * check_GNU_style_lib.py: Use raw strings for

Re: Epiphany target

On 6/3/24 8:12 AM, Andreas Olofsson via Gcc wrote: Hi, Letting the community know that we are working on getting the Epiphany port back to a proper operational state. There will be a GCC maintainer assigned soon. New Epiphany silicon is in development and old Epiphany devices are still in

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] tree-ssa-pre.c/115214(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE

https://gcc.gnu.org/g:6eb2b8506e4123b00c32b8a23bafdee4c8c8b7f8 commit 6eb2b8506e4123b00c32b8a23bafdee4c8c8b7f8 Author: Jiawei Date: Mon May 27 15:40:51 2024 +0800 tree-ssa-pre.c/115214(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE when deal special cases.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Just the riscv bits from:

https://gcc.gnu.org/g:d9181d77435b2037dfbdf7e1b54de8d3e2748beb commit d9181d77435b2037dfbdf7e1b54de8d3e2748beb Author: Jeff Law Date: Sun Jun 2 13:19:16 2024 -0600 Just the riscv bits from: commit a0d60660f2aae2d79685f73d568facb2397582d8 Author: Andrew Pinski Date: Wed

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Use Zbkb for general 64 bit constants when profitable

https://gcc.gnu.org/g:e26b14182c2c18deab641b4b81fc53c456573818 commit e26b14182c2c18deab641b4b81fc53c456573818 Author: Jeff Law Date: Fri May 31 21:45:01 2024 -0600 [to-be-committed] [RISC-V] Use Zbkb for general 64 bit constants when profitable Basically this adds the ability

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Remove dead perm series code and document.

https://gcc.gnu.org/g:43c16b2ab69f25e4705b9582ed0ac921e1ec620e commit 43c16b2ab69f25e4705b9582ed0ac921e1ec620e Author: Robin Dapp Date: Fri May 17 12:48:52 2024 +0200 RISC-V: Remove dead perm series code and document. With the introduction of shuffle_series_patterns the explicit

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add vector popcount, clz, ctz.

https://gcc.gnu.org/g:36260f7a2be90ed27498a28c4d0490414db1491f commit 36260f7a2be90ed27498a28c4d0490414db1491f Author: Robin Dapp Date: Wed May 15 17:41:07 2024 +0200 RISC-V: Add vector popcount, clz, ctz. This patch adds the zvbb vcpop, vclz and vctz to the autovec machinery

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add vandn combine helper.

https://gcc.gnu.org/g:2ec5e6c7a87ebd75ab937ea5f8d926fc212631e2 commit 2ec5e6c7a87ebd75ab937ea5f8d926fc212631e2 Author: Robin Dapp Date: Wed May 15 15:01:35 2024 +0200 RISC-V: Add vandn combine helper. This patch adds a combine pattern for vandn as well as tests for it.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Use widening shift for scatter/gather if applicable.

https://gcc.gnu.org/g:5eade133c823d4ef2e226991c6ab5cfb63f2b338 commit 5eade133c823d4ef2e226991c6ab5cfb63f2b338 Author: Robin Dapp Date: Fri May 10 13:37:03 2024 +0200 RISC-V: Use widening shift for scatter/gather if applicable. With the zvbb extension we can emit a widening shift

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add vwsll combine helpers.

https://gcc.gnu.org/g:9d209e560d83b535ed0e916a5e964381c6111750 commit 9d209e560d83b535ed0e916a5e964381c6111750 Author: Robin Dapp Date: Mon May 13 22:09:35 2024 +0200 RISC-V: Add vwsll combine helpers. This patch enables the usage of vwsll in autovec context by adding the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Split vwadd.wx and vwsub.wx and add helpers.

https://gcc.gnu.org/g:a0fef33b5183de07ca0b0cf248e917d4849a6f2f commit a0fef33b5183de07ca0b0cf248e917d4849a6f2f Author: Robin Dapp Date: Thu May 16 12:43:43 2024 +0200 RISC-V: Split vwadd.wx and vwsub.wx and add helpers. vwadd.wx and vwsub.wx have the same problem vfwadd.wf had.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Do not allow v0 as dest when merging [PR115068].

https://gcc.gnu.org/g:901c9e95366a04a0ccf9af86654ddeb9ae18ee59 commit 901c9e95366a04a0ccf9af86654ddeb9ae18ee59 Author: Robin Dapp Date: Mon May 13 13:49:57 2024 +0200 RISC-V: Do not allow v0 as dest when merging [PR115068]. This patch splits the vfw...wf pattern so we do not emit

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Use pack to handle repeating constants

https://gcc.gnu.org/g:1ca03816836d050e56f8d3c0e1ce0943e39c0444 commit 1ca03816836d050e56f8d3c0e1ce0943e39c0444 Author: Jeff Law Date: Wed May 29 07:41:55 2024 -0600 [to-be-committed] [RISC-V] Use pack to handle repeating constants This patch utilizes zbkb to improve the code we

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Some basic patterns for zbkb code generation

https://gcc.gnu.org/g:95439d053f53a014bed59465ceb563baf44e9a6f commit 95439d053f53a014bed59465ceb563baf44e9a6f Author: Lyut Nersisyan Date: Tue May 28 09:17:50 2024 -0600 [to-be-committed] [RISC-V] Some basic patterns for zbkb code generation And here's Lyut's basic Zbkb support.

Re: RISC-V: Fix round_32.c test on RV32

On 5/27/24 4:17 PM, Jivan Hakobyan wrote: Ya, makes sense -- I guess the current values aren't that exciting for execution, but we could just add some more interesting ones... During the development of the patch, I have an issue with large numbers (2e34, -2e34). They are used in

Re: [RFC/RFA] [PATCH 02/12] Add built-ins and tests for bit-forward and bit-reversed CRCs

On 5/28/24 12:44 AM, Richard Biener wrote: On Mon, May 27, 2024 at 5:16 PM Jeff Law wrote: On 5/27/24 12:38 AM, Richard Biener wrote: On Fri, May 24, 2024 at 10:44 AM Mariam Arutunian wrote: This patch introduces new built-in functions to GCC for computing bit-forward and bit

Re: [PATCH 5/5][v3] RISC-V: Avoid inserting after a GIMPLE_COND with SLP and early break

On 5/31/24 7:44 AM, Richard Biener wrote: When vectorizing an early break loop with LENs (do we miss some check here to disallow this?) we can end up deciding to insert stmts after a GIMPLE_COND when doing SLP scheduling and trying to be conservative with placing of stmts only dependent on

Re: [PING] [PATCH] RISC-V: Add Zfbfmin extension

On 5/30/24 5:38 AM, Xiao Zeng wrote: 1 In the previous patch, the libcall for BF16 was implemented: 2 Riscv provides Zfbfmin extension, which completes the "Scalar BF16 Converts":

Re: [PATCH] ifcvt: Clarify if_info.original_cost.

On 5/31/24 9:03 AM, Robin Dapp wrote: Hi, before noce_find_if_block processes a block it sets up an if_info structure that holds the original costs. At that point the costs of the then/else blocks have not been added so we only care about the "if" cost. The code originally used BRANCH_COST

Re: [PATCH] RISC-V: Add min/max patterns for ifcvt.

On 5/31/24 9:07 AM, Robin Dapp wrote: Hi, ifcvt likes to emit (set (if_then_else) (ge (reg 1) (reg2)) (reg 1) (reg 2)) which can be recognized as min/max patterns in the backend. This patch adds such patterns and the respective iterators as well as a test. This depends

[gcc r15-965] [to-be-committed] [RISC-V] Use Zbkb for general 64 bit constants when profitable

https://gcc.gnu.org/g:c0ded050cd29cc73f78cb4ab23674c7bc024969e commit r15-965-gc0ded050cd29cc73f78cb4ab23674c7bc024969e Author: Jeff Law Date: Fri May 31 21:45:01 2024 -0600 [to-be-committed] [RISC-V] Use Zbkb for general 64 bit constants when profitable Basically this adds

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