[gcc r15-1172] [committed] [RISC-V] Drop dead round_32 test

https://gcc.gnu.org/g:95161c6abfbd7ba9fab0b538ccc885f5980efbee commit r15-1172-g95161c6abfbd7ba9fab0b538ccc885f5980efbee Author: Jeff Law Date: Mon Jun 10 22:39:40 2024 -0600 [committed] [RISC-V] Drop dead round_32 test This test is no longer useful. It doesn't test what it was

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object

https://gcc.gnu.org/g:08a6582277f62c1b5873dfa4d385a2b2e8843d8f commit 08a6582277f62c1b5873dfa4d385a2b2e8843d8f Author: Raphael Zinsly Date: Mon Jun 10 14:16:16 2024 -0600 [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object bext is defined as (src >> n)

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Just the testsuite bits from:

https://gcc.gnu.org/g:1d97b9d17699ea5fdd0945b8ce8aecda79829ff4 commit 1d97b9d17699ea5fdd0945b8ce8aecda79829ff4 Author: Pan Li Date: Mon Jun 10 14:13:38 2024 -0600 Just the testsuite bits from: [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match When

[gcc r15-1168] [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object

https://gcc.gnu.org/g:9aaf29b9ba5ffe332220d002ddde85d96fd6657d commit r15-1168-g9aaf29b9ba5ffe332220d002ddde85d96fd6657d Author: Raphael Zinsly Date: Mon Jun 10 14:16:16 2024 -0600 [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object bext is defined as

[gcc r15-1167] [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match

https://gcc.gnu.org/g:d03ff3fd3e2da1352a404e3c53fe61314569345c commit r15-1167-gd03ff3fd3e2da1352a404e3c53fe61314569345c Author: Pan Li Date: Mon Jun 10 14:13:38 2024 -0600 [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match When enabled the PHI handing for

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object

https://gcc.gnu.org/g:c5c054c429ac5a4d1a665d6e5e4634973dffae5a commit c5c054c429ac5a4d1a665d6e5e4634973dffae5a Author: Raphael Zinsly Date: Mon Jun 10 07:03:00 2024 -0600 [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object bext is defined as (src >> n)

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] FreeBSD: Stop linking _p libs for -pg as of FreeBSD 14

https://gcc.gnu.org/g:7cf4c1e16755f7adab3bff983d980d6ae0b9a6f3 commit 7cf4c1e16755f7adab3bff983d980d6ae0b9a6f3 Author: Andreas Tobler Date: Sun Jun 9 23:18:04 2024 +0200 FreeBSD: Stop linking _p libs for -pg as of FreeBSD 14 As of FreeBSD version 14, FreeBSD no longer provides

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Fix false-positive uninitialized variable

https://gcc.gnu.org/g:e0a5507e6888f85e2ff53aff76c67293890bed85 commit e0a5507e6888f85e2ff53aff76c67293890bed85 Author: Jeff Law Date: Sun Jun 9 09:17:55 2024 -0600 [committed] [RISC-V] Fix false-positive uninitialized variable Andreas noted we were getting an uninit warning after

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates.

https://gcc.gnu.org/g:21b9c1625d9178475ebbb7d524923e421a93906d commit 21b9c1625d9178475ebbb7d524923e421a93906d Author: Roger Sayle Date: Sat Jun 8 19:47:08 2024 -0600 [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates. This patch tweaks RTL

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement .SAT_SUB for unsigned scalar int

https://gcc.gnu.org/g:d63ee880aa3931d37fe73570d3a41952daafd8ee commit d63ee880aa3931d37fe73570d3a41952daafd8ee Author: Pan Li Date: Wed Jun 5 16:42:05 2024 +0800 RISC-V: Implement .SAT_SUB for unsigned scalar int As the middle support of .SAT_SUB committed, implement the

[gcc r15-1164] [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object

https://gcc.gnu.org/g:3472c1b500cf9184766237bfd3d102aa8451b99f commit r15-1164-g3472c1b500cf9184766237bfd3d102aa8451b99f Author: Raphael Zinsly Date: Mon Jun 10 07:03:00 2024 -0600 [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object bext is defined as

[gcc r15-1123] [committed] [RISC-V] Fix false-positive uninitialized variable

https://gcc.gnu.org/g:932c6f8dd8859afb13475c2de466bd1a159530da commit r15-1123-g932c6f8dd8859afb13475c2de466bd1a159530da Author: Jeff Law Date: Sun Jun 9 09:17:55 2024 -0600 [committed] [RISC-V] Fix false-positive uninitialized variable Andreas noted we were getting an uninit

[gcc r15-1120] [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates.

https://gcc.gnu.org/g:2277f987979445f4390a5c6e092d79e04814d641 commit r15-1120-g2277f987979445f4390a5c6e092d79e04814d641 Author: Roger Sayle Date: Sat Jun 8 19:47:08 2024 -0600 [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates. This patch

Re: How to target a processor with very primitive addressing modes?

On 6/8/24 10:45 AM, Paul Koning via Gcc wrote: On Jun 8, 2024, at 5:32 AM, Mikael Pettersson via Gcc wrote: On Thu, Jun 6, 2024 at 8:59 PM Dimitar Dimitrov wrote: Have you tried defining TARGET_LEGITIMIZE_ADDRESS for your target? From a quick search I see that the iq2000 and rx

Re: How to target a processor with very primitive addressing modes?

On 6/8/24 3:32 AM, Mikael Pettersson via Gcc wrote: On Thu, Jun 6, 2024 at 8:59 PM Dimitar Dimitrov wrote: Have you tried defining TARGET_LEGITIMIZE_ADDRESS for your target? From a quick search I see that the iq2000 and rx backends are rewriting some PLUS expression addresses with insn

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 3

https://gcc.gnu.org/g:4b3c0b3380d38553e76bbf01e1ac5b3f66dc3d5c commit 4b3c0b3380d38553e76bbf01e1ac5b3f66dc3d5c Author: Pan Li Date: Mon Jun 3 10:24:47 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 3 After the middle-end support the form 3 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 1

https://gcc.gnu.org/g:efe00579c04e02b6132c678962ce8050c8759bee commit efe00579c04e02b6132c678962ce8050c8759bee Author: Pan Li Date: Wed May 29 14:15:45 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 1 After the middle-end support the form 1 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Regenerate opt urls.

https://gcc.gnu.org/g:4f20feccf708ff7a7af5d776ca87d4995ef46f76 commit 4f20feccf708ff7a7af5d776ca87d4995ef46f76 Author: Robin Dapp Date: Thu Jun 6 09:32:28 2024 +0200 RISC-V: Regenerate opt urls. I wasn't aware that I needed to regenerate the opt urls when adding an option.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 5

https://gcc.gnu.org/g:1a6d2ed7fbd20bfa3079da4700eb591f2abaa395 commit 1a6d2ed7fbd20bfa3079da4700eb591f2abaa395 Author: Pan Li Date: Mon Jun 3 10:43:10 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 5 After the middle-end support the form 5 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 2

https://gcc.gnu.org/g:6f5119eed91a2ec0708e38c9f2e5d58169a3f53e commit 6f5119eed91a2ec0708e38c9f2e5d58169a3f53e Author: Pan Li Date: Mon Jun 3 09:35:49 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 2 After the middle-end support the form 2 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 4

https://gcc.gnu.org/g:b93df02d58c0c448c4b524c07bdf5f3d7c305378 commit b93df02d58c0c448c4b524c07bdf5f3d7c305378 Author: Pan Li Date: Mon Jun 3 10:33:15 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 4 After the middle-end support the form 4 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Simplify (AND (ASHIFTRT A imm) mask) to (LSHIFTRT A imm) for vector mode.

https://gcc.gnu.org/g:e46fc82745c1a917ade318222d514c881c68ce1a commit e46fc82745c1a917ade318222d514c881c68ce1a Author: liuhongt Date: Fri Apr 19 10:29:34 2024 +0800 Simplify (AND (ASHIFTRT A imm) mask) to (LSHIFTRT A imm) for vector mode. When mask is (1 << (prec - imm) - 1)

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Introduce -mvector-strict-align.

https://gcc.gnu.org/g:0e0b666a30f53364292432903b68febd85a3e114 commit 0e0b666a30f53364292432903b68febd85a3e114 Author: Robin Dapp Date: Tue May 28 21:19:26 2024 +0200 RISC-V: Introduce -mvector-strict-align. this patch disables movmisalign by default and introduces the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add Zfbfmin extension

https://gcc.gnu.org/g:f11cbf2edfbd9615cf0d8519bd7a570a2ae00397 commit f11cbf2edfbd9615cf0d8519bd7a570a2ae00397 Author: Xiao Zeng Date: Wed May 15 13:56:42 2024 +0800 RISC-V: Add Zfbfmin extension 1 In the previous patch, the libcall for BF16 was implemented:

Re: Which GCC version start to support RISC-V RVV1.0

On 6/4/24 8:51 PM, Erick Kuo-Chen Huang(黃國鎭) via Gcc-help wrote: Hi, We would like to know which GCC version start to support RISC-V RVV1.0 ? We appreciate for your help. gcc-14. Jeff

Re: Epiphany target

On 6/3/24 8:12 AM, Andreas Olofsson via Gcc wrote: Hi, Letting the community know that we are working on getting the Epiphany port back to a proper operational state. There will be a GCC maintainer assigned soon. New Epiphany silicon is in development and old Epiphany devices are still in

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] tree-ssa-pre.c/115214(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE

https://gcc.gnu.org/g:6eb2b8506e4123b00c32b8a23bafdee4c8c8b7f8 commit 6eb2b8506e4123b00c32b8a23bafdee4c8c8b7f8 Author: Jiawei Date: Mon May 27 15:40:51 2024 +0800 tree-ssa-pre.c/115214(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE when deal special cases.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Just the riscv bits from:

https://gcc.gnu.org/g:d9181d77435b2037dfbdf7e1b54de8d3e2748beb commit d9181d77435b2037dfbdf7e1b54de8d3e2748beb Author: Jeff Law Date: Sun Jun 2 13:19:16 2024 -0600 Just the riscv bits from: commit a0d60660f2aae2d79685f73d568facb2397582d8 Author: Andrew Pinski Date: Wed

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Use Zbkb for general 64 bit constants when profitable

https://gcc.gnu.org/g:e26b14182c2c18deab641b4b81fc53c456573818 commit e26b14182c2c18deab641b4b81fc53c456573818 Author: Jeff Law Date: Fri May 31 21:45:01 2024 -0600 [to-be-committed] [RISC-V] Use Zbkb for general 64 bit constants when profitable Basically this adds the ability

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Remove dead perm series code and document.

https://gcc.gnu.org/g:43c16b2ab69f25e4705b9582ed0ac921e1ec620e commit 43c16b2ab69f25e4705b9582ed0ac921e1ec620e Author: Robin Dapp Date: Fri May 17 12:48:52 2024 +0200 RISC-V: Remove dead perm series code and document. With the introduction of shuffle_series_patterns the explicit

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add vector popcount, clz, ctz.

https://gcc.gnu.org/g:36260f7a2be90ed27498a28c4d0490414db1491f commit 36260f7a2be90ed27498a28c4d0490414db1491f Author: Robin Dapp Date: Wed May 15 17:41:07 2024 +0200 RISC-V: Add vector popcount, clz, ctz. This patch adds the zvbb vcpop, vclz and vctz to the autovec machinery

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add vandn combine helper.

https://gcc.gnu.org/g:2ec5e6c7a87ebd75ab937ea5f8d926fc212631e2 commit 2ec5e6c7a87ebd75ab937ea5f8d926fc212631e2 Author: Robin Dapp Date: Wed May 15 15:01:35 2024 +0200 RISC-V: Add vandn combine helper. This patch adds a combine pattern for vandn as well as tests for it.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Use widening shift for scatter/gather if applicable.

https://gcc.gnu.org/g:5eade133c823d4ef2e226991c6ab5cfb63f2b338 commit 5eade133c823d4ef2e226991c6ab5cfb63f2b338 Author: Robin Dapp Date: Fri May 10 13:37:03 2024 +0200 RISC-V: Use widening shift for scatter/gather if applicable. With the zvbb extension we can emit a widening shift

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add vwsll combine helpers.

https://gcc.gnu.org/g:9d209e560d83b535ed0e916a5e964381c6111750 commit 9d209e560d83b535ed0e916a5e964381c6111750 Author: Robin Dapp Date: Mon May 13 22:09:35 2024 +0200 RISC-V: Add vwsll combine helpers. This patch enables the usage of vwsll in autovec context by adding the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Split vwadd.wx and vwsub.wx and add helpers.

https://gcc.gnu.org/g:a0fef33b5183de07ca0b0cf248e917d4849a6f2f commit a0fef33b5183de07ca0b0cf248e917d4849a6f2f Author: Robin Dapp Date: Thu May 16 12:43:43 2024 +0200 RISC-V: Split vwadd.wx and vwsub.wx and add helpers. vwadd.wx and vwsub.wx have the same problem vfwadd.wf had.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Do not allow v0 as dest when merging [PR115068].

https://gcc.gnu.org/g:901c9e95366a04a0ccf9af86654ddeb9ae18ee59 commit 901c9e95366a04a0ccf9af86654ddeb9ae18ee59 Author: Robin Dapp Date: Mon May 13 13:49:57 2024 +0200 RISC-V: Do not allow v0 as dest when merging [PR115068]. This patch splits the vfw...wf pattern so we do not emit

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Use pack to handle repeating constants

https://gcc.gnu.org/g:1ca03816836d050e56f8d3c0e1ce0943e39c0444 commit 1ca03816836d050e56f8d3c0e1ce0943e39c0444 Author: Jeff Law Date: Wed May 29 07:41:55 2024 -0600 [to-be-committed] [RISC-V] Use pack to handle repeating constants This patch utilizes zbkb to improve the code we

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Some basic patterns for zbkb code generation

https://gcc.gnu.org/g:95439d053f53a014bed59465ceb563baf44e9a6f commit 95439d053f53a014bed59465ceb563baf44e9a6f Author: Lyut Nersisyan Date: Tue May 28 09:17:50 2024 -0600 [to-be-committed] [RISC-V] Some basic patterns for zbkb code generation And here's Lyut's basic Zbkb support.

[gcc r15-965] [to-be-committed] [RISC-V] Use Zbkb for general 64 bit constants when profitable

https://gcc.gnu.org/g:c0ded050cd29cc73f78cb4ab23674c7bc024969e commit r15-965-gc0ded050cd29cc73f78cb4ab23674c7bc024969e Author: Jeff Law Date: Fri May 31 21:45:01 2024 -0600 [to-be-committed] [RISC-V] Use Zbkb for general 64 bit constants when profitable Basically this adds the

[gcc r15-901] [to-be-committed] [RISC-V] Use pack to handle repeating constants

https://gcc.gnu.org/g:3ae02dcb108df426838bbbcc73d7d01855bc1196 commit r15-901-g3ae02dcb108df426838bbbcc73d7d01855bc1196 Author: Jeff Law Date: Wed May 29 07:41:55 2024 -0600 [to-be-committed] [RISC-V] Use pack to handle repeating constants This patch utilizes zbkb to improve the

[gcc r15-864] [to-be-committed] [RISC-V] Some basic patterns for zbkb code generation

https://gcc.gnu.org/g:236116068151bbc72aaaf53d0f223fe06f7e3bac commit r15-864-g236116068151bbc72aaaf53d0f223fe06f7e3bac Author: Lyut Nersisyan Date: Tue May 28 09:17:50 2024 -0600 [to-be-committed] [RISC-V] Some basic patterns for zbkb code generation And here's Lyut's basic Zbkb

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix missing boolean_expression in zmmul extension

https://gcc.gnu.org/g:39e977a4a682e0f5109a29d35f57c5b1b957fd16 commit 39e977a4a682e0f5109a29d35f57c5b1b957fd16 Author: Liao Shihua Date: Fri May 24 13:03:57 2024 +0800 RISC-V: Fix missing boolean_expression in zmmul extension Update v1->v2 Add testcase for this patch.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed][RISC-V] Reassociate constants in logical ops

https://gcc.gnu.org/g:65e6ccc3a04ab2fa8f4fa134976a6e76b25c6549 commit 65e6ccc3a04ab2fa8f4fa134976a6e76b25c6549 Author: Lyut Nersisyan Date: Sun May 26 21:24:40 2024 -0600 [to-be-committed][RISC-V] Reassociate constants in logical ops This patch from Lyut will reassociate operands

[gcc r15-842] [to-be-committed][RISC-V] Reassociate constants in logical ops

https://gcc.gnu.org/g:160929406f0c44df5b0d377a014ebfe5027fe4e7 commit r15-842-g160929406f0c44df5b0d377a014ebfe5027fe4e7 Author: Lyut Nersisyan Date: Sun May 26 21:24:40 2024 -0600 [to-be-committed][RISC-V] Reassociate constants in logical ops This patch from Lyut will reassociate

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Try inverting for constant synthesis

https://gcc.gnu.org/g:7f716ba0f6c0360db3643c815d390aee04d2794f commit 7f716ba0f6c0360db3643c815d390aee04d2794f Author: Jeff Law Date: Sun May 26 17:54:51 2024 -0600 [to-be-committed] [RISC-V] Try inverting for constant synthesis So there's another class of constants we're failing

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed][RISC-V] Generate nearby constant, then adjust to our final desired constant

https://gcc.gnu.org/g:dbd78bcf532086b55ef133074259ad29d33a400a commit dbd78bcf532086b55ef133074259ad29d33a400a Author: Jeff Law Date: Sun May 26 10:54:18 2024 -0600 [to-be-committed][RISC-V] Generate nearby constant, then adjust to our final desired constant Next step in

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [v2] More logical op simplifications in simplify-rtx.cc

https://gcc.gnu.org/g:91f41ea3f28d8ba5d5d93dcfcd82c7d94e4e668d commit 91f41ea3f28d8ba5d5d93dcfcd82c7d94e4e668d Author: Jeff Law Date: Sat May 25 12:39:05 2024 -0600 [committed] [v2] More logical op simplifications in simplify-rtx.cc This is a revamp of what started as a target

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, v2, RISC-V] Use bclri in constant synthesis

https://gcc.gnu.org/g:b6c92195b428de63a4aabcea1a8e00911f2c596d commit b6c92195b428de63a4aabcea1a8e00911f2c596d Author: Jeff Law Date: Fri May 24 07:27:00 2024 -0600 [to-be-committed,v2,RISC-V] Use bclri in constant synthesis Testing with Zbs enabled by default showed a minor

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Enable vectorization for vect-early-break_124-pr114403.c

https://gcc.gnu.org/g:cd9b981f3b5124900f44b5e156c773de2f186ced commit cd9b981f3b5124900f44b5e156c773de2f186ced Author: xuli Date: Mon May 20 01:56:47 2024 + RISC-V: Enable vectorization for vect-early-break_124-pr114403.c Because "targetm.slow_unaligned_access" is set to true

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: avoid LUI based const mat in alloca epilogue expansion

https://gcc.gnu.org/g:d85def27f51584040cffb571ea476d43a132c59e commit d85def27f51584040cffb571ea476d43a132c59e Author: Vineet Gupta Date: Wed Mar 6 15:44:27 2024 -0800 RISC-V: avoid LUI based const mat in alloca epilogue expansion This is continuing on the prev patch in function

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733]

https://gcc.gnu.org/g:5f7595e74bba8ac4ab984ce6b47eac48b82edda2 commit 5f7595e74bba8ac4ab984ce6b47eac48b82edda2 Author: Vineet Gupta Date: Mon May 13 11:46:03 2024 -0700 RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] If the constant used for stack

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Regenerate riscv.opt.urls and i386.opt.urls

https://gcc.gnu.org/g:e42956aafe991efc2128ac0b661f2ddefd11b4f3 commit e42956aafe991efc2128ac0b661f2ddefd11b4f3 Author: Mark Wielaard Date: Mon May 20 13:13:02 2024 +0200 Regenerate riscv.opt.urls and i386.opt.urls risc-v added an -mfence-tso option. i386 removed Xeon Phi ISA

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] DSE: Fix ICE after allow vector type in get_stored_val

https://gcc.gnu.org/g:98a48906bfb653d1e18323997d0854bef18986e7 commit 98a48906bfb653d1e18323997d0854bef18986e7 Author: Pan Li Date: Tue Apr 30 09:42:39 2024 +0800 DSE: Fix ICE after allow vector type in get_stored_val We allowed vector type for get_stored_val when read is less

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed][RISC-V][PR target/115142] Do not create invalidate shift-add insn

https://gcc.gnu.org/g:58349b4561b0cc315e60ff5aa2b777a3e80c7f9f commit 58349b4561b0cc315e60ff5aa2b777a3e80c7f9f Author: Jeff Law Date: Sun May 19 09:56:16 2024 -0600 [to-be-committed][RISC-V][PR target/115142] Do not create invalidate shift-add insn The circumstances which

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement -m{, no}fence-tso

https://gcc.gnu.org/g:48ab926d0426e3e4d682d518b8656a9c6d8b9b96 commit 48ab926d0426e3e4d682d518b8656a9c6d8b9b96 Author: Palmer Dabbelt Date: Sat May 18 15:15:09 2024 -0600 RISC-V: Implement -m{,no}fence-tso Some processors from T-Head don't implement the `fence.tso` instruction

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve some shift-add sequences

https://gcc.gnu.org/g:e043aa621946842ccbc319e9683ad042abdf3ed5 commit e043aa621946842ccbc319e9683ad042abdf3ed5 Author: Jeff Law Date: Sat May 18 15:08:07 2024 -0600 [to-be-committed,RISC-V] Improve some shift-add sequences So this is a minor fix/improvement for shift-add

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix "Nan-box the result of movbf on soft-bf16"

https://gcc.gnu.org/g:5b632ee99b187761fc6bf02a8c6312278563fbdc commit 5b632ee99b187761fc6bf02a8c6312278563fbdc Author: Xiao Zeng Date: Wed May 15 16:23:16 2024 +0800 RISC-V: Fix "Nan-box the result of movbf on soft-bf16" 1 According to unpriv-isa spec:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Modify _Bfloat16 to __bf16

https://gcc.gnu.org/g:a320bcf71489a14a634dbebeccee3b4e932b4ddb commit a320bcf71489a14a634dbebeccee3b4e932b4ddb Author: Xiao Zeng Date: Fri May 17 13:48:21 2024 +0800 RISC-V: Modify _Bfloat16 to __bf16 According to the description in:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement IFN SAT_ADD for both the scalar and vector

https://gcc.gnu.org/g:0b3502c3dfe791e6c13de9c2419905519689d0da commit 0b3502c3dfe791e6c13de9c2419905519689d0da Author: Pan Li Date: Fri May 17 18:49:46 2024 +0800 RISC-V: Implement IFN SAT_ADD for both the scalar and vector The patch implement the SAT_ADD in the riscv backend as

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] internal-fn: Do not force vcond_mask operands to reg.

https://gcc.gnu.org/g:12ceb8df30661c10cfba80742a2503636359c79e commit 12ceb8df30661c10cfba80742a2503636359c79e Author: Robin Dapp Date: Fri May 10 12:44:44 2024 +0200 internal-fn: Do not force vcond_mask operands to reg. In order to directly use constants this patch removes

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add initial cost handling for segment loads/stores.

https://gcc.gnu.org/g:7a46f679b3ad302431a0fdd1dc30cca9712c92ec commit 7a46f679b3ad302431a0fdd1dc30cca9712c92ec Author: Robin Dapp Date: Mon Feb 26 13:09:15 2024 +0100 RISC-V: Add initial cost handling for segment loads/stores. This patch makes segment loads and stores more

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Cleanup some temporally files [NFC]

https://gcc.gnu.org/g:9beeebac68fc0dfb58db7d9cbdcb1b3f3cebf6aa commit 9beeebac68fc0dfb58db7d9cbdcb1b3f3cebf6aa Author: Pan Li Date: Fri May 17 07:45:19 2024 +0800 RISC-V: Cleanup some temporally files [NFC] Just notice some temporally files under gcc/config/riscv, deleted as

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Enable vectorizable early exit testsuite

https://gcc.gnu.org/g:2d6625b39c814a9dc860a361a2855d6547163a69 commit 2d6625b39c814a9dc860a361a2855d6547163a69 Author: Pan Li Date: Thu May 16 10:04:10 2024 +0800 RISC-V: Enable vectorizable early exit testsuite After we supported vectorizable early exit in RISC-V, we would like

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement vectorizable early exit with vcond_mask_len

https://gcc.gnu.org/g:a65f9b17080323a8a936ce5a627b7ff53f25030f commit a65f9b17080323a8a936ce5a627b7ff53f25030f Author: Pan Li Date: Thu May 16 10:02:40 2024 +0800 RISC-V: Implement vectorizable early exit with vcond_mask_len After we support the loop lens for the vectorizable,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Vect: Support loop len in vectorizable early exit

https://gcc.gnu.org/g:f3aa41387600263a3c05b05623bd430fd7beeed2 commit f3aa41387600263a3c05b05623bd430fd7beeed2 Author: Pan Li Date: Thu May 16 09:58:13 2024 +0800 Vect: Support loop len in vectorizable early exit This patch adds early break auto-vectorization support for target

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Vect: Support new IFN SAT_ADD for unsigned vector int

https://gcc.gnu.org/g:210fa5eb9089ee81334d8b315a6d4a0ee26b4a8d commit 210fa5eb9089ee81334d8b315a6d4a0ee26b4a8d Author: Pan Li Date: Wed May 15 10:14:06 2024 +0800 Vect: Support new IFN SAT_ADD for unsigned vector int For vectorize, we leverage the existing vect pattern recog to

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Internal-fn: Support new IFN SAT_ADD for unsigned scalar int

https://gcc.gnu.org/g:592205a276422c31872bf41764c59589e4a17c85 commit 592205a276422c31872bf41764c59589e4a17c85 Author: Pan Li Date: Wed May 15 10:14:05 2024 +0800 Internal-fn: Support new IFN SAT_ADD for unsigned scalar int This patch would like to add the middle-end presentation

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: testsuite: Drop march-string in cmpmemsi/cpymemsi tests

https://gcc.gnu.org/g:423d10a1e064ef86d1c046ee8ed89ed6c5078495 commit 423d10a1e064ef86d1c046ee8ed89ed6c5078495 Author: Christoph Müllner Date: Thu May 16 09:53:47 2024 +0200 RISC-V: testsuite: Drop march-string in cmpmemsi/cpymemsi tests The tests cmpmemsi-1.c and cpymemsi-1.c

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add Zvfbfwma extension to the -march= option

https://gcc.gnu.org/g:5b202f0c899617507fb325deb7f53611f9561f1e commit 5b202f0c899617507fb325deb7f53611f9561f1e Author: Xiao Zeng Date: Wed May 15 10:03:40 2024 +0800 RISC-V: Add Zvfbfwma extension to the -march= option This patch would like to add new sub extension (aka Zvfbfwma)

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Add missing hunk in recent change.

https://gcc.gnu.org/g:d04ee599f2b7bde5bcef0ea5ff09dbacab214046 commit d04ee599f2b7bde5bcef0ea5ff09dbacab214046 Author: Jeff Law Date: Wed May 15 17:05:24 2024 -0600 Add missing hunk in recent change. gcc/ * config/riscv/riscv-string.cc: Add missing hunk from last

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [v2, 2/2] RISC-V: strcmp expansion: Use adjust_address() for address calculation

https://gcc.gnu.org/g:3411fe01e724eb941b7416e596487c55f59cf9e4 commit 3411fe01e724eb941b7416e596487c55f59cf9e4 Author: Christoph Müllner Date: Wed May 15 12:19:40 2024 -0600 [v2,2/2] RISC-V: strcmp expansion: Use adjust_address() for address calculation We have an

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [v2, 1/2] RISC-V: Add cmpmemsi expansion

https://gcc.gnu.org/g:1687d671459b63b7e19fe33d275ebbcddd43381e commit 1687d671459b63b7e19fe33d275ebbcddd43381e Author: Christoph Müllner Date: Wed May 15 12:18:20 2024 -0600 [v2,1/2] RISC-V: Add cmpmemsi expansion GCC has a generic cmpmemsi expansion via the by-pieces framework,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Test cbo.zero expansion for rv32

https://gcc.gnu.org/g:d8f7ba2edaecdaa515d0dfca65934d2a90c63db6 commit d8f7ba2edaecdaa515d0dfca65934d2a90c63db6 Author: Christoph Müllner Date: Wed May 15 01:34:54 2024 +0200 RISC-V: Test cbo.zero expansion for rv32 We had an issue when expanding via cmo-zero for RV32. This

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Allow by-pieces to do overlapping accesses in block_move_straight

https://gcc.gnu.org/g:db2ad3d782827fefec35b3cf140a3690033098af commit db2ad3d782827fefec35b3cf140a3690033098af Author: Christoph Müllner Date: Mon Apr 29 02:53:20 2024 +0200 RISC-V: Allow by-pieces to do overlapping accesses in block_move_straight The current implementation of

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: add tests for overlapping mem ops

https://gcc.gnu.org/g:15af00b183cdc5a3884e35d733e9a2aad475a806 commit 15af00b183cdc5a3884e35d733e9a2aad475a806 Author: Christoph Müllner Date: Mon Apr 29 03:06:52 2024 +0200 RISC-V: add tests for overlapping mem ops A recent patch added the field overlap_op_by_pieces to the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add test cases for cpymem expansion

https://gcc.gnu.org/g:3993646dcfd9fe06eaca5d0252589487444c7ef5 commit 3993646dcfd9fe06eaca5d0252589487444c7ef5 Author: Christoph Müllner Date: Wed May 1 16:54:42 2024 +0200 RISC-V: Add test cases for cpymem expansion We have two mechanisms in the RISC-V backend that expand

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Allow unaligned accesses in cpymemsi expansion

https://gcc.gnu.org/g:242ebff4075f6dde512f75be4b3e4d0b880dd080 commit 242ebff4075f6dde512f75be4b3e4d0b880dd080 Author: Christoph Müllner Date: Wed May 1 18:50:38 2024 +0200 RISC-V: Allow unaligned accesses in cpymemsi expansion The RISC-V cpymemsi expansion is called, whenever

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] Fix rv32 issues with recent zicboz work

https://gcc.gnu.org/g:184fca91cc3131368c0bfe2ce84ffa835d8ef08e commit 184fca91cc3131368c0bfe2ce84ffa835d8ef08e Author: Jeff Law Date: Tue May 14 22:50:15 2024 -0600 [committed] Fix rv32 issues with recent zicboz work I should have double-checked the CI system before pushing

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Remove redundant AND in shift-add sequence

https://gcc.gnu.org/g:1db555ae358fd9a98e98c47e8f4a3cfbea155da4 commit 1db555ae358fd9a98e98c47e8f4a3cfbea155da4 Author: Jeff Law Date: Tue May 14 18:17:59 2024 -0600 [to-be-committed,RISC-V] Remove redundant AND in shift-add sequence So this patch allows us to eliminate an

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: avoid LUI based const materialization ... [part of PR/106265]

https://gcc.gnu.org/g:b80fa21091b28877984b9cc0cabefb2b5687a07e commit b80fa21091b28877984b9cc0cabefb2b5687a07e Author: Vineet Gupta Date: Mon May 13 11:45:55 2024 -0700 RISC-V: avoid LUI based const materialization ... [part of PR/106265] ... if the constant can be represented as

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 3/3] RISC-V: Add memset-zero expansion to cbo.zero

https://gcc.gnu.org/g:80bf573afa3709c9716ead134480872bf88318ca commit 80bf573afa3709c9716ead134480872bf88318ca Author: Christoph Müllner Date: Tue May 14 09:21:17 2024 -0600 [PATCH 3/3] RISC-V: Add memset-zero expansion to cbo.zero The Zicboz extension offers the cbo.zero

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 2/3] RISC-V: testsuite: Make cmo tests LTO safe

https://gcc.gnu.org/g:547adc910bdec0abc590444fe2d5d1eead4358a6 commit 547adc910bdec0abc590444fe2d5d1eead4358a6 Author: Christoph Müllner Date: Tue May 14 09:20:18 2024 -0600 [PATCH 2/3] RISC-V: testsuite: Make cmo tests LTO safe Let's add '\t' to the instruction match pattern to

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [1/3] expr: Export clear_by_pieces()

https://gcc.gnu.org/g:94b1fb81dd8f3db24b6db5476bbaa60db81014bd commit 94b1fb81dd8f3db24b6db5476bbaa60db81014bd Author: Christoph Müllner Date: Tue May 14 09:19:13 2024 -0600 [1/3] expr: Export clear_by_pieces() Make clear_by_pieces() available to other parts of the compiler,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve AND with some constants

https://gcc.gnu.org/g:2d309988ce6388f5a4531a768ba85a983dc50535 commit 2d309988ce6388f5a4531a768ba85a983dc50535 Author: Jeff Law Date: Mon May 13 17:37:46 2024 -0600 [to-be-committed,RISC-V] Improve AND with some constants If we have an AND with a constant operand and the constant

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix format issue for trailing operator [NFC]

https://gcc.gnu.org/g:4bcc64ea9e0232535a3fd9a2ee41775e78803244 commit 4bcc64ea9e0232535a3fd9a2ee41775e78803244 Author: Pan Li Date: Tue May 14 09:38:55 2024 +0800 RISC-V: Fix format issue for trailing operator [NFC] This patch would like to fix below format issue of trailing

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar

https://gcc.gnu.org/g:7bee3e55f02b3ae55128b22db20d0030cbeb745e commit 7bee3e55f02b3ae55128b22db20d0030cbeb745e Author: Pan Li Date: Sat May 11 15:25:28 2024 +0800 RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar For the vfw vx format RVV intrinsic, the scalar type

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve single inverted bit extraction - v3

https://gcc.gnu.org/g:ab251bdcabb261d630eef18f022c63ae9b8e3cd3 commit ab251bdcabb261d630eef18f022c63ae9b8e3cd3 Author: Jeff Law Date: Mon May 13 07:14:08 2024 -0600 [to-be-committed,RISC-V] Improve single inverted bit extraction - v3 So this patch fixes a minor code generation

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve usage of slli.uw in constant synthesis

https://gcc.gnu.org/g:a971125e9455f91915d5be5e701c1cfcafed2b94 commit a971125e9455f91915d5be5e701c1cfcafed2b94 Author: Jeff Law Date: Sun May 12 07:12:04 2024 -0600 [to-be-committed,RISC-V] Improve usage of slli.uw in constant synthesis And an improvement to using slli.uw...

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] RISC-V Fix minor regression in synthesis WRT bseti usage

https://gcc.gnu.org/g:4853bebb4dd07ffa6d836f3a8f630188e3180662 commit 4853bebb4dd07ffa6d836f3a8f630188e3180662 Author: Jeff Law Date: Sun May 12 07:05:43 2024 -0600 [to-be-committed] RISC-V Fix minor regression in synthesis WRT bseti usage Overnight testing showed a small number

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] Use shNadd for constant synthesis

https://gcc.gnu.org/g:972cb5c8dbb56c378c12d2ca88b1940c1c1c1c45 commit 972cb5c8dbb56c378c12d2ca88b1940c1c1c1c45 Author: Jeff Law Date: Fri May 10 13:49:44 2024 -0600 [RISC-V] Use shNadd for constant synthesis So here's the next idiom to improve constant synthesis. The

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix typos in code or comment [NFC]

https://gcc.gnu.org/g:73fe7fd03bc4adeac1b5ce7619b58b60e9f5dca6 commit 73fe7fd03bc4adeac1b5ce7619b58b60e9f5dca6 Author: Kito Cheng Date: Tue May 7 10:18:58 2024 +0800 RISC-V: Fix typos in code or comment [NFC] Just found some typo when fixing bugs and then use aspell to find few

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Provide splitting guidance to combine to faciliate shNadd.uw generation

https://gcc.gnu.org/g:a4b72b2f9d6e5a560ebb42f485121d66576979ee commit a4b72b2f9d6e5a560ebb42f485121d66576979ee Author: Jeff Law Date: Thu May 9 21:07:06 2024 -0600 [committed] [RISC-V] Provide splitting guidance to combine to faciliate shNadd.uw generation This fixes a minor

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add tests for cpymemsi expansion

https://gcc.gnu.org/g:94912842c2baae5ac6a1fe0c0d91330a7376d21f commit 94912842c2baae5ac6a1fe0c0d91330a7376d21f Author: Christoph Müllner Date: Thu Apr 11 12:07:10 2024 +0200 RISC-V: Add tests for cpymemsi expansion cpymemsi expansion was available for RISC-V since the initial

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16

https://gcc.gnu.org/g:6c5e2178e97baaba8ca156bc705222eae9a52f17 commit 6c5e2178e97baaba8ca156bc705222eae9a52f17 Author: Xiao Zeng Date: Wed May 8 14:00:58 2024 -0600 [PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16 1 This patch implements the Nan-box of bf16.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Make full-vec-move1.c test robust for optimization

https://gcc.gnu.org/g:227ec9bfd49a7bf388f5c5ddd4f556e254c7a928 commit 227ec9bfd49a7bf388f5c5ddd4f556e254c7a928 Author: Pan Li Date: Thu May 9 10:56:46 2024 +0800 RISC-V: Make full-vec-move1.c test robust for optimization During investigate the support of early break autovec, we

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V][V2] Fix incorrect if-then-else nesting of Zbs usage in constant synthesis

https://gcc.gnu.org/g:b30496ab6f0706b373ca68cea832fe13dd0c0e59 commit b30496ab6f0706b373ca68cea832fe13dd0c0e59 Author: Jeff Law Date: Wed May 8 13:44:00 2024 -0600 [RISC-V][V2] Fix incorrect if-then-else nesting of Zbs usage in constant synthesis Reposting without the patch that

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add zero_extract support for rv64gc

https://gcc.gnu.org/g:76f36d93c3107544c6dbdffa616599ce3fdb44eb commit 76f36d93c3107544c6dbdffa616599ce3fdb44eb Author: Christoph Müllner Date: Mon May 6 12:33:32 2024 +0200 RISC-V: Add zero_extract support for rv64gc The combiner attempts to optimize a zero-extension of a logical

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Cover sign-extensions in lshr3_zero_extend_4

https://gcc.gnu.org/g:d3660f7816fbc403a97492545a687b0651fe3429 commit d3660f7816fbc403a97492545a687b0651fe3429 Author: Christoph Müllner Date: Tue May 7 22:23:26 2024 +0200 RISC-V: Cover sign-extensions in lshr3_zero_extend_4 The lshr3_zero_extend_4 pattern targets bit extraction

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2

https://gcc.gnu.org/g:31ab40016ae2864e4aa7741a1e3b6d867a6779cc commit 31ab40016ae2864e4aa7741a1e3b6d867a6779cc Author: Christoph Müllner Date: Tue May 7 23:26:02 2024 +0200 RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2 The pattern lshrsi3_zero_extend_2 extracts the MSB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add test for sraiw-31 special case

https://gcc.gnu.org/g:929ef4d2fa08eabbf645c86ffe12ebbfb8219190 commit 929ef4d2fa08eabbf645c86ffe12ebbfb8219190 Author: Christoph Müllner Date: Tue May 7 22:59:44 2024 +0200 RISC-V: Add test for sraiw-31 special case We already optimize a sign-extension of a right-shift by 31 in

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