[PATCH] [x86_64]: Zhaoxin shijidadao enablement

From: mayshao Hi all: This patch enables -march/-mtune=shijidadao, costs and tunings are set according to the characteristics of the processor. Bootstrapped /regtested X86_64. Ok for trunk? BR Mayshao gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_zhaoxin_cpu

Re: [PATCH] invoke.texi: Clarify -march=lujiazui

Hi Jakub: I think the modified lujiazui description is what actually happens,thanks. BR Mayshao [这封邮件来自外部发件人 谨防风险] Hi! Yesterday I was searching which exact CPUs are affected by the PR114576 wrong-code issue and went from the PTA_* bitmasks in GCC, so arrived at the goldmont, goldmont

Re: [PATCH] [x86_64]: Zhaoxin yongfeng enablement

>On Fri, Oct 27, 2023 at 12:20 PM mayshao wrote: >> >> On 2023/10/26 17:34, Uros Bizjak wrote: >> > On Wed, Oct 25, 2023 at 8:43 AM mayshao wrote: >> >> >> >> Hi all: >> >> This patch enables -march/-mtune=yongfeng, costs

[PATCH] [x86_64]: Zhaoxin yongfeng enablement

Hi all: This patch enables -march/-mtune=yongfeng, costs and tunings are set according to the characteristics of the processor. We add a new md file to describe yongfeng processor. Bootstrapped /regtested X86_64. Ok for trunk? BR Mayshao gcc/ChangeLog: * common/config/i386

[gcc10 backport] i386: Call get_available_features for all CPUs with max_level >= 1 [PR100758]

From: mayshao-oc Hi Jakub: This is backport of the fix for PR target/100758 from mainline to the gcc10 release branch. Because the bug still exists in gcc10 on Zhaoxin platform, and it will incur ISA feature detection failure, we want to fix it as the mainline.This patch has been retested

[gcc11 backport] i386: Call get_available_features for all CPUs with max_level >= 1 [PR100758]

branch on Intel,Amd,Zhaoxin with make bootstrap and make -k check without failure. Ok for the gcc11 branch? BR Mayshao gcc/ChangeLog: PR target/100758 * common/config/i386/cpuinfo.h (cpu_indicator_init): Call get_available_features for all CPUs with max_level >= 1, rat

[gcc12 backport] i386: Call get_available_features for all CPUs with max_level >= 1 [PR100758]

From: mayshao-oc Hi Jakub: This is backport of the fix for PR target/100758 from mainline to the gcc12 release branch. Because the bug still exists in gcc12 on Zhaoxin platform, and it will incur ISA feature detection failure, we want to fix it as the mainline.This patch has been retested

[Bug target/100758] __builtin_cpu_supports does not (always) detect "sse2"

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100758 --- Comment #24 from Mayshao-oc at zhaoxin dot com --- Hi Jakub: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100758 Thanks for your patch. We test it works on all zhaoxin platforms. We find the same bug still

Re: [PATCH] i386: correct division modeling in lujiazui.md

>Ping. If there are any questions or concerns about the patch, please let me >know: I'm interested in continuing this cleanup at least for older AMD models. > Hi Alexander: According to the speccpu2017 benchmark result, the patch looks good in lujiazui. BR Mayshao >I n

答复: [PATCH] i386: correct division modeling in lujiazui.md

he result , we will give feedback right away. BR Mayshao >I noticed I had an extra line in my Changelog: > >> (lua_sseicvt_si): Ditto. > >It got there accidentally and I will drop it. > >Alexander > >On Fri, 9 Dec 2022, Alexander Monakov wrote: > >> Model

Re: [PATCH] [x86_64] Zhaoxin lujiazui enablement

oth cases exist in our products. > Good. Then we miss a CPU features detection for (vendor == > signature_CENTAUR_ebx && family < 0x07) > aka https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364. But it's not worth > it as it's a legacy hardware, > right? Yes, for legacy hardware, we need to keep it work correctly, but in respect of performance, we don't spend a lot of time to tune. > Cheers, > Martin >> >>> Thanks, >> Martin >> >> BR >> Mayshao

Re: [PATCH] [x86_64] Zhaoxin lujiazui enablement

family == 0x7 ? > Similarly, are there any signature_SHANGHAI_ebx modes with family < 0x7 ? Yes, both cases exist in our products. > Thanks, > Martin BR Mayshao

Re: [PATCH] [x86_64]: Zhaoxin lujiazui enablement

> On Tue, May 17, 2022 at 5:15 AM mayshao wrote: >> Hi Uros: >> This patch fix Zhaoxin CPU vendor ID detection problem and add >> zhaoxin "lujiazui" processor support. >> Currently gcc can't recognize Zhaoxin CPU(vendor ID "CentaurHau

[PATCH] [x86_64]: Zhaoxin lujiazui enablement

Hi Uros: This patch fix Zhaoxin CPU vendor ID detection problem and add zhaoxin "lujiazui" processor support. Currently gcc can't recognize Zhaoxin CPU(vendor ID "CentaurHauls" and "Shanghai") if user use -march=native option, which is confusing for users. This patch

Re: [PATCH] [x86_64] Zhaoxin lujiazui enablement

On Sun, Mar 27, 2022 at 5:15 PM Uros Bizjak wrote: > On Fri, Mar 25, 2022 at 3:08 AM MayShao wrote: > > > > Hi Uros, > > > > This patch fix Zhaoxin CPU Vendor ID detection problem > > and add Zhaoxin "lujiazui" processor support and tuning. > &

[PATCH] [x86_64] Zhaoxin lujiazui enablement

Hi Uros, This patch fix Zhaoxin CPU Vendor ID detection problem and add Zhaoxin "lujiazui" processor support and tuning. Currently gcc can't recognize Zhaoxin CPU (Vendor ID "CentaurHauls" and "Shanghai") and wrongly identify Zhaoxin "lujiazui" as Intel core2 or i386, which is confusing for