From: Pan Li
This patch would like to add the VLS support vec_set, both INT
and FP are included.
Give sample code as below:
typedef long long vl_t \
__attribute__((vector_size(2 * sizeof (long long;
vl_t init_vl (vl_t v, unsigned index, unsigned value)
{
v[index] = value;
return v;
From: Pan Li
Given below example for VLS mode
void
test (vl_t *u)
{
vl_t t;
long long *p = (long long *)
p[0] = p[1] = 2;
*u = t;
}
The vec_set will simplify the insn to vmv.s.x when index is 0, without
merged operand. That will result in some problems in DCE, aka:
1: 137[DI] = a0
From: Pan Li
This patch would like to allow the VLS mode autovec for the
floating-point binary operation SGNJX.
Give sample code as below:
void
test (float * restrict out, float * restrict in1, float * restrict in2)
{
for (int i = 0; i < 128; i++)
out[i] = in1[i] * copysignf (1.0,
From: Pan Li
When the mode switching from NONE to CALL, we will restore the
frm but lack some check if we have static frm insn in cfun.
This patch would like to fix this by adding static frm insn check.
gcc/ChangeLog:
* PR target/111362
* config/riscv/riscv.cc
From: Pan Li
The struct range is unused, remove it.
gcc/ChangeLog:
* config/riscv/riscv-vector-costs.h (struct range): Removed.
Signed-off-by: Pan Li
---
gcc/config/riscv/riscv-vector-costs.h | 7 ---
1 file changed, 7 deletions(-)
diff --git
From: Pan Li
Update in v3:
* Rewrite comment for overloaded function add.
* Move get_non_overloaded_instance to function_base.
Update in v2:
* Add get_non_overloaded_instance for function instance.
* Fix overload check for policy function.
* Enrich the test cases check.
Original log:
This
From: Pan Li
Update in v2:
* Add get_non_overloaded_instance for function instance.
* Fix overload check for policy function.
* Enrich the test cases check.
Original log:
This patch would like add the framework to support the RVV overloaded
intrinsic API in riscv-xxx-xxx-gcc, like
From: Pan Li
This patch would like add the framework to support the RVV overloaded
intrinsic API in riscv-xxx-xxx-gcc, like riscv-xxx-xxx-g++ did.
However, it almost leverage the hook TARGET_RESOLVE_OVERLOADED_BUILTIN
with below steps.
* Register overloaded functions.
* Add function_resolver
From: Pan Li
Put the test file to the incorrect folder, this patch would like to
fix it.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/intrisinc-vrgatherei16.c: Moved to...
* gcc.target/riscv/rvv/base/intrisinc-vrgatherei16.c: ...here.
Signed-off-by: Pan Li
---
From: Pan Li
This patch would like to allow the VLS mode autovec for the
floating-point binary operation MAX/MIN.
Given below code example:
void test(float * restrict out, float * restrict in1, float * restrict in2)
{
for (int i = 0; i < 128; i++)
out[i] = __builtin_copysignf (in1[i],
From: Pan Li
This patch would like to add FP16 support for the VRGATHEREI16
intrinsic. Aka:
* __riscv_vrgatherei16_vv_f16mf4
* __riscv_vrgatherei16_vv_f16mf4_m
As well as f16mf2 to f16m8 types.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-types.def
From: Pan Li
This patch would like to allow the VLS mode autovec for the
floating-point binary operation MAX/MIN.
Given below code example:
test (float *out, float *in1, float *in2)
{
for (int i = 0; i < 128; i++)
out[i] = in1[i] > in2[i] ? in1[i] : in2[i];
// Or out[i] = fmax
From: Pan Li
This patch would like to allow the VLS mode autovec for the
floating-point binary operation ADD/SUB/MUL/DIV.
Given below code example:
test (float *out, float *in1, float *in2)
{
for (int i = 0; i < 128; i++)
out[i] = in1[i] + in2[i];
}
Before this patch:
test:
csrr
From: Pan Li
There will be one ICE when build vect-multitypes-5.c similar as below:
riscv64-unknown-elf-gcc -O3 \
-march=rv64imafdcv -mabi=lp64d -mcmodel=medlow \
-fdiagnostics-plain-output -flto -ffat-lto-objects \
--param riscv-autovec-preference=scalable -Wno-psabi \
-ftree-vectorize
From: Pan Li
Update in v2:
* Remove control flow check in BB_END.
* Passed x86 bootstrap and regression test.
Original log:
We have EMIT hook in mode switching already, which will insert the
insn before in most cases. However, in some arch like RISC-V, it
requires the additional insn to be
From: Pan Li
There will be a case like below for intrinsic and autovec combination.
vfadd RTZ <- intrinisc static rounding
vfnmadd <- autovec/autovec-opt
The autovec generated vfnmadd should take DYN mode, and the
frm must be restored before the vfnmadd insn. This patch
would like to fix
From: Pan Li
There will be a case like below for intrinsic and autovec combination.
vfadd RTZ <- intrinisc static rounding
vfnmsub <- autovec/autovec-opt
The autovec generated vfnmsub should take DYN mode, and the
frm must be restored before the vfnmsub insn. This patch
would like to fix
From: Pan Li
vfmsac => vfnmacc
vfmsub => vfnmadd
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/autovec.md: Fix typo.
---
gcc/config/riscv/autovec.md | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/autovec.md
From: Pan Li
Fix below typo for the pattern comment.
vfmsac => vfnmsac
vfmsub => vfnmsub
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/autovec.md: Fix typo.
---
gcc/config/riscv/autovec.md | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
From: Pan Li
There will be a case like below for intrinsic and autovec combination.
vfadd RTZ <- intrinisc static rounding
vfmsub <- autovec/autovec-opt
The autovec generated vfmsub should take DYN mode, and the
frm must be restored before the vfmsub insn. This patch
would like to fix
From: Pan Li
There will be a case like below for intrinsic and autovec combination
vfadd RTZ <- intrinisc static rounding
vfmadd <- autovec/autovec-opt
The autovec generated vfmadd should take DYN mode, and the
frm must be restored before the vfmadd insn. This patch
would like to fix
From: Pan Li
Update in v2:
* Added gcc_assert for vx format in binop.
* Passed riscv/rvv.exp test.
Original Log:
As suggested by kito, we will add new frm_opt_type template arg
to the op class, to avoid the duplicated function expand.
Signed-off-by: Pan Li
gcc/ChangeLog:
*
From: Pan Li
We have EMIT hook in mode switching already, which will insert the
insn before in most cases. However, in some arch like RISC-V, it
requires the additional insn to be inserted after when meet a call.
|
| <- EMIT HOOK, insert the insn before.
+---+
|
From: Pan Li
As suggested by kito, we will add new frm_opt_type template arg
to the op class, to avoid the duplicated function expand.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class binop_frm): Removed.
(class
From: Pan Li
This patch would like to support the rounding mode API for the
VFWREDUSUM.VS as the below samples
* __riscv_vfwredusum_vs_f32m1_f64m1_rm
* __riscv_vfwredusum_vs_f32m1_f64m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
From: Pan Li
This patch would like to support the rounding mode API for the
VFWREDOSUM.VS as the below samples
* __riscv_vfwredosum_vs_f32m1_f64m1_rm
* __riscv_vfwredosum_vs_f32m1_f64m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
From: Pan Li
This patch would like to support the rounding mode API for the
VFREDOSUM.VS as the below samples.
* __riscv_vfredosum_vs_f32m1_f32m1_rm
* __riscv_vfredosum_vs_f32m1_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
From: Pan Li
This patch would like to support the rounding mode API for the
VFREDUSUM.VS as the below samples.
* __riscv_vfredusum_vs_f32m1_f32m1_rm
* __riscv_vfredusum_vs_f32m1_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
From: Pan Li
This patch would like to support the rounding mode API for the
VFNCVT.F.{X|XU|F}.W as the below samples.
* __riscv_vfncvt_f_x_w_f32m1_rm
* __riscv_vfncvt_f_x_w_f32m1_rm_m
* __riscv_vfncvt_f_xu_w_f32m1_rm
* __riscv_vfncvt_f_xu_w_f32m1_rm_m
* __riscv_vfncvt_f_f_w_f32m1_rm
*
From: Pan Li
This patch would like to support the rounding mode API for the
VFNCVT.XU.F.W as the below samples.
* __riscv_vfncvt_xu_f_w_u16mf2_rm
* __riscv_vfncvt_xu_f_w_u16mf2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
From: Pan Li
This patch would like to support the rounding mode API for the
VFNCVT.X.F.W as the below samples.
* __riscv_vfncvt_x_f_w_i16mf2_rm
* __riscv_vfncvt_x_f_w_i16mf2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class
From: Pan Li
In some build option combination, the default value may result in
below error. This patch would like to fix it by passing a explict
argument.
riscv-vector-builtins-bases.cc:2495:24: error: invalid use of template-name \
‘riscv_vector::vfcvt_f’ without an argument list
From: Pan Li
This patch would like to support the rounding mode API for the
VFWCVT.X.F.V as the below samples.
* __riscv_vfwcvt_xu_f_v_u64m2_rm
* __riscv_vfwcvt_xu_f_v_u64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(BASE): New
From: Pan Li
This patch would like to support the rounding mode API for the
VFWCVT.X.F.V as the below samples.
* __riscv_vfwcvt_x_f_v_i64m2_rm
* __riscv_vfwcvt_x_f_v_i64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(BASE): New
From: Pan Li
This patch would like to support the rounding mode API for the
VFCVT.F.X.V and VFCVT.F.XU.V as the below samples.
* __riscv_vfcvt_f_x_v_f32m1_rm
* __riscv_vfcvt_f_x_v_f32m1_rm_m
* __riscv_vfcvt_f_xu_v_f32m1_rm
* __riscv_vfcvt_f_xu_v_f32m1_rm_m
Signed-off-by: Pan Li
From: Pan Li
This patch would like to support the rounding mode API for the
VFCVT.XU.F.V as the below samples.
* __riscv_vfcvt_xu_f_v_u32m1_rm
* __riscv_vfcvt_xu_f_v_u32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(BASE): New
From: Pan Li
This patch would like to support the rounding mode API for the
VFCVT.X.F.V as the below samples.
* __riscv_vfcvt_x_f_v_i32m1_rm
* __riscv_vfcvt_x_f_v_i32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(enum
From: Pan Li
This patch would like to support the rounding mode API for the
VFWCVT.X.F.V as the below samples.
* __riscv_vfwcvt_xu_f_v_u64m2_rm
* __riscv_vfwcvt_xu_f_v_u64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
From: Pan Li
This patch would like to support the rounding mode API for the
VFWCVT.X.F.V as the below samples.
* __riscv_vfwcvt_x_f_v_i64m2_rm
* __riscv_vfwcvt_x_f_v_i64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class
From: Pan Li
This patch would like to support the rounding mode API for the
VFCVT.F.X.V and VFCVT.F.XU.V as the below samples.
* __riscv_vfcvt_f_x_v_f32m1_rm
* __riscv_vfcvt_f_x_v_f32m1_rm_m
* __riscv_vfcvt_f_xu_v_f32m1_rm
* __riscv_vfcvt_f_xu_v_f32m1_rm_m
Signed-off-by: Pan Li
From: Pan Li
This patch would like to support the rounding mode API for the
VFCVT.XU.F.V as the below samples.
* __riscv_vfcvt_xu_f_v_u32m1_rm
* __riscv_vfcvt_xu_f_v_u32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
From: Pan Li
This patch would like to support the rounding mode API for the
VFCVT.X.F.V as the below samples.
* __riscv_vfcvt_x_f_v_i32m1_rm
* __riscv_vfcvt_x_f_v_i32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class
From: Pan Li
Update in v2:
1. Remove the template of vfrec7 frm class.
2. Update the vfrec7_frm_obj declaration.
Original logs:
This patch would like to support the rounding mode API for the
VFREC7 as the below samples.
* __riscv_vfrec7_v_f32m1_rm
* __riscv_vfrec7_v_f32m1_rm_m
From: Pan Li
This patch would like to support the rounding mode API for the
VFREC7 as the below samples.
* __riscv_vfrec7_v_f32m1_rm
* __riscv_vfrec7_v_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfrec7_frm): New class
From: Pan Li
This patch would like to support the rounding mode API for the
VFSQRT as the below samples.
* __riscv_vfsqrt_v_f32m1_rm
* __riscv_vfsqrt_v_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class unop_frm): New class
From: Pan Li
This patch would like to support the rounding mode API for the
VFWNMSAC as the below samples.
* __riscv_vfwnmsac_vv_f64m2_rm
* __riscv_vfwnmsac_vv_f64m2_rm_m
* __riscv_vfwnmsac_vf_f64m2_rm
* __riscv_vfwnmsac_vf_f64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
*
From: Pan Li
This patch would like to support the rounding mode API for the
VFWMSAC as the below samples.
* __riscv_vfwmsac_vv_f64m2_rm
* __riscv_vfwmsac_vv_f64m2_rm_m
* __riscv_vfwmsac_vf_f64m2_rm
* __riscv_vfwmsac_vf_f64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
*
From: Pan Li
This patch would like to support the rounding mode API for the
VFWNMACC as the below samples.
* __riscv_vfwnmacc_vv_f64m2_rm
* __riscv_vfwnmacc_vv_f64m2_rm_m
* __riscv_vfwnmacc_vf_f64m2_rm
* __riscv_vfwnmacc_vf_f64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
*
From: Pan Li
This patch would like to support the rounding mode API for the
VFWMACC as the below samples.
* __riscv_vfwmacc_vv_f64m2_rm
* __riscv_vfwmacc_vv_f64m2_rm_m
* __riscv_vfwmacc_vf_f64m2_rm
* __riscv_vfwmacc_vf_f64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
*
From: Pan Li
In same cases, like gcc/testsuite/gcc.dg/pr78148.c in RISC-V, there will
be only 1 operand when SET_SRC in create_pre_exit. For example as below.
(insn 13 9 14 2 (clobber (reg/i:TI 10 a0))
"gcc/testsuite/gcc.dg/pr78148.c":24:1 -1
(expr_list:REG_UNUSED (reg/i:TI 10 a0)
From: Pan Li
This patch would like to support the rounding mode API for the
VFNMSUB as the below samples.
* __riscv_vfnmsub_vv_f32m1_rm
* __riscv_vfnmsub_vv_f32m1_rm_m
* __riscv_vfnmsub_vf_f32m1_rm
* __riscv_vfnmsub_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
*
From: Pan Li
This patch would like to support the rounding mode API for the
VFMSUB as the below samples.
* __riscv_vfmsub_vv_f32m1_rm
* __riscv_vfmsub_vv_f32m1_rm_m
* __riscv_vfmsub_vf_f32m1_rm
* __riscv_vfmsub_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
*
From: Pan Li
This patch would like to support the rounding mode API for the
VFNMADD as the below samples.
* __riscv_vfnmadd_vv_f32m1_rm
* __riscv_vfnmadd_vv_f32m1_rm_m
* __riscv_vfnmadd_vf_f32m1_rm
* __riscv_vfnmadd_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
*
From: Pan Li
This patch would like to support the rounding mode API for the
VFMADD as the below samples.
* __riscv_vfmadd_vv_f32m1_rm
* __riscv_vfmadd_vv_f32m1_rm_m
* __riscv_vfmadd_vf_f32m1_rm
* __riscv_vfmadd_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
*
From: Pan Li
This patch would like to support the rounding mode API for the
VFNMSAC for the below samples.
* __riscv_vfnmsac_vv_f32m1_rm
* __riscv_vfnmsac_vv_f32m1_rm_m
* __riscv_vfnmsac_vf_f32m1_rm
* __riscv_vfnmsac_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
*
From: Pan Li
This patch would like to support the rounding mode API for the
VFMSAC for the below samples.
* __riscv_vfmsac_vv_f32m1_rm
* __riscv_vfmsac_vv_f32m1_rm_m
* __riscv_vfmsac_vf_f32m1_rm
* __riscv_vfmsac_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
(class vfmsac_frm):
From: Pan Li
This patch would like to support the rounding mode API for the
VFNMACC for the below samples.
* __riscv_vfnmacc_vv_f32m1_rm
* __riscv_vfnmacc_vv_f32m1_rm_m
* __riscv_vfnmacc_vf_f32m1_rm
* __riscv_vfnmacc_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
*
From: Pan Li
This patch would like to support the rounding mode API for the
VFMACC for the below samples.
* __riscv_vfmacc_vv_f32m1_rm
* __riscv_vfmacc_vv_f32m1_rm_m
* __riscv_vfmacc_vf_f32m1_rm
* __riscv_vfmacc_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
*
From: Pan Li
The frm_mode attr has some assumptions for each define insn as below.
1. The define insn has at least 9 operands.
2. The operands[9] must be frm reg.
3. The operands[9] must be const int.
Actually, the frm operand can be operands[8], operands[9] or
operands[10], and not all the
From: Pan Li
In same cases, like gcc/testsuite/gcc.dg/pr78148.c in RISC-V, there will
be only 1 operand when SET_SRC in create_pre_exit. For example as below.
(insn 13 9 14 2 (clobber (reg/i:TI 10 a0))
"gcc/testsuite/gcc.dg/pr78148.c":24:1 -1
(expr_list:REG_UNUSED (reg/i:TI 10 a0)
From: Pan Li
The frm_mode attr has some assumptions for each define insn as below.
1. The define insn has at least 9 operands.
2. The operands[9] must be frm reg.
3. The operands[9] must be const int.
Actually, the frm operand can be operands[8], operands[9] or
operands[10], and not all the
From: Pan Li
In same cases, like gcc/testsuite/gcc.dg/pr78148.c in RISC-V, there will
be only 1 operand when SET_SRC in create_pre_exit. For example as below.
(insn 13 9 14 2 (clobber (reg/i:TI 10 a0))
"gcc/testsuite/gcc.dg/pr78148.c":24:1 -1
(expr_list:REG_UNUSED (reg/i:TI 10 a0)
From: Pan Li
In same cases, like gcc/testsuite/gcc.dg/pr78148.c in RISC-V, there will
be only 1 operand when SET_SRC in create_pre_exit. For example as below.
(insn 13 9 14 2 (clobber (reg/i:TI 10 a0))
"gcc/testsuite/gcc.dg/pr78148.c":24:1 -1
(expr_list:REG_UNUSED (reg/i:TI 10 a0)
From: Pan Li
The frm_mode attr has some assumptions for each define insn as below.
1. The define insn has at least 9 operands.
2. The operands[9] must be frm reg.
3. The operands[9] must be const int.
Actually, the frm operand can be operands[8], operands[9] or
operands[10], and not all the
From: Pan Li
This patch would like to support the rounding mode API for the
VFMADD as the below samples.
* __riscv_vfmadd_vv_f32m1_rm
* __riscv_vfmadd_vv_f32m1_rm_m
* __riscv_vfmadd_vf_f32m1_rm
* __riscv_vfmadd_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
*
From: Pan Li
This patch would like to support the rounding mode API for the
VFNMSAC for the below samples.
* __riscv_vfnmsac_vv_f32m1_rm
* __riscv_vfnmsac_vv_f32m1_rm_m
* __riscv_vfnmsac_vf_f32m1_rm
* __riscv_vfnmsac_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
*
From: Pan Li
This patch would like to support the rounding mode API for the
VFMSAC for the below samples.
* __riscv_vfmsac_vv_f32m1_rm
* __riscv_vfmsac_vv_f32m1_rm_m
* __riscv_vfmsac_vf_f32m1_rm
* __riscv_vfmsac_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
*
From: Pan Li
This patch would like to support the rounding mode API for the
VFNMACC for the below samples.
* __riscv_vfnmacc_vv_f32m1_rm
* __riscv_vfnmacc_vv_f32m1_rm_m
* __riscv_vfnmacc_vf_f32m1_rm
* __riscv_vfnmacc_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
*
From: Pan Li
This patch would like to support the rounding mode API for the
VFMACC for the below samples.
* __riscv_vfmacc_vv_f32m1_rm
* __riscv_vfmacc_vv_f32m1_rm_m
* __riscv_vfmacc_vf_f32m1_rm
* __riscv_vfmacc_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
*
From: Pan Li
The previous patch missed the vfsub comment for binop_frm, this
patch would like to fix this.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Add vfsub.
---
gcc/config/riscv/riscv-vector-builtins-bases.cc | 1 +
1 file changed, 1
From: Pan Li
This patch would like to support the rounding mode API for the
VFWMUL for the below samples.
* __riscv_vfwmul_vv_f64m2_rm
* __riscv_vfwmul_vv_f64m2_rm_m
* __riscv_vfwmul_vf_f64m2_rm
* __riscv_vfwmul_vf_f64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
*
From: Pan Li
This patch would like to support the rounding mode API for the
VFDIV and VFRDIV for the below samples.
* __riscv_vfdiv_vv_f32m1_rm
* __riscv_vfdiv_vv_f32m1_rm_m
* __riscv_vfdiv_vf_f32m1_rm
* __riscv_vfdiv_vf_f32m1_rm_m
* __riscv_vfrdiv_vf_f32m1_rm
* __riscv_vfrdiv_vf_f32m1_rm_m
From: Pan Li
Update in v2:
* Sync with upstream for the vfmul duplicated declaration.
Original log:
This patch would like to support the rounding mode API for the VFMUL
for the below samples.
* __riscv_vfmul_vv_f32m1_rm
* __riscv_vfmul_vv_f32m1_rm_m
* __riscv_vfmul_vf_f32m1_rm
*
From: Pan Li
This patch would like to remove the redudant declaration.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.h: Remove
redudant declaration.
---
gcc/config/riscv/riscv-vector-builtins-bases.h | 1 -
1 file changed, 1 deletion(-)
From: Pan Li
This patch would like to support the rounding mode API for the VFMUL
for the below samples.
* __riscv_vfmul_vv_f32m1_rm
* __riscv_vfmul_vv_f32m1_rm_m
* __riscv_vfmul_vf_f32m1_rm
* __riscv_vfmul_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
*
From: Pan Li
This patch would like to support the rounding mode API for the VFWSUB
for the below samples.
* __riscv_vfwsub_vv_f64m2_rm
* __riscv_vfwsub_vv_f64m2_rm_m
* __riscv_vfwsub_vf_f64m2_rm
* __riscv_vfwsub_vf_f64m2_rm_m
* __riscv_vfwsub_wv_f64m2_rm
*
From: Pan Li
This patch would like to enhance the vfsub/vfrsub rounding API test for
below 2 purposes.
* The non-rm API has no frm related insn generated.
* The rm API has the frm backup/restore/set insn generated.
Signed-off-by: Pan Li
gcc/testsuite/ChangeLog:
*
From: Pan Li
Update in v2:
1. Add vfwalu type to frm_mode.
2. Enhance the test cases for frm.
Original log:
This patch would like to support the rounding mode API for the VFWADD
VFSUB and VFRSUB as below samples.
* __riscv_vfwadd_vv_f64m2_rm
* __riscv_vfwadd_vv_f64m2_rm_m
*
From: Pan Li
This patch would like to support the rounding mode API for the VFWADD
VFSUB and VFRSUB as below samples.
* __riscv_vfwadd_vv_f64m2_rm
* __riscv_vfwadd_vv_f64m2_rm_m
* __riscv_vfwadd_vf_f64m2_rm
* __riscv_vfwadd_vf_f64m2_rm_m
* __riscv_vfwadd_wv_f64m2_rm
*
From: Pan Li
This patch would like to support the rounding mode API for both the
VFSUB and VFRSUB as below samples.
* __riscv_vfsub_vv_f32m1_rm
* __riscv_vfsub_vv_f32m1_rm_m
* __riscv_vfsub_vf_f32m1_rm
* __riscv_vfsub_vf_f32m1_rm_m
* __riscv_vfrsub_vf_f32m1_rm
* __riscv_vfrsub_vf_f32m1_rm_m
From: Pan Li
According to below RVV intrinsic doc, the RVV floating-point intrinsic name
with rounding mode should be:
_rm_m
instead of:
_m_rm
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226
This patch fix this naming sequence issue and adjust the test cases.
Signed-off-by: Pan
From: Pan Li
Update in PATCH v8:
1. Emit non-abnormal backup insn to edge.
2. Fix _after return when call.
3. Refine some run tests.
4. Cleanup code.
Original commit logs:
In basic dynamic rounding mode, we simply ignore call instructions and
we would like to take care of call in this PATCH.
From: Pan Li
According to below RVV doc, the related intrinsic is not longer needed.
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/249
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv_vector.h (enum RVV_CSR): Removed.
(vread_csr): Ditto.
From: Pan Li
Update in PATCH v7:
1. Take previous/next_nonnote_nondebug_insn_bb for seeking the insn.
2. Splitting the function in detection and emit when needed.
Original commit logs:
In basic dynamic rounding mode, we simply ignore call instructions and
we would like to take care of call in
From: Pan Li
In basic dynamic rounding mode, we simply ignore call instructions and
we would like to take care of call in this PATCH.
During the call, the frm may be updated or keep as is. Thus, we must
make sure at least 2 things.
1. The static frm before call should not pollute the frm value
From: Pan Li
According to the spec, dyn rounding mode is invalid for RVV
floating-point, this patch would like to fix this.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-shapes.cc
(struct alu_frm_def): Take range check.
gcc/testsuite/ChangeLog:
From: Pan Li
In basic dynamic rounding mode, we simply ignore call instructions and
we would like to take care of call in this PATCH.
During the call, the frm may be updated or keep as is. Thus, we must
make sure at least 2 things.
1. The static frm before call should not pollute the frm value
From: Pan Li
There are 2 of the RVV reduction pattern mask operand takes
vector_merge_operand instead of vector_mask_operand by mistake. This
patch would like to fix this.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/vector.md: Fix incorrect match_operand.
From: Pan Li
In basic dynamic rounding mode, we simply ignore call instructions and
we would like to take care of call in this PATCH.
During the call, the frm may be updated or keep as is. Thus, we must
make sure at least 2 things.
1. The static frm before call should not pollute the frm value
From: Pan Li
There are some format-unaligned pattern in vector.md, this patch
would like to align the format for these patterns.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/vector.md: Align pattern format.
---
gcc/config/riscv/vector.md | 850
From: Pan Li
In basic dynamic rounding mode, we simply ignore call instructions and
we would like to take care of call in this PATCH.
During the call, the frm may be updated or keep as is. Thus, we must
make sure at least 2 things.
1. The static frm before call should not pollute the frm value
From: Pan Li
In basic dynamic rounding mode, we simply ignore call instructions and
we would like to take care of call in this PATCH.
During the call, the frm may be updated or keep as is. Thus, we must
make sure at least 2 things.
1. The static frm before call should not pollute the frm value
From: Pan Li
In basic dynamic rounding mode, we simply ignore call instructions and
we would like to take care of call in this PATCH.
During the call, the frm may be updated or keep as is. Thus, we must
make sure at least 2 things.
1. The static frm before call should not pollute the frm value
From: Pan Li
Refine the run test case to avoid interactive checking in RV32, by
separating each checks in different functions.
Signed-off-by: Pan Li
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-run-1.c: Fix run failure.
---
From: Ju-Zhe Zhong
This patch comes from part of below change, which locate one bug of rvv
vsetvel pass when auto-vectorization.
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/624523.html
Unforunately, It is not easy to reproduce this bug by intrinsic APIs
but it is worth to backport to
From: Pan Li
Refine the run test case to avoid interactive checking in RV32, by
separating each checks in different functions.
Signed-off-by: Pan Li
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-run-1.c: Fix failure
on RV32.
---
From: Pan Li
This patch would like to support the basic floating-point dynamic
rounding modes for the RVV.
We implement the dynamic rounding mode by below steps.
1. Set entry to DYN and exit to DYN_EXIT.
2. Add one rtl variable into machine_function for backup/restore.
3. Backup frm value when
From: Pan Li
Add more test cases include both the asm check and run for RVV FRM.
Signed-off-by: Pan Li
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-insert-10.c: New test.
* gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: New test.
*
From: Pan Li
When investigate the FRM dynmaic rounding mode, we find the global
unknown status is quite different between the fixed-point and
floating-point. Thus, we separate the unknown function with extracting
some inner common functions.
We will also prepare more test cases in another
From: Pan Li
Add more test cases include both the asm check and run for RVV FRM.
Signed-off-by: Pan Li
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-insert-10.c: New test.
* gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: New test.
*
1 - 100 of 216 matches
Mail list logo
