On Tue, 11 Jun 2024 at 15:37, Jeff Law wrote:
>
>
>
> On 6/11/24 1:22 AM, Richard Biener wrote:
>
> >> Absolutely. But forwarding from a smaller store to a wider load is
> >> painful
> >> from a hardware standpoint and if we can avoid it from a codegen
> >> standpoint,
> >> we should.
> >
> >
On Mon, 10 Jun 2024 at 20:03, Jeff Law wrote:
>
>
>
> On 6/10/24 1:55 AM, Manolis Tsamis wrote:
>
> >>
> > There was an older submission of a load-pair specific pass but this is
> > a complete reimplementation and indeed significantly more general.
> > Apart from being target independant, it
On Fri, 24 May 2024 at 13:02, Richard Biener wrote:
>
> On Fri, 24 May 2024, Manolis Tsamis wrote:
>
> > The match.pd patterns to merge two vector permutes into one fail when a
> > potentially no-op view convert expressions is between the two permutes.
> > This change lifts this restriction.
>
>
https://gcc.gnu.org/g:6d6f324bda1ccb51cd43ff9d4d017eb71bb2d690
commit r15-818-g6d6f324bda1ccb51cd43ff9d4d017eb71bb2d690
Author: Manolis Tsamis
Date: Wed Nov 1 12:27:28 2023 +0100
MATCH: Look through VIEW_CONVERT when folding VEC_PERM_EXPRs.
The match.pd patterns to merge two
On Thu, 23 May 2024 at 18:18, Andrew Pinski wrote:
>
> On Thu, May 23, 2024 at 8:01 AM Manolis Tsamis
> wrote:
> >
> > This pass detects cases of expensive store forwarding and tries to avoid
> > them
> > by reordering the stores and using suitable bit insertion sequences.
> > For example it
On Sat 6. Apr 2024 at 06:52, Jeff Law wrote:
>
>
> On 3/27/24 4:55 AM, Philipp Tomsich wrote:
> > Jeff,
> >
> > just a heads-up that that trunk (i.e., the soon-to-be GCC14) still
> > generates the suboptimal sequence:
> >https://godbolt.org/z/K9YYEPs
Jeff,
just a heads-up that that trunk (i.e., the soon-to-be GCC14) still
generates the suboptimal sequence:
https://godbolt.org/z/K9YYEPsvY
Thanks,
Philipp.
On Mon, 21 Nov 2022 at 18:00, Philipp Tomsich wrote:
>
> On Sun, 20 Nov 2022 at 17:38, Jeff Law wrote:
> >
> >
&g
Applied to master, thanks!
--Philipp.
On Wed, 24 Jan 2024 at 12:43, Richard Sandiford
wrote:
> Manos Anagnostakis writes:
> > The current ldp/stp policy framework implementation was missing cases,
> where
> > the memory operands were reversed. Therefore the call to the framework
> function
> >
* config/aarch64/aarch64-store-forwarding.cc: New file.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/aarch64/ldp_ssll_no_overlap_address.c: New test.
> > * gcc.target/aarch64/ldp_ssll_no_overlap_offset.c: New test.
> > * gc
Applied to master, thanks!
Philipp.
On Tue, 28 Nov 2023 at 12:57, Richard Sandiford
wrote:
>
> Philipp Tomsich writes:
> > On Tue, 28 Nov 2023 at 12:21, Richard Sandiford
> > wrote:
> >>
> >> Philipp Tomsich writes:
> >> > Th
These build-ins are used internally for the
TARGET_ATOMIC_ASSIGN_EXPAND_FENV expansion (and therefore can not be
removed):
/* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
void
riscv_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
{
if (!(TARGET_HARD_FLOAT || TARGET_ZFINX))
On Tue, 28 Nov 2023 at 20:31, Palmer Dabbelt wrote:
>
> On Wed, 22 Nov 2023 14:27:50 PST (-0800), jeffreya...@gmail.com wrote:
> > ...
>
> [Trimming everything else, as this is a big change. I'm also making it
> a new subject/thread, so folks can see.]
>
> > More generally, I think I need to
On Tue, 28 Nov 2023 at 12:21, Richard Sandiford
wrote:
>
> Philipp Tomsich writes:
> > This patch adds initial support for Ampere-1B core.
> >
> > The Ampere-1B core implements ARMv8.7 with the following (compiler
> > visible) extensions:
> > - CSS
Applied to master, thanks!
Philipp,
On Thu, 23 Nov 2023 at 04:48, Jeff Law wrote:
>
>
>
> On 11/21/23 11:04, Manolis Tsamis wrote:
> > This code used to handle SUBREG for register replacement when ifcvt was
> > doing
> > the replacements manually. This special handling is not needed anymore
>
/aarch64/tuning_models/ampere1b.h: New file.
Signed-off-by: Philipp Tomsich
---
Changes in v2:
- moved ampere1b model to a separated file
- regenerated aarch64-tune.md after rebase
gcc/config/aarch64/aarch64-cores.def| 1 +
gcc/config/aarch64/aarch64-cost-tables.h| 107
On Fri, 17 Nov 2023 at 22:47, Jeff Law wrote:
>
>
>
> On 11/17/23 04:39, juzhe.zh...@rivai.ai wrote:
> > 90% theadvector extension reusing current RVV 1.0 instructions patterns:
> > Just change ASM, For example:
> >
> > @@ -2923,7 +2923,7 @@ (define_insn "*pred_mulh_scalar"
> >
:
>
>
>
> > -Original Message-
> > From: Richard Earnshaw
> > Sent: Thursday, November 16, 2023 8:53 AM
> > To: Philipp Tomsich ; gcc-patches@gcc.gnu.org
> > Cc: Kyrylo Tkachov
> > Subject: Re: [PATCH] aarch64: costs: update for TARGET_CSSC
> >
>
: Document -mcpu=ampere1b
Signed-off-by: Philipp Tomsich
---
gcc/config/aarch64/aarch64-cores.def | 1 +
gcc/config/aarch64/aarch64-cost-tables.h | 107 +++
gcc/config/aarch64/aarch64-tune.md | 2 +-
gcc/config/aarch64/aarch64.cc| 89
instruction.
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_rtx_costs): Support
idioms matching to CSSC instructions, if target CSSC is
present
Signed-off-by: Philipp Tomsich
---
gcc/config/aarch64/aarch64.cc | 34 --
1 file changed, 24
Applied to master. Thanks!
--Philipp.
On Fri, 29 Sept 2023 at 12:34, Richard Sandiford
wrote:
>
> Manos Anagnostakis writes:
> > Improves on: 834fc2bf
> >
> > This improves the code structure of the ldp-stp policies
> > patch introduced in 834fc2bf
> >
> > Bootstrapped and regtested on
Manos,
Please submit a follow-on patch implementing the requested
improvements of the code structure (as this reduces the maintenance
burden).
Thanks,
Philipp.
On Thu, 28 Sept 2023 at 15:33, Manos Anagnostakis
wrote:
>
> Hey Richard,
>
> Thanks for taking the time to review this, but it has
rg
> > Cc: Kyrylo Tkachov ; Tamar Christina
> > ; Philipp Tomsich ;
> > Manos Anagnostakis
> > Subject: [PATCH v4] aarch64: Fine-grained policies to control ldp-stp
> > formation.
> >
> > This patch implements the following TODO in gcc/config/aarch64
On Mon, 25 Sept 2023 at 21:54, Andrew Pinski wrote:
>
> On Mon, Sep 25, 2023 at 12:50 PM Manos Anagnostakis
> wrote:
> >
> > This patch implements the following TODO in gcc/config/aarch64/aarch64.cc
> > to provide the requested behaviour for handling ldp and stp:
> >
> > /* Allow the tuning
Applied to master. Thanks!
Philipp.
On Wed, 6 Sept 2023 at 18:07, Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> This patch implements the expansion of the strlen builtin for RV32/RV64
> for xlen-aligned aligned strings if Zbb or XTheadBb instructions are
> available.
> The
Applied to master. Thanks!
Philipp.
On Tue, 12 Sept 2023 at 05:34, Jeff Law wrote:
>
>
>
> On 9/6/23 10:07, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > This patch implements expansions for the cmpstrsi and cmpstrnsi
> > builtins for RV32/RV64 for xlen-aligned strings if Zbb or
Applied to master. Thanks!
Philipp.
On Fri, 8 Sept 2023 at 14:17, Kito Cheng wrote:
> LGTM
>
> Christoph Muellner 於 2023年9月8日 週五，14:00寫道：
>
>> From: Christoph Müllner
>>
>> Recently three SPEC CPU 2017 benchmarks broke when using xtheadbb:
>> * 500.perlbench_r
>> * 525.x264_r
>> * 557.xz_r
>>
Applied to master. Thanks!
Philipp.
On Fri, 8 Sept 2023 at 10:13, Kito Cheng wrote:
> LGTM
>
> Christoph Muellner 於 2023年9月8日 週五 14:16 寫道：
>
>> From: Christoph Müllner
>>
>> The mode attribute of an extension pattern is usually set to the target
>> type.
>> Let's follow this convention
Committed as 'obvious' to master. Thanks!
Philipp.
On Fri, 8 Sept 2023 at 08:53, Christoph Muellner <
christoph.muell...@vrull.eu> wrote:
> From: Christoph Müllner
>
> We currently have two identical zero_extendhi2 patterns:
> * '*zero_extendhi2_zbb'
> * '*zero_extendhi2_bitmanip'
>
> This
Committed as "obvious" to master.
--Philipp.
On Wed, 6 Sept 2023 at 12:04, Christoph Muellner <
christoph.muell...@vrull.eu> wrote:
> From: Christoph Müllner
>
> The test was introduced recently and tests a RV64-only feature.
> However, when testing an RV32 compiler, the test gets executed as
Applied to master. Thanks!
Philipp.
On Tue, 5 Sept 2023 at 23:57, Jeff Law wrote:
>
>
> On 9/5/23 15:15, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > Some constants can be built up using LI+RORI instructions.
> > The current implementation requires one of the upper 32-bits
> >
Applied to master. Thanks!
Philipp.
On Tue, 5 Sept 2023 at 18:10, Jeff Law wrote:
>
>
> On 9/5/23 09:42, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > Some constants can be built up using rotate-right instructions.
> > The code that enables this can be found in
Applied to master. Thanks!
Philipp.
On Tue, 5 Sept 2023 at 08:22, Jeff Law wrote:
>
>
> On 9/1/23 04:20, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > Recently, these xtheadcondmov tests regressed with -Oz:
> > * FAIL: gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c
> > * FAIL:
On Wed, 16 Aug 2023 at 21:10, Alexander Monakov wrote:
>
>
> On Tue, 15 Aug 2023, Jeff Law wrote:
>
> > Because if the compiler can optimize it automatically, then the projects
> > have
> > to do literally nothing to take advantage of it. They just compile normally
> > and their bitwise CRC
On Wed, 16 Aug 2023 at 03:27, Jeff Law via Gcc-patches
wrote:
>
>
>
> On 8/9/23 20:25, Tsukasa OI wrote:
> > From: Tsukasa OI
> >
> > The "pause" RISC-V hint instruction requires the 'Zihintpause' extension
> > (in the assembler). However, GCC emits "pause" unconditionally, making
> > an
On Sat, 12 Aug 2023 at 01:31, Jeff Law via Gcc-patches
wrote:
>
>
>
> On 8/9/23 16:39, Tsukasa OI wrote:
> > On 2023/08/10 5:05, Jeff Law wrote:
>
> >> I'd tend to think we do not want to expose the intrinsic unless the
> >> right extensions are enabled -- even though the encoding is a no-op and
Applied to master, thanks!
--Philipp.
On Mon, 7 Aug 2023 at 19:20, Jeff Law wrote:
>
>
>
> On 8/7/23 05:31, Manolis Tsamis wrote:
> > The stack pointer propagation fix 736f8fd3 turned out to be more restrictive
> > than needed by rejecting propagation of the stack pointer when REG_POINTER
> >
Very helpful! Looks as if regprop for stack_pointer is now either too
conservative — or one of our patches is missing in everyone's test
setup; we'll take a closer look.
On Wed, 2 Aug 2023 at 01:03, Vineet Gupta wrote:
>
>
>
> On 8/1/23 15:07, Philipp Tomsich wrote:
> &g
+Manolis Tsamis
On Tue, 1 Aug 2023 at 23:56, Jeff Law via Gcc-patches
wrote:
>
>
>
> On 8/1/23 13:14, Vineet Gupta wrote:
>
> >
> > I have some numbers for f-m-o v3 vs this. Attached here (vs. inline to
> > avoid the Thunderbird mangling the test formatting)
> Thanks. Of particular importance
On Fri, 21 Jul 2023 at 19:56, Vineet Gupta wrote:
>
> DF +0.0 is bitwise all zeros so int x0 store to mem can be used to optimize
> it.
>
> void zd(double *) { *d = 0.0; }
>
> currently:
>
> | fmv.d.x fa5,zero
> | fsd fa5,0(a0)
> | ret
>
> With patch
>
> | sd zero,0(a0)
> | ret
> This
Thanks, applied to trunk!
Philipp.
On Wed, 12 Jul 2023 at 16:08, Jeff Law wrote:
>
>
> On 7/12/23 08:07, Philipp Tomsich wrote:
> >
> >
> > On Wed, 12 Jul 2023 at 16:05, Jeff Law > <mailto:jeffreya...@gmail.com>> wrote:
> >
> >
&g
On Wed, 12 Jul 2023 at 16:05, Jeff Law wrote:
>
>
> On 7/12/23 06:48, Christoph Müllner wrote:
> > On Wed, Jul 12, 2023 at 4:05 AM Jeff Law wrote:
> >>
> >>
> >>
> >> On 7/10/23 22:44, Christoph Muellner wrote:
> >>> From: Christoph Müllner
> >>>
> >>> Recently, two identical XTheadCondMov
Awesome, thanks!
On Wed, 12 Jul 2023 at 09:18, Kito Cheng wrote:
> Yeah, I've applied patches on my local tree and running the testsuite.
>
> On Wed, Jul 12, 2023 at 3:11 PM Philipp Tomsich
> wrote:
> >
> > Looks like I missed the OK on this one.
> > I can pic
Looks like I missed the OK on this one.
I can pick it up today, unless you Kito already has it in flight?
Thanks,
Philipp.
On Tue, 11 Jul 2023 at 17:51, Kito Cheng wrote:
> Hi Christoph:
>
> Ooops, I thought Philipp will push those patches, does here any other
> patches got approved but not
Jakub,
it looks like you did a lot of work on reassoc in the past — could you
have a quick look and comment?
Thanks,
Philipp.
On Tue, 11 Jul 2023 at 04:59, Di Zhao OS wrote:
>
> Attached is an updated version of the patch.
>
> Based on Philipp's review, some changes:
>
> 1. Defined new enum
On Fri, 7 Jul 2023 at 10:28, Di Zhao OS via Gcc-patches
wrote:
>
> Update the patch so it can apply.
>
> Tested on spec2017 fprate cases again. With option "-funroll-loops -Ofast
> -flto",
> the improvements of 1-copy run are:
>
> Ampere1:
> 508.namd_r 4.26%
> 510.parest_r2.55%
Thanks, applied to master.
--Philipp.
On Mon, 3 Jul 2023 at 15:42, Kito Cheng wrote:
> Thanks, LGTM :)
>
> Christoph Muellner 於 2023年7月3日 週一，19:08寫道：
>
>> From: Christoph Müllner
>>
>> This series adds basic support for the vector crypto extensions:
>> * Zvbb
>> * Zvbc
>> * Zvkg
>> * Zvkned
>>
/22/23 05:11, Philipp Tomsich wrote:
> > From: Manolis Tsamis
> >
> > Fixes: 6a2e8dcbbd4bab3
> >
> > Propagation for the stack pointer in regcprop was enabled in
> > 6a2e8dcbbd4bab3, but set ORIGINAL_REGNO/REG_ATTRS/REG_POINTER for
> > stack_pointer_r
mode.
(maybe_copy_reg_attrs): New function.
(find_oldest_value_reg): Use maybe_copy_reg_attrs.
(copyprop_hardreg_forward_1): Ditto.
gcc/testsuite/ChangeLog:
* g++.dg/torture/pr110308.C: New test.
Signed-off-by: Manolis Tsamis
Signed-off-by: Philipp Tomsich
Richard,
OK for backport to GCC-13?
Thanks,
Philipp.
On Thu, 22 Jun 2023 at 16:18, Richard Sandiford via Gcc-patches
wrote:
>
> Di Zhao OS via Gcc-patches writes:
> > This patch enables reassociation of floating-point additions on ampere1.
> > This brings about 1% overall benefit on spec2017
.
(find_oldest_value_reg): Special handling of stack_pointer_rtx.
(copyprop_hardreg_forward_1): Ditto.
gcc/testsuite/ChangeLog:
* g++.dg/torture/pr110308.C: New test.
Signed-off-by: Manolis Tsamis
Signed-off-by: Philipp Tomsich
---
This addresses both the PRs (110308
This should be covered by PR110308 (proposed fix attached there) and PR110313.
Our bootstrap runs are still in progress to confirm.
On Thu, 22 Jun 2023 at 09:40, Richard Biener wrote:
>
> On Thu, Jun 22, 2023 at 1:42 AM Thiago Jung Bauermann
> wrote:
> >
> >
> > Hello,
> >
> > Jeff Law
Rebased, retested, and applied to trunk. Thanks!
--Philipp.
On Thu, 8 Jun 2023 at 00:18, Jeff Law wrote:
>
>
>
> On 5/25/23 06:35, Manolis Tsamis wrote:
> > Propagation of the stack pointer in cprop_hardreg is currenty forbidden
> > in all cases, due to maybe_mode_change returning NULL. Relax
mcpu for temporary before binutils support, otherwise it just a broken
> > support for that CPU on trunk gcc.
> I pushed the binutils bits into the repo a couple months ago:
>
> > commit 1656d3f8ef56a16745689c03269412988ebcaa54
> > Author: Philipp Tomsich
> >
On Thu 8. Jun 2023 at 09:35, Kito Cheng via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> > diff --git a/gcc/config/riscv/riscv-cores.def
> b/gcc/config/riscv/riscv-cores.def
> > index 7d87ab7ce28..4078439e562 100644
> > --- a/gcc/config/riscv/riscv-cores.def
> > +++
On Thu, 1 Jun 2023 at 18:49, Jeff Law via Gcc-patches
wrote:
>
>
>
> On 6/1/23 01:01, juzhe.zh...@rivai.ai wrote:
> > I plan to implement BF16 vector in GCC but still waiting for ISA
> > ratified since GCC policy doesn't allow un-ratified ISA.
> Right. So those specs need to move along further
Assuming a fully pipelined vector unit (and from experience on
AArch64), an u-arch's scalar-to-vector move cost is likely to play a
significant role in whether this will be profitable or not.
--Philipp.
On Wed, 31 May 2023 at 00:10, Jeff Law via Gcc-patches
wrote:
>
>
>
> On 5/30/23 16:01, 钟居哲
LGTM. Happy to move this forward, once it receives an OK from one of you.
--Philipp.
On Fri, 26 May 2023 at 02:53, Die Li wrote:
>
> This patch allows less instructions to be used when TARGET_XTHEADCONDMOV is
> enabled.
>
> Provide an example from the existing testcases.
>
> Testcase:
> int
On Thu, 25 May 2023 at 16:14, Jeff Law via Gcc-patches
wrote:
>
>
>
> On 5/25/23 07:50, Richard Biener wrote:
> > On Thu, May 25, 2023 at 3:32 PM Jeff Law via Gcc-patches
> > wrote:
> >>
> >>
> >>
> >> On 5/25/23 07:01, Richard Biener via Gcc-patches wrote:
> >>> On Thu, May 25, 2023 at 2:36 PM
On Mon, 15 May 2023 at 10:18, wrote:
>
> From: Juzhe-Zhong
>
> Since we are going to have fixed-point intrinsics that are modeling rounding
> mode
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222
>
> We should have operand to specify rounding mode in fixed-point instructions.
> We
Bootstrapped and reg-tested overnight for x86 and aarch64.
Applied to master, thanks!
Philipp.
On Tue, 9 May 2023 at 09:13, Richard Biener wrote:
>
> On Tue, Dec 20, 2022 at 1:23 PM Manolis Tsamis
> wrote:
> >
> > When using SWAR (SIMD in a register) techniques a comparison operation
> >
uld accept this on gcc trunk without binutils
> support?
>
> On Sat, Apr 22, 2023 at 3:58 AM Jeff Law via Gcc-patches
> wrote:
> >
> >
> >
> > On 2/10/23 15:41, Philipp Tomsich wrote:
> > > This adds the xventanacondops extension to the option parsing
Any guidance on the next steps for this patch?
I believe that we answered all open questions, but may have missed something.
With trunk open for new development, we would like to revise and land this…
Thanks,
Philipp.
On Mon, 20 Mar 2023 at 15:02, Manolis Tsamis wrote:
>
> On Fri, Mar 17, 2023
On Mon, 17 Apr 2023 at 17:07, Kyrylo Tkachov wrote:
>
>
>
> > -Original Message-
> > From: Philipp Tomsich
> > Sent: Monday, April 17, 2023 11:22 AM
> > To: Kyrylo Tkachov
> > Cc: gcc-patches@gcc.gnu.org; Di Zhao
> > Subject: Re: [PATCH
OK for backport?
This will be all the way down to GCC10, as I just realized that we
need to backport the entire ampere1/1a support to GCC10 (we stopped at
GCC11 for some unexplainable reason)...
Philipp.
On Mon, 17 Apr 2023 at 12:20, Philipp Tomsich wrote:
>
> Applied to master,
Applied to master, thanks!
Philipp.
On Mon, 17 Apr 2023 at 11:56, Kyrylo Tkachov wrote:
>
>
> > -Original Message-
> > From: Philipp Tomsich
> > Sent: Friday, April 14, 2023 7:06 PM
> > To: gcc-patches@gcc.gnu.org
> > Cc: Kyrylo Tkachov ; Philip
2.47%
527.cam4_r 0.70%
538.imagick_r 0.00%
544.nab_r -0.33%
549.fotonik3d_r. -0.42%
554.roms_r 0.00%
-
= total 1.79%
Signed-off-by: Philipp Tomsich
Co-Authored-By: Di Zhao
gcc/ChangeLog
On Fri, 14 Apr 2023 at 13:02, Kyrylo Tkachov wrote:
> Hi Philipp,
>
> From: Philipp Tomsich
> Sent: Friday, April 14, 2023 11:26 AM
> To: Kyrylo Tkachov
> Cc: gcc-patches@gcc.gnu.org; Di Zhao
> Subject: Re: [PATCH] aarch64: disable LDP via tuning structure for
> -mcp
On Fri, 14 Apr 2023 at 11:31, Philipp Tomsich
wrote:
> Kyrylo,
>
> On Fri, 14 Apr 2023 at 11:21, Kyrylo Tkachov
> wrote:
> >
> > Hi Philipp,
> >
> > > -Original Message-
> > > From: Philipp Tomsich
> > > Sent: Friday, April 14,
requires refactoring, as it doesn't differentiate between the load and
store cases), pro/epilogue creation and mem* function expansion.
Philipp.
On Fri, 14 Apr 2023 at 11:31, Philipp Tomsich wrote:
>
> Kyrylo,
>
> On Fri, 14 Apr 2023 at 11:21, Kyrylo Tkachov wrote:
> &
Kyrylo,
On Fri, 14 Apr 2023 at 11:21, Kyrylo Tkachov wrote:
>
> Hi Philipp,
>
> > -Original Message-
> > From: Philipp Tomsich
> > Sent: Friday, April 14, 2023 12:22 AM
> > To: gcc-patches@gcc.gnu.org
> > Cc: Kyrylo Tkachov ; Philipp Tomsich
>
-by: Philipp Tomsich
Co-Authored-By: Di Zhao
gcc/ChangeLog:
* config/aarch64/aarch64-tuning-flags.def (AARCH64_EXTRA_TUNING_OPTION):
Add AARCH64_EXTRA_TUNE_NO_LDP_COMBINE.
* config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
Check for the above tuning option when
On Mon, 10 Apr 2023 at 17:57, Jeff Law wrote:
>
>
>
> On 4/9/23 23:07, Lin Sinan via Gcc-patches wrote:
> > From: Sinan Lin
> >
> > there is no need to split an xori/ori with an small constant. take the test
> > case `int foo(int idx) { return idx|3; }` as an example,
> >
> > rv64im_zba
; -Original Message-
> > From: Philipp Tomsich
> > Sent: Monday, March 27, 2023 9:50 AM
> > To: Kyrylo Tkachov
> > Cc: gcc-patches@gcc.gnu.org; Richard Sandiford
> > ; Tamar Christina
> > ; Manolis Tsamis
> > Subject: Re: [PATCH] aarch64: update amp
Applied to master, thanks!
Philipp.
On Mon, 27 Mar 2023 at 19:55, Kito Cheng wrote:
>
> OK for trunk, thanks :)
>
> On Mon, Mar 27, 2023 at 7:04 PM Christoph Muellner
> wrote:
>>
>> From: Christoph Müllner
>>
>> This patch adds missing mode specifiers for XTheadMemPair INSNs.
>>
>>
Applied to master, thanks!
Philipp.
On Mon, 27 Mar 2023 at 16:45, Kyrylo Tkachov wrote:
>
> Hi Philipp,
>
> > -Original Message-
> > From: Gcc-patches > bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Philipp
> > Tomsich
> > Sent: Mon
On Mon, 27 Mar 2023 at 16:45, Kyrylo Tkachov wrote:
>
> Hi Philipp,
>
> > -Original Message-
> > From: Gcc-patches > bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Philipp
> > Tomsich
> > Sent: Monday, March 27, 2023 8:47 AM
> >
: Update vector costs for ampere1.
Co-Authored-By: Manolis Tsamis
Signed-off-by: Philipp Tomsich
---
We would like to get this into GCC 13 to avoid having to backport at
the start of the next cycle.
OK for backports?
gcc/config/aarch64/aarch64.cc | 12 ++--
1 file changed, 6 insertions
On Fri, 17 Mar 2023 at 09:31, Richard Biener wrote:
>
> On Thu, Mar 16, 2023 at 4:27 PM Manolis Tsamis
> wrote:
> >
> > For this C testcase:
> >
> > void g();
> > void f(unsigned int *a)
> > {
> > if (++*a == 1)
> > g();
> > }
> >
> > GCC will currently emit a comparison with 1 by using
Just to add a bit more color on this one...
It was originally observed (and isolated from)
_ZN11xalanc_1_1027XalanReferenceCountedObject12addReferenceEPS0_ and
reproduces both for AArch64 and RISC-V.
The basic block (annotated with dynamic instructions executed and
percentage of total dynamic
Applied to master, thanks!
Philipp.
On Sun, 5 Mar 2023 at 11:18, Kito Cheng wrote:
> LGTM :)
>
>
> On Fri, Feb 24, 2023 at 7:19 PM Christoph Muellner
> wrote:
> >
> > From: Christoph Müllner
> >
> > This patch documents the new T-Head CPU support for RISC-V.
> >
> > Signed-off-by: Christoph
On Sun, 5 Mar 2023 at 11:19, Kito Cheng wrote:
> LGTM :)
>
Applied to master, thanks!
--Philipp.
On Thu, Mar 2, 2023 at 4:36 PM Christoph Muellner
> wrote:
> >
> > From: Christoph Müllner
> >
> > This series introduces support for the T-Head specific RISC-V ISA
> extensions
> > which are
>
> gcc/Changelog:
>
> * config/riscv/riscv.cc (riscv_rtx_costs): Fixed IN_RANGE() to
> use exact_log2().
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/zba-shNadd-07.c: f2(i*783) now generates MUL vs.
> 5 insn sh1add+slli+add+slli+sub.
> * gcc.target/riscv/pr108987.c: New test.
>
> Signed-off-by: Vineet Gupta
Reviewed-by: Philipp Tomsich
On Tue, 28 Feb 2023 at 06:00, Lin Sinan wrote:
>
> From: Lin Sinan
>
> The partial subreg check should be for subreg operand(operand 1) instead of
> the immediate operand(operand 2). This change also fix pr68648.c in zbs.
Good catch.
Reviewed-by:
/xventanacondops-ne-03.c: New test.
* gcc.target/riscv/xventanacondops-ne-04.c: New test.
* gcc.target/riscv/xventanacondops-xor-01.c: New test.
Signed-off-by: Philipp Tomsich
---
gcc/config/riscv/riscv.cc | 4 +--
gcc/config/riscv/riscv.md
to "bexti + addi".
Signed-off-by: Philipp Tomsich
---
gcc/config/riscv/zicond.md | 10 ++
1 file changed, 10 insertions(+)
diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
index 15fdaa539f1..0aad61c7009 100644
--- a/gcc/config/riscv/zicond.md
+++ b/gcc/
New test.
* gcc.target/riscv/xventanacondops-xor-01.c: New test.
Signed-off-by: Philipp Tomsich
---
gcc/ifcvt.cc | 216 ++
.../gcc.target/riscv/zicond-and-01.c | 16 ++
.../gcc.target/riscv/zicond-and-02.c | 15 ++
t.
Signed-off-by: Philipp Tomsich
---
gcc/config/riscv/zicond.md| 45 +++
gcc/testsuite/gcc.target/riscv/zicond-le-01.c | 16 +++
2 files changed, 61 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-le-01.c
diff --git a/gcc/config/riscv/z
/czero.nez through a splitter.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zicond-ifconv-imm.c: New test.
Signed-off-by: Philipp Tomsich
---
gcc/config/riscv/zicond.md| 20 +++
.../gcc.target/riscv/zicond-ifconv-imm.c | 19 ++
2 files
g/riscv/zicond.md: Add split to wrap an an
order-operator suitably for generating czero.eqz/nez
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zicond-le-02.c: New test.
* gcc.target/riscv/zicond-lt-03.c: New test.
Signed-off-by: Philipp Tomsich
---
gcc/config/riscv/predic
scv-opts.h (MASK_XVENTANACONDOPS): Define.
(TARGET_XVENTANACONDOPS): Define.
* config/riscv/riscv.opt: Add "riscv_xventanacondops".
Signed-off-by: Philipp Tomsich
---
gcc/common/config/riscv/riscv-common.cc | 2 ++
gcc/config/riscv/riscv-opts.h | 3 +++
gcc/config/riscv/riscv.
2017.
Philipp Tomsich (10):
docs: Document a canonical RTL for a conditional-zero insns
RISC-V: Recognize Zicond (conditional operations) extension
RISC-V: Generate czero.eqz/nez on noce_try_store_flag_mask
if-conversion
RISC-V: Support immediates in Zicond
RISC-V: Support
-zero as a single instruction for TARGET_ZICOND
* config/riscv/riscv.md: Include zicond.md.
* config/riscv/zicond.md: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zicond-ne-03.c: New test.
* gcc.target/riscv/zicond-ne-04.c: New test.
Signed-off-by: Philipp
On RISC-V, conditional-zero (i.e., move a register value or zero to a
destination register) instructions are part if the Zicond extension.
To support architectures that have similar constructs, we define a
canonical RTL representation that can be used in if-conversion.
Signed-off-by: Philipp
Signed-off-by: Philipp Tomsich
---
gcc/common/config/riscv/riscv-common.cc | 3 +++
gcc/config/riscv/riscv-opts.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 787674003cb..999e1926db1 100644
Just a quick heads-up to avoid duplication of work: we have a series
queued up for later this week (right now, SPEC2017 is still running
for QA purposes) that adds if-conversion support and converts that
into Zicond operations.
It doesn't have much overlap (except handling the "zicond" flag), as
(aarch_macro_fusion_pair_p): Check
REG_P on SET_DEST.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/pr108589.c: New test.
Signed-off-by: Philipp Tomsich
---
gcc/config/aarch64/aarch64.cc | 1 +
gcc/testsuite/gcc.target/aarch64/pr108589.c | 15 +++
2 files
On Mon, 30 Jan 2023 at 15:18, Kyrylo Tkachov wrote:
>
>
>
> > -Original Message-
> > From: Gcc-patches > bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Philipp
> > Tomsich
> > Sent: Saturday, January 28, 2023 11:12 PM
> > To: g
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Update
ampere1a to include SM4.
Signed-off-by: Philipp Tomsich
---
gcc/config/aarch64/aarch64-cores.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/aarch64/aarch64-cores.def
b
On Wed, 28 Dec 2022 at 19:18, Raphael Moreira Zinsly <
rzin...@ventanamicro.com> wrote:
> The Zbb min/max pattern was not matching 32-bit sources when
> compiling for 64-bit.
> This patch separates the pattern into SImode and DImode, and
> use a define_expand to handle SImode on 64-bit.
>
Applied to master (with the change from the reviews), thanks!
Philipp.
On Mon, 19 Dec 2022 at 07:30, Kito Cheng wrote:
> just one more nit: Use INVALID_REGNUM as sentinel value for
> riscv_next_saved_reg, otherwise LGTM, and feel free to commit that
> separately :)
>
> On Mon, Dec 19, 2022 at
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