[Bug c++/113032] New: RISCV linker relaxation leaves redundant addi (from load immediate)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113032 Bug ID: 113032 Summary: RISCV linker relaxation leaves redundant addi (from load immediate) Product: gcc Version: 12.2.0 Status: UNCONFIRMED Severity: normal

[Bug target/113023] RISCV redundant code for loading fixed address

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113023 --- Comment #4 from Iain Finlay --- GCC does know that it needs LANCHOR0 and LANCHOR0+4 (meaning a difference of 4). The 12-bit lower portion can be provided in the load and store commands. It seems just an implementation choice in pcnt0 that

[Bug target/113023] RISCV redundant code for loading fixed address

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113023 --- Comment #3 from Iain Finlay --- It does not get removed. It ends up in the final image. It is also redundant because load and store can also add a 12 bit signed offset.

[Bug c++/113023] New: RISCV redundant code for loading fixed address

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113023 Bug ID: 113023 Summary: RISCV redundant code for loading fixed address Product: gcc Version: 12.2.0 Status: UNCONFIRMED Severity: normal Priority: P3

[Bug c++/108284] New: RISCV 32-bit Zbs extension - ICE: in extract_insn, at recog.cc:2791

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108284 Bug ID: 108284 Summary: RISCV 32-bit Zbs extension - ICE: in extract_insn, at recog.cc:2791 Product: gcc Version: 12.2.0 Status: UNCONFIRMED Severity: normal