https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104610
Hongtao.liu changed:
What|Removed |Added
Attachment #52495|0 |1
is obsolete|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104610
--- Comment #15 from Hongtao.liu ---
Could someone help to mark this blocks PR105073, the patch is ready and waiting
for GCC13.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105073
Bug ID: 105073
Summary: [meta bug]Patch pending for GCC13.
Product: gcc
Version: 12.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
pinsrw is available for both reg and mem operand under sse2.
pextrw requires sse4.1 for mem operands.
The patch change attr "isa" for pinsrw mem alternative from sse4_noavx
to noavx, will enable below optimization.
-movzwl (%rdi), %eax
pxor%xmm1, %xmm1
-pinsrw $0,
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105066
--- Comment #2 from Hongtao.liu ---
> That may be a separate bug, IDK
>
Open PR105072 for it.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105072
Bug ID: 105072
Summary: Miss optimization for pmovzxbq.
Product: gcc
Version: 12.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105034
--- Comment #2 from Hongyu Wang ---
For -O2 stv doesn't do such transform
Computing gain for chain #1...
Instruction gain 8 for 7: {r84:SI=smax(r85:SI,0);clobber flags:CC;}
REG_DEAD r85:SI
REG_UNUSED flags:CC
Instruction
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99754
--- Comment #9 from Hongtao.liu ---
(In reply to Hongtao.liu from comment #7)
> >
> > But that's unrelated to correctness; this bug can be closed unless we're
> > keeping it open until it's fixed in the GCC11 current stable series.
>
> Let me
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99754
--- Comment #8 from CVS Commits ---
The releases/gcc-11 branch has been updated by hongtao Liu
:
https://gcc.gnu.org/g:85568e505c3b06708ec0fb21d1ab4f78e0c66896
commit r11-9699-g85568e505c3b06708ec0fb21d1ab4f78e0c66896
Author: Jakub Jelinek
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105066
--- Comment #1 from Hongtao.liu ---
pinsrw is under sse2 for both reg and mem operands, but not for pextrw which
requires sse4.1 for memory operands.
10593(define_insn "vec_set_0"
10594 [(set (match_operand:V8_128 0 "register_operand"
10595
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104915
--- Comment #1 from Hongtao.liu ---
As described in PR105066, pinsrw mem should be better than movzx + vmovd.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84508
--- Comment #16 from Andrew Pinski ---
>According to Intel (
> https://software.intel.com/sites/landingpage/IntrinsicsGuide), there are no
> alignment requirements for _mm_load_sd, _mm_store_sd and _mm_loaddup_pd. For
> example, from
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84508
Hongtao.liu changed:
What|Removed |Added
CC||crazylht at gmail dot com
--- Comment #15
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99754
--- Comment #7 from Hongtao.liu ---
>
> But that's unrelated to correctness; this bug can be closed unless we're
> keeping it open until it's fixed in the GCC11 current stable series.
Let me do the backporting.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105071
Andrew Pinski changed:
What|Removed |Added
Target Milestone|--- |9.5
Known to work|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105071
Bug ID: 105071
Summary: Incorrect code with -Os and complex
Product: gcc
Version: 9.3.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c++
Hi,
as seen on TSVC, Spec2017, the Zen3 gather instruction is a win only for
vectors with 8 elements. At the time I was implementing the tuning vectorizer
did not know how to open-code gather and thus it was still a win to enable it
for shorter vector, but this has changed.
The following are
Snapshot gcc-12-20220327 is now available on
https://gcc.gnu.org/pub/gcc/snapshots/12-20220327/
and on various mirrors, see http://gcc.gnu.org/mirrors.html for details.
This snapshot has been generated from the GCC 12 git branch
with the following options: git://gcc.gnu.org/git/gcc.git branch
When the mode of regno_reg_rtx is not hard_regno_mode_ok for the
target, try grouping the register with subsequent ones. This enables
s16 to s31 and their hidden pairs to be zeroed with the default logic
on some arm variants.
Regstrapped on x86_64-linux-gnu, also tested on an affected arm
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105064
Jonathan Wakely changed:
What|Removed |Added
Known to work||9.4.0
Status|WAITING
Hello, Marek,
The patch looks good to me, and I'd have no trouble approving it if we
were in stage1. Since we aren't, I'd prefer if we waited for another
build system maintainer to give it a look, if it's to go in gcc-12. If
release managers feel I'm being overcautious, I don't mind if they
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=50549
anlauf at gcc dot gnu.org changed:
What|Removed |Added
Assignee|unassigned at gcc dot gnu.org |anlauf at gcc dot
Dear all,
when assigning character pointers, we have a check for same length,
which however does not trigger for character pointers within a
structure constructor.
The attached patch extends the character checks slightly to fix
this loophole. I've verified that NAG and Crayftn behave similarly,
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102043
--- Comment #35 from Mikael Morin ---
A little status update.
I have pushed the latest patch attached to this PR a little further, but not
far enough to reduce the number of testsuite regressions to 0.
I plan to submit it for gcc-13, but it
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102419
Jason Merrill changed:
What|Removed |Added
Priority|P2 |P4
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102419
Jason Merrill changed:
What|Removed |Added
CC||jason at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105064
--- Comment #9 from Janez Zemva ---
Anyway, I've grown bored, so here's the minimal test case:
#include
class task
{
friend void suspend_to(auto const tp) noexcept
requires(std::is_same_v);
};
class loop
{
friend void
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105068
--- Comment #1 from CVS Commits ---
The master branch has been updated by H.J. Lu :
https://gcc.gnu.org/g:08e69332881f8d28ce8b559ffba1900ae5c0d5ee
commit r12-7837-g08e69332881f8d28ce8b559ffba1900ae5c0d5ee
Author: H.J. Lu
Date: Sun Mar 27
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105064
--- Comment #8 from Janez Zemva ---
I can reproduce the bug in my rpi4b:
$ g++ -std=c++20 -Ofast loopdemo.cpp -o l
In file included from loopdemo.cpp:3:
loop.hpp:169:55: internal compiler error: Segmentation fault
169 |
On Sun, Mar 27, 2022 at 8:14 PM H.J. Lu wrote:
>
> Since AVX512VL and AVX512BW are required for AVX512 VPSHUFB, replace the
> "Yv" register constraint with the "Yw" register constraint.
This is an obvious fix, as said in https://gcc.gnu.org/gitwrite.html :
Obvious fixes can be committed without
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105064
--- Comment #7 from Janez Zemva ---
Also, I'd like to add, that you can mount a github repository with FUSE, so
providing an URL is almost the same as providing an archive.
https://github.com/taterbase/git-mount
Since AVX512VL and AVX512BW are required for AVX512 VPSHUFB, replace the
"Yv" register constraint with the "Yw" register constraint.
gcc/
PR target/105068
* config/i386/sse.md (*ssse3_pshufbv8qi3): Replace "Yv" with
"Yw".
gcc/testsuite/
PR target/105068
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105064
--- Comment #6 from Janez Zemva ---
Also, there are several workarounds around this bug, but I'll keep my
repository in a crashing state, until you find time to produce a minimal test
case.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105064
--- Comment #5 from Janez Zemva ---
$ gcc -v
Using built-in specs.
COLLECT_GCC=gcc
COLLECT_LTO_WRAPPER=/usr/lib/gcc/x86_64-pc-linux-gnu/11.2.0/lto-wrapper
Target: x86_64-pc-linux-gnu
Configured with: /build/gcc/src/gcc/configure
Tested powerpc64le-linux, pushed to trunk.
It's late in stage 4 to be adding new features, but this is C++23-only
so entirely experimental, and not defined for the std-gnu++17 default
(or even -std=gnu++20). It does mean that the old (very old)
std::unexpected function is no longer available in
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101886
--- Comment #2 from Jason Merrill ---
This use of 'auto' was not accepted into C++20, so fixing this bug in the
vestigial Concepts TS implementation is a low priority.
On Wed, Feb 23, 2022 at 12:52 PM Richard Biener
wrote:
>
> On Tue, Feb 22, 2022 at 2:10 PM Shubham Narlawar
> wrote:
> >
> > On Tue, Feb 22, 2022 at 3:55 PM Richard Biener
> > wrote:
> > >
> > > On Tue, Feb 22, 2022 at 8:38 AM Shubham Narlawar
> > > wrote:
> > > >
> > > > On Mon, Feb 21,
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102071
Jason Merrill changed:
What|Removed |Added
CC||jason at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104987
Jeffrey A. Law changed:
What|Removed |Added
Target|iq2000-elf, v850e-elf |iq2000-elf
Priority|P3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105070
Bug ID: 105070
Summary: Missing debug info for switch statement
Product: gcc
Version: 11.1.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: debug
Hi!
On Thu, Mar 24, 2022 at 10:00:43AM +0800, Kewen.Lin wrote:
> Commit r12-7687 exposed one miss optimization chance in function
> rs6000_maybe_emit_maxc_minc, for now it only considers comparison
> codes GE/GT/LE/LT, but it can support more variants with codes
> UNLT/UNLE/UNGT/UNGE by reversing
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105069
--- Comment #1 from John Scott ---
Here is a backtrace:
bar.c:2:1: internal compiler error: ‘global_options’ are modified in local
context
2 | [[gnu::optimize("Os")]] int main(void) {}
| ^
0xe71b6b
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105069
Andrew Pinski changed:
What|Removed |Added
Keywords||ice-on-valid-code
Component|c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105069
Bug ID: 105069
Summary: [12 regression] sh-elf internal compiler errors and
test failures with -Os
Product: gcc
Version: 12.0
Status: UNCONFIRMED
Severity:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91440
R Copley changed:
What|Removed |Added
Status|UNCONFIRMED |RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103291
Jason Merrill changed:
What|Removed |Added
Assignee|unassigned at gcc dot gnu.org |jason at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105064
--- Comment #4 from Jonathan Wakely ---
And segfaults are not special, it's a bug like many others.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105064
--- Comment #3 from Jonathan Wakely ---
Read it again, because you've misunderstood. It doesn't say we need a minimal
example, that's not essential. But it clearly says to provide the code HERE,
not via URL. And to include the output of gcc -v.
On Fri, 25 Mar 2022 at 05:58, Jason Merrill wrote:
> >
> >>> + if (current_function_decl
> >>> + && (DECL_CONSTRUCTOR_P (current_function_decl)
> >>> + || DECL_DESTRUCTOR_P (current_function_decl))
> >>> + && TREE_CODE (expr) == NOP_EXPR
> >>> + &&
Hello,
Lately, I have been working on a way to implement recursion on the heap to
deal with
the limits associated with recursion on the stack. If a good implementation
is reached
that should allow us to convert the code.
I have implemented the data structure and I have written a simple factorial
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105064
--- Comment #2 from Janez Zemva ---
Yeah, I tried to make a minimal crash example for you, but it compiled
perfectly. Anyway, you know about the crash, you know about my repository and I
am no hurry for a fix, as this is my pet-project. And
da-checking-yes-rtl-df-extra-amd64
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 12.0.1 20220327 (experimental) (GCC)
On Fri, Mar 25, 2022 at 3:08 AM MayShao wrote:
>
> Hi Uros,
>
> This patch fix Zhaoxin CPU Vendor ID detection problem
> and add Zhaoxin "lujiazui" processor support and tuning.
>
> Currently gcc can't recognize Zhaoxin CPU (Vendor ID "CentaurHauls" and
> "Shanghai")
> and wrongly identify
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105067
Bug ID: 105067
Summary: ICE: in operator[], at vec.h:889
Product: gcc
Version: 12.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c++
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104719
--- Comment #14 from Jonathan Wakely ---
I have a patch to remove indirections in std::array which I'll commit for GCC
13.
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