[Bug target/115375] New: [15 Regression] RISCV scan failures since 2024-05-04

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115375 Bug ID: 115375 Summary: [15 Regression] RISCV scan failures since 2024-05-04 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3

[Bug target/115373] [15 Regression] RISCV slp-cond-2-big-array.c slp-cond-2.c scan-tree-dump fails since r15-859-geaaa4b88038

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115373 --- Comment #1 from Patrick O'Neill --- Relevant postcommit issue: https://github.com/patrick-rivos/gcc-postcommit-ci/issues/999

[Bug target/115373] New: [15 Regression] RISCV slp-cond-2-big-array.c slp-cond-2.c scan-tree-dump fails since r15-859-geaaa4b88038

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115373 Bug ID: 115373 Summary: [15 Regression] RISCV slp-cond-2-big-array.c slp-cond-2.c scan-tree-dump fails since r15-859-geaaa4b88038 Product: gcc Version: 15.0

[Bug target/115372] [15 Regression] RISCV pr97428.c scan-tree-dump-times after r15-812-gc71886f2ca2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115372 --- Comment #1 from Patrick O'Neill --- debug output: gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c: vsseg3e64\\.v found 0 times FAIL: gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c scan-assembler-times vsseg3e64\\.v 8

[Bug target/115372] New: [15 Regression] RISCV pr97428.c scan-tree-dump-times after r15-812-gc71886f2ca2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115372 Bug ID: 115372 Summary: [15 Regression] RISCV pr97428.c scan-tree-dump-times after r15-812-gc71886f2ca2 Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug middle-end/115346] New: [15] Volatile load elimination with packed struct bitfields at -O2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115346 Bug ID: 115346 Summary: [15] Volatile load elimination with packed struct bitfields at -O2 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/115336] [15] rv64gcv_zvl256b miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115336 Patrick O'Neill changed: What|Removed |Added Keywords||wrong-code Target|

[Bug target/115336] New: [15] rv64gcv_zvl256b miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115336 Bug ID: 115336 Summary: [15] rv64gcv_zvl256b miscompile at -O3 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug c++/115195] [12 Regression] Segfault when instantiating template

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115195 --- Comment #4 from Patrick O'Neill --- Thanks Andrew

[Bug c++/115195] New: [12 Regression] Segfault when instantiating template

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115195 Bug ID: 115195 Summary: [12 Regression] Segfault when instantiating template Product: gcc Version: 12.3.0 Status: UNCONFIRMED Severity: normal Priority: P3

[Bug tree-optimization/115143] New: [14/15 Regression] tree check: expected class 'type', have 'exceptional' (error_mark) in useless_type_conversion_p, at gimple-expr.cc:85

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115143 Bug ID: 115143 Summary: [14/15 Regression] tree check: expected class 'type', have 'exceptional' (error_mark) in useless_type_conversion_p, at gimple-expr.cc:85 Product:

[Bug target/115142] New: [14/15 Regression] Unrecognizable insn in extract_insn, at recog.cc:2812 with -ftree-ter

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115142 Bug ID: 115142 Summary: [14/15 Regression] Unrecognizable insn in extract_insn, at recog.cc:2812 with -ftree-ter Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug target/115123] New: [15 Regression] RISCV vector scan-assembler failures

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115123 Bug ID: 115123 Summary: [15 Regression] RISCV vector scan-assembler failures Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3

[Bug rtl-optimization/115104] RISC-V: GCC-14 can combine vsext+vadd -> vwadd but Trunk GCC (GCC 15) Failed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115104 --- Comment #4 from Patrick O'Neill --- Relevant CI issue: https://github.com/patrick-rivos/gcc-postcommit-ci/issues/895 Commit Range:

[Bug target/114916] New: [14/15] RISC-V rv64gcv_zvl256b: miscompile at -O3 with -mrvv-vector-bits=zvl -fwhole-program

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114916 Bug ID: 114916 Summary: [14/15] RISC-V rv64gcv_zvl256b: miscompile at -O3 with -mrvv-vector-bits=zvl -fwhole-program Product: gcc Version: 14.0 Status: UNCONFIRMED

[Bug target/114734] [11/12/13/14 regression] RISC-V rv64gcv_zvl256b miscompile with -flto -O3 -mrvv-vector-bits=zvl since r8-6047-g65dd1346027bb5

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114734 --- Comment #14 from Patrick O'Neill --- I'll send a patch with the testcase in a few hours. Testing it now.

[Bug target/114756] New: [14] RISC-V rv32imc miscompile with -fdata-sections

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114756 Bug ID: 114756 Summary: [14] RISC-V rv32imc miscompile with -fdata-sections Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3

[Bug tree-optimization/114749] New: [14] RISC-V rv64gcv ICE: in vectorizable_load, at tree-vect-stmts.cc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114749 Bug ID: 114749 Summary: [14] RISC-V rv64gcv ICE: in vectorizable_load, at tree-vect-stmts.cc Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug target/114734] New: [14] RISC-V rv64gcv_zvl256b miscompile with -flto -O3 -mrvv-vector-bits=zvl

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114734 Bug ID: 114734 Summary: [14] RISC-V rv64gcv_zvl256b miscompile with -flto -O3 -mrvv-vector-bits=zvl Product: gcc Version: 14.0 Status: UNCONFIRMED Severity:

[Bug middle-end/114733] New: [14] Miscompile with -march=rv64gcv -O3 on riscv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114733 Bug ID: 114733 Summary: [14] Miscompile with -march=rv64gcv -O3 on riscv Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3

[Bug target/114665] [14] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114665 --- Comment #6 from Patrick O'Neill --- Binutils: #binutils-2_42 (c7f28aad0c99d1d2fec4e52ebfa3735d90ceb8e9) QEMU_CPU=rv64,vlen=128,v=true,vext_spec=v1.0,zve32f=true,zve64f=true

[Bug target/114665] [14] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114665 --- Comment #4 from Patrick O'Neill --- Reran as requested in pr114668. Still present with that fix. I'll triage some other testcases and file those as well. Hopefully one of them is a duplicate to this one that is easily reproducible. GCC:

[Bug target/114665] [14] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114665 --- Comment #3 from Patrick O'Neill --- Created attachment 57922 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=57922=edit Generated assembly files Hmm doesn't look like it from my side - maybe there's some stack related weirdness going

[Bug target/114671] New: [RISC-V] -fvar-tracking -gas-locview-support -ggdb emits a non-constant .uleb128

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114671 Bug ID: 114671 Summary: [RISC-V] -fvar-tracking -gas-locview-support -ggdb emits a non-constant .uleb128 Product: gcc Version: 14.0 Status: UNCONFIRMED

[Bug target/114668] New: [14] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114668 Bug ID: 114668 Summary: [14] RISC-V rv64gcv: miscompile at -O3 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug middle-end/114666] New: [14 Regression] Signed single bit comparison miscompile at -O2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114666 Bug ID: 114666 Summary: [14 Regression] Signed single bit comparison miscompile at -O2 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug target/114665] New: [14] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114665 Bug ID: 114665 Summary: [14] RISC-V rv64gcv: miscompile at -O3 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug debug/114608] [14 Regression] Undefined reference in output asm with -fipa-reference -fipa-reference-addressable -fsection-anchors -gbtf

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114608 --- Comment #2 from Patrick O'Neill --- (.BTF+0x88): undefined reference to `a' ^ This is the interesting failure line

[Bug debug/114608] [14 Regression] Undefined reference in output asm with -fipa-reference -fipa-reference-addressable -fsection-anchors -gbtf

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114608 --- Comment #1 from Patrick O'Neill --- Command: > /scratch/tc-testing/tc-apr-4/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc > -fipa-reference -fipa-reference-addressable -fsection-anchors -gbtf red.c -o > rv64gcv.out

[Bug debug/114608] New: [14 Regression] Undefined reference in output asm with -fipa-reference -fipa-reference-addressable -fsection-anchors -gbtf

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114608 Bug ID: 114608 Summary: [14 Regression] Undefined reference in output asm with -fipa-reference -fipa-reference-addressable -fsection-anchors -gbtf Product: gcc

[Bug ipa/114247] RISC-V: miscompile at -O3 and IPA SRA

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114247 --- Comment #8 from Patrick O'Neill --- Adjusted testcase: union a { unsigned short b; int c; signed short d; }; int e, f = 1, g; long h; const int **i; void j(union a k, int l, unsigned m) { const int *a[100]; i = [0]; h = k.d; }

[Bug tree-optimization/114485] New: [14] Wrong code with -O3 -march=rv64gcv on riscv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114485 Bug ID: 114485 Summary: [14] Wrong code with -O3 -march=rv64gcv on riscv Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3

[Bug target/114476] New: [14] RISC-V rv64gcv vector: Runtime mismatch at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114476 Bug ID: 114476 Summary: [14] RISC-V rv64gcv vector: Runtime mismatch at -O3 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3

[Bug target/114399] [14] RISC-V rv32i miscompile

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114399 Patrick O'Neill changed: What|Removed |Added Resolution|INVALID |FIXED --- Comment #3 from Patrick

[Bug target/114399] New: [14] RISC-V rv32i miscompile

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114399 Bug ID: 114399 Summary: [14] RISC-V rv32i miscompile Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/114396] [14 Regression] Vector: Runtime mismatch at -O2 with -fwrapv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114396 Patrick O'Neill changed: What|Removed |Added Target|x86_64-*-* riscv*-*-* |riscv*-*-* aarch64-*-*

[Bug target/114396] [14] RISC-V rv64gcv vector: Runtime mismatch at -O3 with -fwrapv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114396 --- Comment #1 from Patrick O'Neill --- Here's the result when running with -fwrapv on rv64gcv at O2: > /scratch/tc-testing/tc-mar-18/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc > -march=rv64gcv -O2 red.c -o red.out -fwrapv >

[Bug target/114396] New: [14] RISC-V rv64gcv vector: Runtime mismatch at -O3 with -fwrapv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114396 Bug ID: 114396 Summary: [14] RISC-V rv64gcv vector: Runtime mismatch at -O3 with -fwrapv Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug tree-optimization/114386] [11/12/13 Regression] Miscompile at -O1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114386 --- Comment #4 from Patrick O'Neill --- (In reply to Patrick O'Neill from comment #0) > ... > Issue is not present when targeting risc-v. This was in reference to tip-of-tree gcc - forgot to update this when I determined the upper bound of the

[Bug target/114386] New: [10/11/12 Regression] Miscompile at -O1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114386 Bug ID: 114386 Summary: [10/11/12 Regression] Miscompile at -O1 Product: gcc Version: 12.3.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component:

[Bug tree-optimization/113281] [11/12/13 Regression] Latent wrong code due to vectorization of shift reduction and missing promotions since r9-1590

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113281 --- Comment #27 from Patrick O'Neill --- (In reply to Andrew Pinski from comment #26) > (In reply to Edwin Lu from comment #25) > > It's still persisting on trunk (at least for pr113281-1.c > > https://godbolt.org/z/M9EK44hKe) > > I looked

[Bug c/114314] New: [14 Regression] ICE: in common_handle_option, at opts.cc:3356 with -fno-multiflags

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114314 Bug ID: 114314 Summary: [14 Regression] ICE: in common_handle_option, at opts.cc:3356 with -fno-multiflags Product: gcc Version: 14.0 Status: UNCONFIRMED

[Bug middle-end/114198] [14] RISC-V fixed-length vector -flto ICE: in vectorizable_load, at tree-vect-stmts.cc:10570

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114198 Patrick O'Neill changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug middle-end/114198] [14] RISC-V fixed-length vector -flto ICE: in vectorizable_load, at tree-vect-stmts.cc:10570

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114198 --- Comment #3 from Patrick O'Neill --- Fixed!

[Bug middle-end/114195] [14] RISC-V vector ICE: in vectorizable_store, at tree-vect-stmts.cc:8690

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114195 Patrick O'Neill changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug middle-end/114196] [13/14 Regression] Fixed length vector ICE: in vect_peel_nonlinear_iv_init, at tree-vect-loop.cc:9454

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114196 Patrick O'Neill changed: What|Removed |Added Resolution|FIXED |--- Status|RESOLVED

[Bug middle-end/114196] [13/14 Regression] Fixed length vector ICE: in vect_peel_nonlinear_iv_init, at tree-vect-loop.cc:9454

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114196 Patrick O'Neill changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug rtl-optimization/114261] [13/14 Regression] Scheduling takes excessive time (97%)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114261 Patrick O'Neill changed: What|Removed |Added Attachment #57640|0 |1 is obsolete|

[Bug rtl-optimization/114261] [13/14 Regression] Scheduling takes excessive time (97%)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114261 --- Comment #2 from Patrick O'Neill --- Created attachment 57641 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=57641=edit unreduced preprocessed testcase

[Bug rtl-optimization/114261] [13/14 Regression] Scheduling takes excessive time (97%)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114261 --- Comment #1 from Patrick O'Neill --- Created attachment 57640 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=57640=edit Raw testcase and headers

[Bug rtl-optimization/114261] New: [13/14 Regression] Scheduling takes excessive time (97%)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114261 Bug ID: 114261 Summary: [13/14 Regression] Scheduling takes excessive time (97%) Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug target/114200] [14] RISC-V fixed-length vector miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114200 Patrick O'Neill changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug tree-optimization/114249] [14 regression] ICE when building lvm2-2.03.22 (error: invalid types in nop conversion)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114249 Patrick O'Neill changed: What|Removed |Added CC||patrick at rivosinc dot com ---

[Bug tree-optimization/114259] [14 Regression] ICE during GIMPLE pass: slp: internal compiler error: tree check: expected class 'type', have 'exceptional' (error_mark) in useless_type_conversion_p, at

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114259 Patrick O'Neill changed: What|Removed |Added Resolution|--- |DUPLICATE

[Bug tree-optimization/114259] New: [14 Regression] ICE during GIMPLE pass: slp: internal compiler error: tree check: expected class 'type', have 'exceptional' (error_mark) in useless_type_conversion

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114259 Bug ID: 114259 Summary: [14 Regression] ICE during GIMPLE pass: slp: internal compiler error: tree check: expected class 'type', have 'exceptional' (error_mark) in

[Bug target/114247] New: RISC-V: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114247 Bug ID: 114247 Summary: RISC-V: miscompile at -O3 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug middle-end/114198] [14] RISC-V fixed-length vector -flto ICE: in vectorizable_load, at tree-vect-stmts.cc:10570

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114198 --- Comment #2 from Patrick O'Neill --- (In reply to Richard Biener from comment #1) > Probably also with -fwhole-program instead of -flto Thanks! Updated args (--param=riscv-autovec-preference=fixed-vlmax was recently removed):

[Bug target/114202] [14] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114202 --- Comment #1 from Patrick O'Neill --- Looks similar to pr114200 so it might be related/duplicate.

[Bug target/114202] New: [14] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114202 Bug ID: 114202 Summary: [14] RISC-V rv64gcv: miscompile at -O3 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/114200] New: [14] RISC-V fixed-length vector miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114200 Bug ID: 114200 Summary: [14] RISC-V fixed-length vector miscompile at -O3 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3

[Bug middle-end/114198] New: [14] RISC-V fixed-length vector -flto ICE: in vectorizable_load, at tree-vect-stmts.cc:10570

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114198 Bug ID: 114198 Summary: [14] RISC-V fixed-length vector -flto ICE: in vectorizable_load, at tree-vect-stmts.cc:10570 Product: gcc Version: 14.0 Status: UNCONFIRMED

[Bug middle-end/114197] [14] middle-end: ICE in verify_dominators

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114197 --- Comment #2 from Patrick O'Neill --- found via fuzzer

[Bug middle-end/114196] New: [13/14 Regression] Fixed length vector ICE: in vect_peel_nonlinear_iv_init, at tree-vect-loop.cc:9454

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114196 Bug ID: 114196 Summary: [13/14 Regression] Fixed length vector ICE: in vect_peel_nonlinear_iv_init, at tree-vect-loop.cc:9454 Product: gcc Version: 14.0 Status:

[Bug target/114195] New: [14] RISC-V vector ICE: in vectorizable_store, at tree-vect-stmts.cc:8690

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114195 Bug ID: 114195 Summary: [14] RISC-V vector ICE: in vectorizable_store, at tree-vect-stmts.cc:8690 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity:

[Bug target/114028] [14] RISC-V rv64gcv_zvl256b: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114028 Patrick O'Neill changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug middle-end/112971] [14] RISC-V rv64gcv_zvl256b vector -O3: internal compiler error: Segmentation fault signal terminated program cc1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112971 Patrick O'Neill changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/114028] New: [14] RISC-V rv64gcv_zvl256b: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114028 Bug ID: 114028 Summary: [14] RISC-V rv64gcv_zvl256b: miscompile at -O3 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component:

[Bug target/114027] New: [14] RISC-V vector: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114027 Bug ID: 114027 Summary: [14] RISC-V vector: miscompile at -O3 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/113796] New: [14] RISC-V rv64gcv vector: Runtime mismatch at -O2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113796 Bug ID: 113796 Summary: [14] RISC-V rv64gcv vector: Runtime mismatch at -O2 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3

[Bug middle-end/113607] [14] RISC-V rv64gcv vector: Runtime mismatch at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113607 Patrick O'Neill changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/113607] [14] RISC-V rv64gcv vector: Runtime mismatch at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113607 --- Comment #6 from Patrick O'Neill --- I think I may have messed up when copy/pasting the testcase. Please try this testcase: struct { signed b; } c, d = {6}; short e, f; int g[1000]; signed char h; int i, j; long k, l; long m(long n, long

[Bug target/113607] [14] RISC-V rv64gcv vector: Runtime mismatch at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113607 --- Comment #5 from Patrick O'Neill --- Hmm that's odd. I just reproduced with tip-of-tree GCC. > /scratch/tc-testing/tc-jan-25-reconfirm/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc > -O3 -march=rv64gcv red.c -o user-config-o3.out >

[Bug target/113607] New: [14] RISC-V rv64gcv vector: Runtime mismatch at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113607 Bug ID: 113607 Summary: [14] RISC-V rv64gcv vector: Runtime mismatch at -O3 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3

[Bug tree-optimization/113603] New: [14 Regression] ICE Segfault during GIMPLE pass: strlen at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113603 Bug ID: 113603 Summary: [14 Regression] ICE Segfault during GIMPLE pass: strlen at -O3 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug target/112755] RISC-V regression testsuite errors with rv32gcv_zvl256b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112755 Patrick O'Neill changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/112754] RISC-V regression testsuite errors with rv32gcv_zvl128b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112754 Patrick O'Neill changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/112798] RISC-V regression testsuite errors with rv64gcv_zve32f

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112798 Patrick O'Neill changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/112757] RISC-V regression testsuite errors with rv32gcv_zvl1024b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112757 Patrick O'Neill changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/112756] RISC-V regression testsuite errors with rv32gcv_zvl512b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112756 Patrick O'Neill changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/112598] RISC-V regression testsuite errors with rv64gcv_zvl512b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112598 Patrick O'Neill changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/112583] RISC-V regression testsuite errors with rv64gcv_zvl128b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112583 Patrick O'Neill changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/112597] RISC-V regression testsuite errors with rv64gcv_zvl256b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112597 Patrick O'Neill changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/112599] RISC-V regression testsuite errors with rv64gcv_zvl1024b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112599 Patrick O'Neill changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug testsuite/112799] RISC-V regression testsuite errors with rv32gcv_zve64d

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112799 Patrick O'Neill changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug testsuite/112800] RISC-V regression testsuite errors with rv32gcv_zve32f

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112800 Patrick O'Neill changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/112797] RISC-V regression testsuite errors with rv64gcv_zve64d

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112797 Patrick O'Neill changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/113087] [14] RISC-V rv64gcv vector: Runtime mismatch with rv64gc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113087 --- Comment #43 from Patrick O'Neill --- (In reply to Patrick O'Neill from comment #42) > I kicked off a run roughly 10 hours ago with your memory-hog fix patch > applied to a1b2953924c451ce90a3fdce6841b63bf05f335f. I'll post the results > here

[Bug target/113010] [RISCV] sign-extension lost in comparison with constant embedded in comma-op expression

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113010 --- Comment #8 from Patrick O'Neill --- >From the CI run here: https://patchwork.sourceware.org/project/gcc/patch/20240116221914.267015-1-...@rivosinc.com/ It looks like this issue also affects ARM since the testcase fails.

[Bug target/113087] [14] RISC-V rv64gcv vector: Runtime mismatch with rv64gc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113087 --- Comment #42 from Patrick O'Neill --- (In reply to JuzheZhong from comment #41) > Hi, Patrick. > > Could you trigger test again base on latest trunk GCC? > > We have recent memory-hog fix patch: >

[Bug target/113087] [14] RISC-V rv64gcv vector: Runtime mismatch with rv64gc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113087 --- Comment #40 from Patrick O'Neill --- (In reply to Patrick O'Neill from comment #39) > FYI I ran spec2017 last night and got: > > zvl128b: > no fails! > > zvl256b: > 549.fotonik3d (runtime) - pr113570 GCC hash:

[Bug target/113087] [14] RISC-V rv64gcv vector: Runtime mismatch with rv64gc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113087 --- Comment #39 from Patrick O'Neill --- FYI I ran spec2017 last night and got: zvl128b: no fails! zvl256b: 549.fotonik3d (runtime) - pr113570

[Bug rtl-optimization/113495] RISC-V: Time and memory awful consumption of SPEC2017 wrf benchmark

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113495 Patrick O'Neill changed: What|Removed |Added CC||patrick at rivosinc dot com ---

[Bug target/113431] [14] RISC-V rv64gcv vector: Runtime mismatch at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113431 --- Comment #7 from Patrick O'Neill --- (In reply to JuzheZhong from comment #6) > (In reply to Patrick O'Neill from comment #5) > > (In reply to JuzheZhong from comment #4) > > > a[0][1] seems to be undefined value. > > > > a is a global

[Bug target/113431] [14] RISC-V rv64gcv vector: Runtime mismatch at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113431 --- Comment #5 from Patrick O'Neill --- (In reply to JuzheZhong from comment #4) > a[0][1] seems to be undefined value. a is a global variable so the elements are initialized to 0. a[0][1] is within the bounds a[2][9].

[Bug target/113431] [14] RISC-V rv64gcv vector: Runtime mismatch at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113431 --- Comment #3 from Patrick O'Neill --- This has the same behavior with --param=vsetvl-strategy=simple so this is probably not a vsetvl issue. > /scratch/tc-testing/tc-jan-16-vsetvl-toggle/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc > -O3

[Bug target/113431] [14] RISC-V rv64gcv vector: Runtime mismatch at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113431 Patrick O'Neill changed: What|Removed |Added Keywords||wrong-code Target|

[Bug target/113431] New: [14] RISC-V rv64gcv vector: Runtime mismatch at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113431 Bug ID: 113431 Summary: [14] RISC-V rv64gcv vector: Runtime mismatch at -O3 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3

[Bug target/113087] [14] RISC-V rv64gcv vector: Runtime mismatch with rv64gc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113087 --- Comment #32 from Patrick O'Neill --- (In reply to JuzheZhong from comment #31) > You are using -Ofast which will have precision issue on floating-point. > > You can reference it: > > https://godbolt.org/z/zzG8xbx95 > > O3 result:

[Bug target/113087] [14] RISC-V rv64gcv vector: Runtime mismatch with rv64gc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113087 --- Comment #30 from Patrick O'Neill --- (In reply to Li Pan from comment #29) > Thanks a lot for the summary. Could you please help to share some more > information about the spec2017 for above data? Like data set (test, train, > or ref), the

[Bug target/113282] RISC-V non-atomic union store/load reordering

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113282 Patrick O'Neill changed: What|Removed |Added Resolution|INVALID |FIXED --- Comment #4 from Patrick

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