https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105052
Bug ID: 105052 Summary: Incorrect constraint on SSSE3 split patterns with MMX operands Product: gcc Version: 10.3.1 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: hjl.tools at gmail dot com Target Milestone: --- define_insn_and_split "ssse3_ph<plusminus_mnemonic>wv4hi3" and define_insn_and_split "ssse3_ph<plusminus_mnemonic>dv2si3" have the Yv register constraint: (define_register_constraint "Yv" "TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS" "@internal For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), otherwise any SSE register.") But these instructions aren't available with EVEX encoding. The x register constraint should be used.