From: Juzhe-Zhong
According to new comming fixed-point API:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222
Introduce vxrm argument:
- vint32m1_t __riscv_vsadd_vv_i32m1 (vint32m1_t op1, vint32m1_t op2, size_t vl);
+ vint32m1_t __riscv_vsadd_vv_i32m1 (vint32m1_t op1, vint32m1_t op2,
On 5/10/23 09:50, Jivan Hakobyan via Gcc-patches wrote:
Subject:
RISC-V: Remove masking third operand of rotate instructions
From:
Jivan Hakobyan via Gcc-patches
Date:
5/10/23, 09:50
To:
gcc-patches@gcc.gnu.org
Rotate instructions do not need to mask the third operand.
For example RV64
On 5/16/23 20:39, Palmer Dabbelt wrote:
By "chroot environment" you mean something like a
debootstrap-into-chroot with qemu-user/binfmt-misc? I don't have that
setup right now, but it wouldn't be a big lift.
Essentially, yes. I actually have a home built ones for the various
targets.
On 5/16/23 21:33, Kito Cheng via Gcc-patches wrote:
diff --git a/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run
b/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run
index 94d6ec5..efc3a80 100755
--- a/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run
+++
On Wed, May 17, 2023 at 11:36 AM juzhe.zh...@rivai.ai
wrote:
>
> >> Does it means we assume inner_int_mode is DImode? (because sizeof
> >> (uint64_t))
> >> or it should be something like `for (unsigned int i = 0; i <
> >> (GET_MODE_SIZE(inner_int_mode ()) * 8 / npatterns ()); i++)` ?
> No,
>> Does it means we assume inner_int_mode is DImode? (because sizeof (uint64_t))
>> or it should be something like `for (unsigned int i = 0; i <
>> (GET_MODE_SIZE(inner_int_mode ()) * 8 / npatterns ()); i++)` ?
No, sizeof (uint64_t) means uint64_t mask = 0;
>> Do you mind give more comment about
> diff --git a/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run
> b/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run
> index 94d6ec5..efc3a80 100755
> --- a/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run
> +++ b/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run
> @@ -12,4 +12,4 @@ done
>
> +
> +/* Get the mask for merge approach.
> +
> + Consider such following case:
> + {a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b}
> + To merge "a", the mask should be 1010
> + To merge "b", the mask should be 0101
> +*/
> +rtx
> +rvv_builder::get_merge_mask_bitfield
On Tue, 16 May 2023 20:08:26 PDT (-0700), Vineet Gupta wrote:
On 5/16/23 19:53, Palmer Dabbelt wrote:
Probably, I'll go try and bump stuff and see if it works...
Word of caution: Best to not disturb your existing setup, a try a fresh
checkout first
Even easier, I think I can get away with
On 5/16/23 19:53, Palmer Dabbelt wrote:
Probably, I'll go try and bump stuff and see if it works...
Word of caution: Best to not disturb your existing setup, a try a fresh
checkout first
I would like to defer this until the PR has updated.
On Wed, May 17, 2023 at 9:52 AM wrote:
>
> From: Juzhe-Zhong
>
> Hi, since fixed-point with modeling rounding mode intrinsics are coming:
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222
>
> I am adding vxrm rounding mode enum to
On Tue, 16 May 2023 19:51:48 PDT (-0700), Patrick O'Neill wrote:
On 5/16/23 19:47, Palmer Dabbelt wrote:
On Tue, 16 May 2023 19:46:28 PDT (-0700), Vineet Gupta wrote:
On 5/16/23 19:21, Kito Cheng wrote:
Palmer:
For short-term, this should help your internal test:
On 5/16/23 19:47, Palmer Dabbelt wrote:
On Tue, 16 May 2023 19:46:28 PDT (-0700), Vineet Gupta wrote:
On 5/16/23 19:21, Kito Cheng wrote:
Palmer:
For short-term, this should help your internal test:
https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1233
That only helps if using
On Tue, 16 May 2023 19:46:28 PDT (-0700), Vineet Gupta wrote:
On 5/16/23 19:21, Kito Cheng wrote:
Palmer:
For short-term, this should help your internal test:
https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1233
That only helps if using bleeding edge toolchain scripts (which I
On 5/16/23 19:21, Kito Cheng wrote:
Palmer:
For short-term, this should help your internal test:
https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1233
That only helps if using bleeding edge toolchain scripts (which I
regularly do and so did Patrick).
Palmer has a fork of toolchain
On Tue, 16 May 2023 19:32:21 PDT (-0700), jeffreya...@gmail.com wrote:
On 5/16/23 20:05, Palmer Dabbelt wrote:
On Tue, 16 May 2023 19:00:12 PDT (-0700), Jeff Law wrote:
On 5/16/23 19:29, Palmer Dabbelt wrote:
I think the most pressing need is bleeding edge gcc regression
tracking.
On 5/16/23 20:05, Palmer Dabbelt wrote:
On Tue, 16 May 2023 19:00:12 PDT (-0700), Jeff Law wrote:
On 5/16/23 19:29, Palmer Dabbelt wrote:
I think the most pressing need is bleeding edge gcc regression
tracking.
@Jeff is anything setup on sourceware and/or usable ? I thought they
do
Palmer:
For short-term, this should help your internal test:
https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1233
On Wed, May 17, 2023 at 10:20 AM Kito Cheng wrote:
>
> Currently we are highly rely on simulator can setup correctly by ELF
> attribute or -march setting, but seems not
Currently we are highly rely on simulator can setup correctly by ELF
attribute or -march setting, but seems not true for everyone, for
longer term we need something like
check_effective_target_aarch64_sve_hw, but as Palmer point out, we
might need...bunch of that for different extensions
On
Hi,
On 2023-05-15 14:53, Kewen.Lin wrote:
Hi Jeff,
on 2022/12/12 09:38, Jiufu Guo wrote:
Hi,
For constant C:
If '(c & 0xULL) == 0x' or say:
32(1) || 1(0) || 15(x) || 16(0), we could use "lis; xoris" to build.
Here N(M) means N continuous bit M, x for M means
On Tue, 16 May 2023 19:07:01 PDT (-0700), juzhe.zh...@rivai.ai wrote:
Oh, I see. Kito has add /* { dg-do run { target { riscv_vector } } } */
But not all RVV tests has use this and I not sure whether it can work.
I think Kito can answer it.
If yes, I think we should add all of them.
Unless I'm
On 5/16/23 20:08, Vineet Gupta wrote:
I think the most pressing need is bleeding edge gcc regression tracking.
@Jeff is anything setup on sourceware and/or usable ? I thought they
do have existing bots for some arches to spin up build / run - perhaps
runs are native and not qemu.
IIRC
On 5/16/23 18:29, Palmer Dabbelt wrote:
On Tue, 16 May 2023 18:04:37 PDT (-0700), Vineet Gupta wrote:
+ Christoph, Jiawei
On 5/16/23 17:20, Palmer Dabbelt wrote:
We really need to add some CI around RV toolchains to trip on these
sooner !
Sounds like you're volunteering to set one up?
Oh, I see. Kito has add /* { dg-do run { target { riscv_vector } } } */
But not all RVV tests has use this and I not sure whether it can work.
I think Kito can answer it.
If yes, I think we should add all of them.
Thanks.
juzhe.zh...@rivai.ai
From: Andrew Pinski
Date: 2023-05-17 10:02
To:
On Tue, 16 May 2023 19:00:12 PDT (-0700), Jeff Law wrote:
On 5/16/23 19:29, Palmer Dabbelt wrote:
I think the most pressing need is bleeding edge gcc regression tracking.
@Jeff is anything setup on sourceware and/or usable ? I thought they
do have existing bots for some arches to spin up
On Tue, May 16, 2023 at 6:58 PM juzhe.zh...@rivai.ai
wrote:
>
> Hi, Palmer.
> I saw your patch showed there are a lot of run time fail (execution fail) of
> C++.
> bug-*.C
>
> These tests are RVV api intrinsics tests coming from Kito's that I have
> already fixed all of them.
> I just double
On 5/16/23 19:29, Palmer Dabbelt wrote:
I think the most pressing need is bleeding edge gcc regression tracking.
@Jeff is anything setup on sourceware and/or usable ? I thought they
do have existing bots for some arches to spin up build / run - perhaps
runs are native and not qemu.
Hi, Palmer.
I saw your patch showed there are a lot of run time fail (execution fail) of
C++.
bug-*.C
These tests are RVV api intrinsics tests coming from Kito's that I have already
fixed all of them.
I just double checked again they all passed.
I think it may be your regression environment
From: Juzhe-Zhong
Hi, since fixed-point with modeling rounding mode intrinsics are coming:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222
I am adding vxrm rounding mode enum to user first before the API intrinsic.
This patch is simple && obvious.
Ok for trunk ?
gcc/ChangeLog:
On Tue, 16 May 2023 18:04:37 PDT (-0700), Vineet Gupta wrote:
+ Christoph, Jiawei
On 5/16/23 17:20, Palmer Dabbelt wrote:
We really need to add some CI around RV toolchains to trip on these
sooner !
Sounds like you're volunteering to set one up?
Patrick's github CI patch seems to be a
+ Christoph, Jiawei
On 5/16/23 17:20, Palmer Dabbelt wrote:
We really need to add some CI around RV toolchains to trip on these
sooner !
Sounds like you're volunteering to set one up?
Patrick's github CI patch seems to be a great start. Lets wait for it to
get merged, that will at least
The problem here is that VRP cannot figure out isize could not be 0
due to using integer_zerop. This patch removes the use of integer_zerop
and instead checks for 0 directly after converting the tree to
an unsigned HOST_WIDE_INT. This allows VRP to figure out isize is not 0
and `isize - 1` will
On Tue, 16 May 2023 17:16:11 PDT (-0700), Vineet Gupta wrote:
On 5/16/23 16:06, Palmer Dabbelt wrote:
A few of us were talking about test-related issues in the patchwork
meeting
this morning. I bumped to trunk and did a full rebuild, I'm getting the
following (it's in
On 5/16/23 16:06, Palmer Dabbelt wrote:
A few of us were talking about test-related issues in the patchwork
meeting
this morning. I bumped to trunk and did a full rebuild, I'm getting the
following (it's in riscv-systems-ci/riscv-gnu-toolchain). This is
about what I
remember seeing last
C2X removes a restriction that the only declarations in the
declaration part of a 'for' loop are declarations of objects with
storage class auto or register. Implement this change, making the
diagnostics into pedwarn_c11 calls instead of errors (as usual for
features added in a new standard
A few of us were talking about test-related issues in the patchwork meeting
this morning. I bumped to trunk and did a full rebuild, I'm getting the
following (it's in riscv-systems-ci/riscv-gnu-toolchain). This is about what I
remember seeing last time I ran the tests, which was a week or so
Hi, Kyrill.
It makes sense. I could add the classification to a different attribute as you
did and keep it in aarch64 as well.
I took the same approach, gleaning over several optimization guides for Arm
processors supporting SVE and figuring out the smallest number of types that
could cover
Hi Marek,
> On 16 May 2023, at 16:29, Marek Polacek via Gcc-patches
> wrote:
>
> Ping.
I’m trying this on Darwin (since I have a local patch to do this for modern
[darwin20+]
versions, which do not allow non-PIE)
I think you are missing a hunk to deal with Ada.
thanks for the patch
Iain
>
On 5/16/23 08:43, Stefan Schulze Frielinghaus wrote:
> So far atomic objects are aligned according to their default alignment.
> For 128 bit scalar types like int128 or long double this results in an
> 8 byte alignment which is wrong and must be 16 byte.
>
> libstdc++ already computes a correct
On 5/16/23 15:34, Jakub Jelinek wrote:
Hi!
My GCC 12 change to avoid removing zero-sized bitfields as they are
important for ABI and are needed for layout compatibility traits
apparently causes zero sized bitfields to be initialized in the IL,
which at least in 13+ results in ICEs in the ranger
On 5/16/23 15:13, Marek Polacek wrote:
In check_return_expr, we suppress the -Wdangling-reference warning when
we're sure it would be a false positive. It wasn't working in a
template, though, because the suppress_warning call was never reached.
Bootstrapped/regtested on x86_64-pc-linux-gnu,
Hi!
My GCC 12 change to avoid removing zero-sized bitfields as they are
important for ABI and are needed for layout compatibility traits
apparently causes zero sized bitfields to be initialized in the IL,
which at least in 13+ results in ICEs in the ranger which is upset
about zero precision
In check_return_expr, we suppress the -Wdangling-reference warning when
we're sure it would be a false positive. It wasn't working in a
template, though, because the suppress_warning call was never reached.
Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk and 13.2?
PR
Tested powerpc64le-linux. Builds OK on djgpp too.
Pushed to trunk.
-- >8 --
DJGPP (and maybe other targets) uses MAX_OFILE_ALIGNMENT=16 which means
that globals (and static objects) can't have alignment greater than 16.
This causes an error for the locks defined in src/c++11/shared_ptr.cc
Tested powerpc64le-linux. Builds OK for avr too.
Roger, does this work for xstormy16?
-- >8 --
libstdc++-v3/ChangeLog:
* acinclude.m4 (GLIBCXX_ZONEINFO_DIR): Extend logic for avr and
msp430 to all 16-bit targets.
* configure: Regenerate.
---
libstdc++-v3/acinclude.m4
rs6000: Enable REE pass by default
Add ree pass as a default pass for rs6000 target for
O2 and above.
2023-05-16 Ajit Kumar Agarwal
gcc/ChangeLog:
* common/config/rs6000/rs6000-common.cc: Add REE pass as a
default rs6000 target pass for O2 and above.
*
On 5/15/23 21:32, Jeff Law wrote:
On 5/9/23 10:01, Patrick O'Neill wrote:
Ping.
OK for backporting. Sorry for the delay.
jeff
Committed.
Thanks,
Patrick
On 5/16/23 11:38, Patrick Palka wrote:
add_list_candidates has logic to reject designated initialization of a
non-aggregate type, but this is inadvertendly being suppressed if the type
has a list constructor due to the order of case analysis, which in the
below testcase leads to us incorrectly
Update the PATCH v4 (I am sorry, missed the v4 in subject) as below with x86
bootstrap test passed.
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618742.html
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Li, Pan2 via Gcc-patches
Sent: Tuesday, May 16, 2023 8:17 PM
To:
add_list_candidates has logic to reject designated initialization of a
non-aggregate type, but this is inadvertendly being suppressed if the type
has a list constructor due to the order of case analysis, which in the
below testcase leads to us incorrectly treating the list initializer as
an
As promised in the --enable-host-pie patch, this patch adds another
configure option, --enable-host-bind-now, which adds -z now when linking
the compiler executables in order to extend hardening. BIND_NOW with RELRO
allows the GOT to be marked RO; this prevents GOT modification attacks.
This
From: Pan Li
We are running out of the machine_mode(8 bits) in RISC-V backend. Thus
we would like to extend the machine_mode bit size from 8 to 16 bits.
However, it is sensitive to extend the memory size in common structure
like tree or rtx. This patch would like to extend the machine_mode bits
Seems like I screw up bare-metal toolchian multi lib selection during
finxing linux multi-lib selction...
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_compute_multilib):
Fix wrong select_kind...
---
gcc/common/config/riscv/riscv-common.cc | 6 +++---
1 file
Ping.
On Tue, May 09, 2023 at 03:41:58PM -0400, Marek Polacek via Gcc-patches wrote:
> [ This is my third attempt to add this configure option. The first
> version was approved but it came too late in the development cycle.
> The second version was also approved, but I had to revert it:
>
Hi!
On Tue, May 16, 2023 at 11:45:28AM +0530, Ajit Agarwal wrote:
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -12455,8 +12455,8 @@ Attempt to remove redundant extension instructions.
> This is especially
> helpful for the x86-64 architecture, which implicitly zero-extends in
Following the similar support for C++ and Fortran, here is the
C implementation for the OpenMP 5.0 array-shaping operator, and for
strided and rectangular updates for "target update" directives.
Much of the implementation is shared with the previously-posted C++
support:
Hi!
On 2023-05-05T10:59:31+0200, I wrote:
> On 2023-05-05T10:55:41+0200, I wrote:
>> [Putting Bernhard, Honza, Segher in CC, as they are eager to test this,
>> based on recent comments on IRC.] ;-P
>> First, establish the parallel testing infrastructure -- while still
>> hard-coding the number
Hi!
OK to push the attached "Remove stale Autoconf checks for Perl"?
For avoidance of doubt, there still exist a few instances of Perl usage
in the GCC build process (like, when 'contrib/make_sunver.pl' is used),
but those always directly invoke 'perl'. As this, apparently, is working
fine,
On 24/04/2023 09:33, Richard Sandiford via Gcc-patches wrote:
Richard Sandiford writes:
Tamar Christina writes:
Hi All,
This patch adds support for a compact syntax for specifying constraints in
instruction patterns. Credit for the idea goes to Richard Earnshaw.
I am sending up this RFC to
Hi all,
We've recently sent up a lot of patches overhauling the testsuite of the
Arm MVE backend.
With these changes, we've also identified and fixed a number of bugs
(some backend bugs and many to do with the polymorphism of intrinsics in
MVE the header file).
These would all be relevant to
On 29/04/23 5:03 am, Jeff Law wrote:
>
>
> On 4/28/23 16:42, Hans-Peter Nilsson wrote:
>> On Sat, 22 Apr 2023, Ajit Agarwal via Gcc-patches wrote:
>>
>>> Hello All:
>>>
>>> This new version of patch 4 use improve ree pass for rs6000 target using
>>> defined ABI interfaces.
>>> Bootstrapped
Sorry for the slow reply.
Oluwatamilore Adebayo writes:
> From afa416dab831795f7e1114da2fb9e94ea3b8c519 Mon Sep 17 00:00:00 2001
> From: oluade01
> Date: Fri, 14 Apr 2023 15:10:07 +0100
> Subject: [PATCH 2/4] AArch64: New RTL for ABD
>
> This patch adds new RTL and tests for sabd and uabd
>
>
Thanks Richard Sandiford for review.
Yes, currently the class access_info will be extended from 8 bytes to 12 bytes,
which is missed in the table. With the adjustment as you suggested it will be 8
bytes but unfortunately the change of m_kind may trigger some ICE in some test
case(s).
I will
Tejas Belagod writes:
>>> + {
>>> + b = build3 (BIT_FIELD_REF, TREE_TYPE (f.lhs), val,
>>> + bitsize_int (step * BITS_PER_UNIT),
>>> + bitsize_int ((16 - step) * BITS_PER_UNIT));
>>> +
>>> + return gimple_build_assign (f.lhs, b);
>>> +
From: Richard Sandiford
Date: Tuesday, May 16, 2023 at 2:15 PM
To: Tejas Belagod
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] [PR96339] AArch64: Optimise svlast[ab]
Tejas Belagod writes:
>> + {
>> +int i;
>> +int nelts = vector_cst_encoded_nelts (v);
>> +int first_el = 0;
Hi, Richard. Forget about V10 patch. Just go directly V11 patch.
I am so sorry that I send V10 since I originally did not notice Case 2 and Case
3 are totally the same.
I apologize for that. I have reviewed V11 patch twice, it seems that this patch
is much more reasonable and better
On Tue, May 16, 2023 at 11:45:16AM +0200, Frederik Harwath wrote:
> The place where different compilers implement the loop transformations
> was discussed in an OpenMP loop transformation meeting last year. Two
> compilers (another one and GCC with this patch series) transformed the loops
> in the
I missed these two in g:4ff89f10ca0d41f9cfa76 because I was
testing on a system that didn't support big-endian compilation.
Testing on aarch64_be-elf shows no other related failures
(although the overall results are worse than for little-endian).
Tested on aarch64_be-elf & pushed.
Richard
Hi, Richard and Richi.
I am so sorry for sending you garbage patches (My mistake, sending RISC-V
patches to you).
I finally realize that Case 2 and Case 3 are totally the same sequence!
I have combined them into single function called "vect_adjust_loop_lens_control"
I have sent V11 patch:
From: Ju-Zhe Zhong
This patch implement decrement IV for length approach in loop control.
Address comment from kewen that incorporate the implementation inside
"vect_set_loop_controls_directly" instead of a standalone function.
Address comment from Richard using MIN_EXPR to handle these 3
From: Juzhe-Zhong
This patch is adding rounding mode operand and FRM_REGNUM dependency
into floating-point instructions.
The floating-point instructions we added FRM and rounding mode operand:
1. vfadd/vfsub
2. vfwadd/vfwsub
3. vfmul
4. vfdiv
5. vfwmul
6. vfwmacc/vfwnmacc/vfwmsac/vfwnmsac
7.
From: Juzhe-Zhong
This patch is adding rounding mode operand and FRM_REGNUM dependency
into floating-point instructions.
The floating-point instructions we added FRM and rounding mode operand:
1. vfadd/vfsub
2. vfwadd/vfwsub
3. vfmul
4. vfdiv
5. vfwmul
6. vfwmacc/vfwnmacc/vfwmsac/vfwnmsac
7.
Hi Jakub,
On 15.05.23 12:19, Jakub Jelinek wrote:
On Fri, Mar 24, 2023 at 04:30:38PM +0100, Frederik Harwath wrote:
this patch series implements the OpenMP 5.1 "unroll" and "tile"
constructs. It includes changes to the C,C++, and Fortran front end
for parsing the new constructs and a new
Hi, Richard.
I have sent V10:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618718.html
I can't combine implementation Case 2 and Case 3, Case 2 each control (len) are
coming from same rgc.
But Case 3 each control (len) are coming coming from different rgc.
Can you help me with that ?
On 5/15/23 20:14, Aldy Hernandez wrote:
On 5/15/23 17:07, Aldy Hernandez wrote:
On 5/15/23 12:42, Jakub Jelinek wrote:
On Mon, May 15, 2023 at 12:35:23PM +0200, Aldy Hernandez wrote:
gcc/ChangeLog:
PR tree-optimization/109695
* value-range.cc (irange::operator=): Resize range.
From: Ju-Zhe Zhong
This patch implement decrement IV for length approach in loop control.
Address comment from kewen that incorporate the implementation inside
"vect_set_loop_controls_directly" instead of a standalone function.
Address comment from Richard using MIN_EXPR to handle these 3
Tested powerpc64le-linux. Pushed to trunk.
-- >8 --
The _GLIBCXX_USE_C99_STDINT_TR1 macro (and the comments about it in
acinclude.m4 and config.h) are misleading when it is also used for
, not only . It is also wrong, because the
configure checks for TR1 use -std=c++98 and a target might define
Tested powerpc64le-linux. Pushed to trunk.
-- >8 --
As with the two commits before this, the _GLIBCXX_USE_C99_CTYPE_TR1 and
_GLIBCXX_USE_C99_FENV_TR1 macros are misleading when they are also used
for and , not only for TR1 headers. It is also wrong,
because the configure checks for TR1 use
Tested powerpc64le-linux. Pushed to trunk.
-- >8 --
The _GLIBCXX_USE_C99_COMPLEX_TR1 macro (and the comments about it in
acinclude.m4 and config.h) are misleading when it is also used for
, not only . It is also wrong, because the
configure checks for TR1 use -std=c++98 and a target might define
pan2...@intel.com writes:
> diff --git a/gcc/rtl-ssa/accesses.h b/gcc/rtl-ssa/accesses.h
> index c5180b9308a..38b4d6160c2 100644
> --- a/gcc/rtl-ssa/accesses.h
> +++ b/gcc/rtl-ssa/accesses.h
> @@ -254,7 +254,7 @@ private:
>unsigned int m_spare : 2;
>
>// The value returned by the
Tested x86_64-linux. Pushed to trunk.
-- >8 --
libstdc++-v3/ChangeLog:
* testsuite/ext/debug_allocator/check_deallocate_null.cc: Add
assertion to ensure expected exception is throw.
---
.../testsuite/ext/debug_allocator/check_deallocate_null.cc | 3 ++-
1 file changed, 2
Tested powerpc64le-linux. Pushed to trunk.
-- >8 --
libstdc++-v3/ChangeLog:
* testsuite/libstdc++-prettyprinters/chrono.cc: Only test
printer for chrono::zoned_time for cx11 ABI and tzdb effective
target.
---
libstdc++-v3/testsuite/libstdc++-prettyprinters/chrono.cc | 3
Tested powerpc64le-linux. Pushed to trunk.
-- >8 --
As noted in https://github.com/llvm/llvm-project/issues/62623 there are
no tsan interceptors for some of the new POSIX-1:202x APIs added by
https://austingroupbugs.net/view.php?id=1216 so tsan gives false
positive warnings for try_lock_for on
This patch removes the superfluous parallel in [u]divmod patterns
in the AVR backend. Effect of extra parallel is that add_clobbers
reaches gcc_unreachable() because the clobbers for [u]divmod are
missing. The parallel around the parts of an insn pattern is
implicit if it has multiple parts
From: Eric Botcazou
The problem is that the freeze node generated for the type of a static
subexpression present in the expression function is incorrectly placed
inside instead of outside the function.
gcc/ada/
* freeze.adb (Freeze_Expression): When the freezing is to be done
From: Eric Botcazou
This happens because the array component depends on a discriminant.
gcc/ada/
* exp_imgv.adb (Rewrite_Object_Image): If the prefix is a component
that depends on a discriminant, create an actual subtype for it.
Tested on x86_64-pc-linux-gnu, committed on
From: Yannick Moy
Following changes in GNATprove, proofs need to be amended.
gcc/ada/
* libgnat/s-aridou.adb (Lemma_Div_Pow2): Add assertion.
* libgnat/s-arit32.adb (Lemma_Abs_Div_Commutation): Simplify.
* libgnat/s-expmod.adb (Lemma_Exp_Mod): Add assertions.
From: Steve Baird
The output generated by "gnat --help-ada" should include descriptions for
the newly added -gnatw_s and -gnatw_S switches".
gcc/ada/
* usage.adb: Generate output text describing the -gnatw_s switch
(and the corresponding -gnatw_S switch).
Tested on
From: Eric Botcazou
It avoids to recreate an actual subtype for an explicit dereference.
gcc/ada/
* sem_util.adb (Get_Actual_Subtype): For an explicit dereference,
return the Actual_Designated_Subtype if it is present.
(Get_Actual_Subtype_If_Available): Likewise.
Tejas Belagod writes:
>> + {
>> +int i;
>> +int nelts = vector_cst_encoded_nelts (v);
>> +int first_el = 0;
>> +
>> +for (i = first_el; i < nelts; i += step)
>> + if (VECTOR_CST_ENCODED_ELT (v, i) != VECTOR_CST_ENCODED_ELT (v,
> first_el))
>
> I think this should use
From: Eric Botcazou
The preanalysis of a predicate set on one of the record types was causing
premature freezing of another record type.
gcc/ada/
* sem_ch13.adb: Add with and use clauses for Expander.
(Resolve_Aspect_Expressions) : Emulate a
bona-fide preanalysis setup
From: Eric Botcazou
This makes the following adjustments to the semantics and implementation of
storage models in the compiler:
1. By-copy semantics in subprogram calls: when an object accessed with a
nonnative storage model is passed as an actual parameter in a call to
a
From: Eric Botcazou
The current expansion of the 'Reduce attribute uses the resolution type of
the expression for the accumulator. Now this type can be unresolved or set
to a universal type, for example if it is itself the prefix of the 'Image
attribute, and this may yield a spurious type
From: Javier Miranda
gcc/ada/
* exp_ch6.adb
(Needs_BIP_Alloc_Form): Return False for functions with foreign
convention since we never use build-in-place for such functions.
Tested on x86_64-pc-linux-gnu, committed on master.
---
gcc/ada/exp_ch6.adb | 7 ++-
1 file
From: Piotr Trojanek
Invariant procedure bodies are created either by expansion of freezing
nodes (but only in ordinary compilation mode) or at the end of package
private declarations (but not for with private types in the type
derivation chain).
In GNATprove mode we didn't create invariant
From: Javier Miranda
gcc/ada/
* sem_attr.adb
(Analyze_Attribute_Old_Result): When preanalyzing a class-wide
condition, search in the scopes stack for the subprogram that has
the condition. This is required because returning the current
scope causes
From: Piotr Trojanek
When preanalyzing expressions in GNATprove mode, e.g. Pre/Post
contracts, we apply checks, because these expressions will never
be expanded. This didn't happen for aggregate expressions, most
likely because of an oversight.
gcc/ada/
* sem_util.adb
From: Eric Botcazou
gcc/ada/
* doc/gnat_rm/standard_and_implementation_defined_restrictions.rst
(No_Dependence): Give examples of new No_Dependence restrictions.
* gnat_rm.texi: Regenerate.
Tested on x86_64-pc-linux-gnu, committed on master.
---
From: Ghjuvan Lacambre
-gnatyD was documented in the user guide but not in `gnat --help-ada`.
gcc/ada/
* usage.adb (Usage): Document -gnatyD.
Tested on x86_64-pc-linux-gnu, committed on master.
---
gcc/ada/usage.adb | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Johannes Kliemann
gcc/ada/
* libgnat/system-linux-ppc.ads: Add Support_Atomic_Primitives.
* libgnat/s-atopri__32.ads: Add 32 bit version of s-atopri.ads.
* Makefile.rtl: Use s-atopro__32.ads for ppc-linux.
Tested on x86_64-pc-linux-gnu, committed on master.
---
1 - 100 of 137 matches
Mail list logo
