Re: [PATCH, rs6000] Call vector load/store with length expand only on 64-bit Power10 [PR96762]

Kewen, I refined the patch according to your comments and it passed bootstrap and regression test. I committed it as https://gcc.gnu.org/g:946b8967b905257ac9f140225db744c9a6ab91be Thanks Gui Haochen 在 2023/8/29 16:55, Kewen.Lin 写道: > Hi Haochen, > > on 2023/8/29 10:50, HAO CHEN GUI wrote:

Re: [PATCH V5 1/2] Add overflow API for plus minus mult on range

On 2023-08-03 21:18, Andrew MacLeod wrote: This is OK. Thanks a lot! Committed via r14-3582. BR, Jeff (Jiufu Guo) On 8/2/23 22:18, Jiufu Guo wrote: Hi, I would like to have a ping on this patch. BR, Jeff (Jiufu Guo) Jiufu Guo writes: Hi, As discussed in previous reviews, adding

[committed] arc: Honor SWAP option for lsl16 instruction

The LSL16 instruction is only available if SWAP (-mswap) option is turned on. gcc/ChangeLog: * config/arc/arc.cc (arc_split_mov_const): Use LSL16 only when SWAP option is enabled. * config/arc/arc.md (ashlsi2_cnt16): Likewise. Signed-off-by: Claudiu Zissulescu ---

Re: [PATCH v4] LoongArch:Implement 128-bit floating point functions in gcc.

On Thu, 2023-08-31 at 10:46 +0800, chenxiaolong wrote: > +;; Implement __builtin_fabs128 function. > + > +(define_expand "abstf2" > +  [(match_operand:TF 0 "register_operand") > +   (match_operand:TF 1 "register_operand")] > +  "TARGET_64BIT" > +{ > +  loongarch_emit_move (operands[0],

[PATCH v2] RISC-V: Optimize the MASK opt generation

This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt generation". Please check the detail info on the "https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg302295.html; gcc/ChangeLog: * config/riscv/riscv-opts.h (MASK_ZICSR): (MASK_ZIFENCEI): Delete;

Re: [PING][PATCH] LoongArch: initial ada support on linux

ping? 在 2023/8/25 下午1:55, Yujie Yang 写道: Hi! I'd like to ping this patch for acknowledgement from the Ada team. We have successfully compiled a cross-native toolchain with Ada enabled for loongarch64-linux-gnuf64 (or loongarch64-linux-gnu), and have run the regtests with the following

Re: [PATCH v2 1/4] LoongArch: improved target configuration interface

On Wed, Aug 30, 2023 at 09:36:22PM +, Joseph Myers wrote: > On Wed, 30 Aug 2023, Yang Yujie wrote: > > > +A suffix @code{[/ARCH][/OPTION]...]} may follow immediately after the ABI > > +identifier to customize the compiler options for building the given set of > > +libraries. @code{ARCH}

[PATCH v4] LoongArch:Implement 128-bit floating point functions in gcc.

Brief version history of patch set: v1 -> v2: According to the GNU code specification, adjust the format of the function implementation with "q" as the suffix function. v2 - >v3: 1.On the LoongArch architecture, refer to the functionality of 64-bit functions and modify the underlying

Re: [PATCH] RISC-V: Fix vsetvl pass ICE

Committed to the trunk and backported to GCC 13 one week later. Thanks Juzhe and Kito. On 2023/8/31 9:44, Kito Cheng via Gcc-patches wrote: OK for gcc 13 branch too, the general rule for backport is to wait one week on trunk to make sure the fix is stable. On Thu, Aug 31, 2023 at 8:08 AM

Re: [PATCH] RISC-V: Fix vsetvl pass ICE

OK for gcc 13 branch too, the general rule for backport is to wait one week on trunk to make sure the fix is stable. On Thu, Aug 31, 2023 at 8:08 AM juzhe.zh...@rivai.ai wrote: > > Ok for trunk. But not sure whether it's ok for GCC-13. > > > > juzhe.zh...@rivai.ai > > From: Lehua Ding > Date:

[r14-3571 Regression] FAIL: gcc.target/i386/pr52252-atom.c scan-assembler palignr on Linux/x86_64

On Linux/x86_64, caa7a99a052929d5970677c5b639e1fa5166e334 is the first bad commit commit caa7a99a052929d5970677c5b639e1fa5166e334 Author: Richard Biener Date: Wed Aug 30 11:57:47 2023 +0200 tree-optimization/111228 - combine two VEC_PERM_EXPRs caused FAIL: gcc.target/i386/pr52252-atom.c

RE: [EXTERNAL] Check that passes do not forget to define profile

Hi Jan, These new checks are too strong for AutoFDO. For example, the edge probabilities are not guaranteed to be initialized (see afdo_calculate_branch_prob). This currently breaks autoprofiledbootstrap build. I suggest removing cfun->cfg->full_profile = true; from auto-profile.cc.

Re: [PATCH] RISC-V: Fix vsetvl pass ICE

Ok for trunk. But not sure whether it's ok for GCC-13. juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-08-30 17:51 To: gcc-patches CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw Subject: [PATCH] RISC-V: Fix vsetvl pass ICE This patch fix pr111234 (a vsetvl pass ICE) when fuse a

[RFC PATCH v2 1/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support

From: Tsukasa OI 'XVentanaCondOps' is a vendor extension from Ventana Micro Systems containing two instructions for conditional move and will be supported on their Veyron V1 CPU. And most notably (for historical reasons), 'XVentanaCondOps' and the standard 'Zicond' extension are functionally

[RFC PATCH v2 0/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support

PATCH v1: Changes: v1 -> v2 * Removed bogus opt2 pattern as pointed out in: note that this is not in the ChangeLog expecting the patch above

[PATCH] rs6000: Update instruction counts to match vec_* calls [PR111228]

Commit r14-3258-ge7a36e4715c716 increased the amount of folding we perform, leading to better code. Update the expected instruction counts to match the the number of associated vec_* built-in calls. Tested on powerpc64le-linux with no regressions. Ok for mainline? Peter gcc/testsuite/

Re: RFC: Top level configure: Require a minimum version 6.8 texinfo

> "Eric" == Eric Gallager via Gdb-patches > writes: Eric> Just as a point of reference, but the default makeinfo shipped with Eric> macOS (/usr/bin/makeinfo) is stuck at version 4.8 due to the whole Eric> GPL3 transition. The other makeinfos that I have installed are: [...] I think

[PATCH] MATCH: extend min_value/max_value match to vectors

This simple patch extends the min_value/max_value match to vector integer types. Using uniform_integer_cst_p makes this easy. OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions. The testcases pr110915-*.c are the same as pr88784-*.c except using vector types instead. PR

Re: [PATCH] analyzer: implement reference count checking for CPython plugin [PR107646]

On Tue, Aug 29, 2023 at 5:14 PM David Malcolm wrote: > > On Tue, 2023-08-29 at 13:28 -0400, Eric Feng wrote: > > Additionally, by using the old model and the pointer per your > > suggestion, > > we are able to find the representative tree and emit a more accurate > > diagnostic! > > > >

[PATCH] RISC-V: zicond: remove bogus opt2 pattern

This was tripping up gcc.c-torture/execute/pr60003.c at -O1 since the pattern semantics can't be expressed by zicond instructions. This involves test code snippet: if (a == 0) return 0; else return x; } which is equivalent to: "x = (a != 0) ? x : a" and matches

Re: Analyzer failure due to missing header

On Wed, 2023-08-30 at 23:24 +0200, FX Coudert wrote: > > std::max and std::min, introduced by d99d73c77d1e and 2bad0eeb5573, > > are not available because is not included. > > I originally thought this was only seen in cross-compilers, but it > actually broke bootstrap on darwin. > Attached

Re: [PATCH v2 1/4] LoongArch: improved target configuration interface

On Wed, 30 Aug 2023, Yang Yujie wrote: > +A suffix @code{[/ARCH][/OPTION]...]} may follow immediately after the ABI > +identifier to customize the compiler options for building the given set of > +libraries. @code{ARCH} denotes the architecture name recognized by the > +@code{-march=ARCH}

Re: Analyzer failure due to missing header

> std::max and std::min, introduced by d99d73c77d1e and 2bad0eeb5573, are not > available because is not included. I originally thought this was only seen in cross-compilers, but it actually broke bootstrap on darwin. Attached patch restores it, OK to commit? FX

Re: [PATCH] c++: Check for indirect change of active union member in constexpr [PR101631]

On 8/29/23 09:35, Nathaniel Shead wrote: This is an attempt to improve the constexpr machinery's handling of union lifetime by catching more cases that cause UB. Is this approach OK? I'd also like some feedback on a couple of pain points with this implementation; in particular, is there a good

[committed] pru: Add cstore expansion patterns

Add cstore patterns for the two specific operations which can be efficiently expanded using the UMIN instruction: X != 0 X == 0 The rest of the operations are rejected, and left to be expanded by the common expansion code. Reg-tested pru-unknown-elf. Pushed to trunk. PR

Re: [PATCH] c++: CWG 2359, wrong copy-init with designated init [PR91319]

On Tue, Aug 29, 2023 at 04:44:11PM -0400, Jason Merrill wrote: > On 8/28/23 19:09, Marek Polacek wrote: > > On Mon, Aug 28, 2023 at 06:27:26PM -0400, Jason Merrill wrote: > > > On 8/25/23 12:44, Marek Polacek wrote: > > > > Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? > > > > > >

Re: [PATCH] expmed: Allow extract_bit_field via mem for low-precision modes.

Robin Dapp writes: >> But in the VLA case, doesn't it instead have precision 4+4X? >> The problem then is that we can't tell at compile time which >> byte that corresponds to. So... > > Yes 4 + 4x. I keep getting confused with poly modes :) > In this case we want to extract the bitnum [3 4] = 3

Re: [PATCH] expmed: Allow extract_bit_field via mem for low-precision modes.

> But in the VLA case, doesn't it instead have precision 4+4X? > The problem then is that we can't tell at compile time which > byte that corresponds to. So... Yes 4 + 4x. I keep getting confused with poly modes :) In this case we want to extract the bitnum [3 4] = 3 + 4x which would be in byte

Re: [PATCH 6/8] vect: Add vector_mode paramater to simd_clone_usable

On 30/08/2023 14:01, Richard Biener wrote: On Wed, Aug 30, 2023 at 11:15 AM Andre Vieira (lists) via Gcc-patches wrote: This patch adds a machine_mode parameter to the TARGET_SIMD_CLONE_USABLE hook to enable rejecting SVE modes when the target architecture does not support SVE. How does

Re: [pushed] analyzer: fix ICE in text art strings support

On Wed, 2023-08-30 at 11:52 +0530, Prathamesh Kulkarni wrote: > On Wed, 30 Aug 2023 at 04:21, David Malcolm > wrote: > > > > On Tue, 2023-08-29 at 11:01 +0530, Prathamesh Kulkarni wrote: > > > On Fri, 25 Aug 2023 at 18:15, David Malcolm via Gcc-patches > > > wrote: > > > > > > > > Successfully

Re: [PATCH] c++: disallow constinit on functions [PR111173]

On 8/29/23 15:01, Marek Polacek wrote: Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? OK. -- >8 -- [dcl.constinit]/1: The constinit specifier shall be applied only to a declaration of a variable with static or thread storage duration. and while we detect constinit int

RE: [PATCH] expmed: Allow extract_bit_field via mem for low-precision modes.

[Sorry for any weird MUA issues, don't have access to my usual set-up.] > when looking at a riscv ICE in vect-live-6.c I noticed that we > assume that the variable part (coeffs[1] * x1) of the to-be-extracted > bit number in extract_bit_field_1 is a multiple of BITS_PER_UNIT. > > This means that

Re: RFC: Introduce -fhardened to enable security-related flags

On Wed, Aug 30, 2023 at 12:51 PM Jakub Jelinek via Gcc-patches wrote: > > On Tue, Aug 29, 2023 at 03:42:27PM -0400, Marek Polacek via Gcc-patches wrote: > > + if (UNLIKELY (flag_hardened) > > + && (opt->code == OPT_D || opt->code == OPT_U)) > > + { > > + if

Re: [PATCH7/8] vect: Add TARGET_SIMD_CLONE_ADJUST_RET_OR_PARAM

On Wed, 30 Aug 2023, Andre Vieira (lists) wrote: > This patch adds a new target hook to enable us to adapt the types of return > and parameters of simd clones. We use this in two ways, the first one is to > make sure we can create valid SVE types, including the SVE type attribute, > when

Re: [PATCH 6/8] vect: Add vector_mode paramater to simd_clone_usable

On Wed, Aug 30, 2023 at 11:15 AM Andre Vieira (lists) via Gcc-patches wrote: > > This patch adds a machine_mode parameter to the TARGET_SIMD_CLONE_USABLE > hook to enable rejecting SVE modes when the target architecture does not > support SVE. How does the graph node of the SIMD clone lack this

Re: [PATCH 4/8] vect: don't allow fully masked loops with non-masked simd clones [PR 110485]

On Wed, 30 Aug 2023, Andre Vieira (lists) wrote: > When analyzing a loop and choosing a simdclone to use it is possible to choose > a simdclone that cannot be used 'inbranch' for a loop that can use partial > vectors. This may lead to the vectorizer deciding to use partial vectors > which are

Re: [Patch 3/8] vect: Fix vect_get_smallest_scalar_type for simd clones

On Wed, 30 Aug 2023, Andre Vieira (lists) wrote: > The vect_get_smallest_scalar_type helper function was using any argument to a > simd clone call when trying to determine the smallest scalar type that would > be vectorized. This included the function pointer type in a MASK_CALL for > instance,

Re: [Patch] OpenMP (C only): omp allocate - handle stack vars, improve diagnostic

Attached is an incremental patch to add diagnostic for the in-between allocator issues, i.e. On 30.08.23 12:47, Tobias Burnus wrote: omp_allocator_handle_t uninit; int var, var2; uninit = omp_low_lat_mem_alloc; omp_allocator_handle_t late_declared = omp_low_lat_mem_alloc; #pragma omp

RE: [PATCH] test: Adapt slp-26.c check for RVV

Committed, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Wednesday, August 30, 2023 8:23 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH] test: Adapt slp-26.c check for RVV On Wed, 30 Aug 2023,

RE: [PATCH] test: Add xfail into slp-reduc-7.c for RVV VLA vectorization

Committed, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Wednesday, August 30, 2023 8:23 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH] test: Add xfail into slp-reduc-7.c for RVV VLA vectorization On

Re: [Patch 2/8] parloops: Allow poly nit and bound

On Wed, 30 Aug 2023, Andre Vieira (lists) wrote: > Teach parloops how to handle a poly nit and bound e ahead of the changes to > enable non-constant simdlen. Can you use poly_int_tree_p to combine INTEGER_CST || POLY_INT_CST please? OK with that change. > gcc/ChangeLog: > > *

Re: [PATCH 1/8] parloops: Copy target and optimizations when creating a function clone

On Wed, 30 Aug 2023, Andre Vieira (lists) wrote: > > SVE simd clones require to be compiled with a SVE target enabled or the > argument types will not be created properly. To achieve this we need to copy > DECL_FUNCTION_SPECIFIC_TARGET from the original function declaration to the > clones. I

Re: [PATCH] tree-optimization/111228 - combine two VEC_PERM_EXPRs

On Wed, 30 Aug 2023, Jakub Jelinek wrote: > On Wed, Aug 30, 2023 at 01:54:46PM +0200, Richard Biener via Gcc-patches > wrote: > > * gcc.dg/tree-ssa/forwprop-42.c: New testcase. > > > --- /dev/null > > +++ b/gcc/testsuite/gcc.dg/tree-ssa/forwprop-42.c > > @@ -0,0 +1,17 @@ > > +/* { dg-do

Re: [PATCH] test: Add xfail into slp-reduc-7.c for RVV VLA vectorization

On Wed, 30 Aug 2023, Juzhe-Zhong wrote: > Like ARM SVE, add RVV variable length xfail. OK > gcc/testsuite/ChangeLog: > > * gcc.dg/vect/slp-reduc-7.c: Add RVV. > > --- > gcc/testsuite/gcc.dg/vect/slp-reduc-7.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git

Re: [PATCH] test: Adapt slp-26.c check for RVV

On Wed, 30 Aug 2023, Juzhe-Zhong wrote: > Fix FAILs: > FAIL: gcc.dg/vect/slp-26.c -flto -ffat-lto-objects scan-tree-dump-times vect > "vectorized 0 loops" 1 > FAIL: gcc.dg/vect/slp-26.c -flto -ffat-lto-objects scan-tree-dump-times vect > "vectorizing stmts using SLP" 0 > FAIL:

[PATCH] expmed: Allow extract_bit_field via mem for low-precision modes.

Hi, when looking at a riscv ICE in vect-live-6.c I noticed that we assume that the variable part (coeffs[1] * x1) of the to-be-extracted bit number in extract_bit_field_1 is a multiple of BITS_PER_UNIT. This means that bits_to_bytes_round_down and num_trailing_bits cannot handle e.g. extracting

Re: [PATCH] Adjust costing of emulated vectorized gather/scatter

On Wed, Aug 30, 2023 at 12:38 PM liuhongt via Gcc-patches wrote: > > r14-332-g24905a4bd1375c adjusts costing of emulated vectorized > gather/scatter. > > commit 24905a4bd1375ccd99c02510b9f9529015a48315 > Author: Richard Biener > Date: Wed Jan 18 11:04:49 2023 +0100 > > Adjust costing

Re: [PATCH] tree-optimization/111228 - combine two VEC_PERM_EXPRs

On Wed, Aug 30, 2023 at 01:54:46PM +0200, Richard Biener via Gcc-patches wrote: > * gcc.dg/tree-ssa/forwprop-42.c: New testcase. > --- /dev/null > +++ b/gcc/testsuite/gcc.dg/tree-ssa/forwprop-42.c > @@ -0,0 +1,17 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O -fdump-tree-cddce1" } */

[PATCH V6] RISC-V: Enable vec_int testsuite for RVV VLA vectorization

This patch is the final version of enabling vect_int test for RVV. There are still 80+ FAILs and they can't be fixed by adjusting testcases or target-supports.exp Here is the analysis of **ALL** FAILs: 1. REAL highest priority FAILs: ICE: FAIL: gcc.dg/vect/vect-live-6.c (internal compiler

[PATCH] tree-optimization/111228 - combine two VEC_PERM_EXPRs

The following adds simplification of two VEC_PERM_EXPRs where the later one replaces all elements from either the first or the second input of the earlier permute. This allows a three input permute to be simplified to a two input one. I'm following the existing two input simplification case and

[PATCH] RISC-V: Refactor and clean emit_{vlmax, nonvlmax}_xxx functions

Hi, This patch refactor the code of emit_{vlmax,nonvlmax}_xxx functions. These functions are used to generate RVV insn. There are currently 31 such functions and a few duplicates. The reason so many functions are needed is because there are more types of RVV instructions. There are patterns that

[PATCH] test: Add xfail into slp-reduc-7.c for RVV VLA vectorization

Like ARM SVE, add RVV variable length xfail. gcc/testsuite/ChangeLog: * gcc.dg/vect/slp-reduc-7.c: Add RVV. --- gcc/testsuite/gcc.dg/vect/slp-reduc-7.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.dg/vect/slp-reduc-7.c

[PATCH] test: Adapt slp-26.c check for RVV

Fix FAILs: FAIL: gcc.dg/vect/slp-26.c -flto -ffat-lto-objects scan-tree-dump-times vect "vectorized 0 loops" 1 FAIL: gcc.dg/vect/slp-26.c -flto -ffat-lto-objects scan-tree-dump-times vect "vectorizing stmts using SLP" 0 FAIL: gcc.dg/vect/slp-26.c scan-tree-dump-times vect "vectorized 0 loops"

Re: [Patch] OpenMP (C only): omp allocate - handle stack vars, improve diagnostic

On Wed, Aug 30, 2023 at 12:47:42PM +0200, Tobias Burnus wrote: > > For switches, there is the case of the switch jumping across declaration > > of an automatic var which is not initialized/constructed (I think in that > > case there is normally no warning/error and happens a lot in the wild > >

Re: RFC: Introduce -fhardened to enable security-related flags

On Tue, Aug 29, 2023 at 03:42:27PM -0400, Marek Polacek via Gcc-patches wrote: > + if (UNLIKELY (flag_hardened) > + && (opt->code == OPT_D || opt->code == OPT_U)) > + { > + if (!fortify_seen_p) > + fortify_seen_p = !strncmp (opt->arg,

Re: [PATCH] RISC-V: Remove movmisalign pattern for VLA modes

Committed, thanks Jeff. On 2023/8/29 21:48, Jeff Law via Gcc-patches wrote: On 8/29/23 03:39, Juzhe-Zhong wrote: This patch fixed this bunch of failures in "vect" testsuite: FAIL: gcc.dg/vect/pr63341-1.c -flto -ffat-lto-objects execution test FAIL: gcc.dg/vect/pr63341-1.c execution test

Re: [Patch] OpenMP (C only): omp allocate - handle stack vars, improve diagnostic

Revised patch included - addresses part of the issues: * gimplify.cc: Fix placement of GOMP_alloc by really checking for DECL_EXPR (experimented with it before but settled for a different pattern) * c/ Add it to has_jump_unsafe_decl similar to VLA + added msg to the switch/goto error

[PATCH] Adjust costing of emulated vectorized gather/scatter

r14-332-g24905a4bd1375c adjusts costing of emulated vectorized gather/scatter. commit 24905a4bd1375ccd99c02510b9f9529015a48315 Author: Richard Biener Date: Wed Jan 18 11:04:49 2023 +0100 Adjust costing of emulated vectorized gather/scatter Emulated gather/scatter behave similar

RE: [PATCH] test: Add xfail for riscv_vector

Committed, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Wednesday, August 30, 2023 4:36 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH] test: Add xfail for riscv_vector On Wed, 30 Aug 2023, Juzhe-Zhong

RE: [PATCH] test: Fix XPASS of RVV

Committed, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Wednesday, August 30, 2023 6:24 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH] test: Fix XPASS of RVV On Wed, 30 Aug 2023, Juzhe-Zhong wrote: >

Re: [PATCH v2 0/2] ifcvt: Allow if conversion of arithmetic in basic blocks with multiple sets

On Tue, Jul 18, 2023 at 9:38 PM Richard Sandiford wrote: > > Manolis Tsamis writes: > > On Tue, Jul 18, 2023 at 1:12 AM Richard Sandiford > > wrote: > >> > >> Manolis Tsamis writes: > >> > noce_convert_multiple_sets has been introduced and extended over time to > >> > handle > >> > if

Re: [PATCH] test: Fix XPASS of RVV

On Wed, 30 Aug 2023, Juzhe-Zhong wrote: > XPASS: gcc.dg/vect/vect-outer-4e.c -flto -ffat-lto-objects > scan-tree-dump-times vect "OUTER LOOP VECTORIZED" 1 > XPASS: gcc.dg/vect/vect-outer-4e.c scan-tree-dump-times vect "OUTER LOOP > VECTORIZED" 1 > XPASS: gcc.dg/vect/vect-outer-4f.c -flto

[PATCH v3 3/4] ifcvt: Handle multiple rewired regs and refactor noce_convert_multiple_sets

The existing implementation of need_cmov_or_rewire and noce_convert_multiple_sets_1 assumes that sets are either REG or SUBREG. This commit enchances them so they can handle/rewire arbitrary set statements. To do that a new helper struct noce_multiple_sets_info is introduced which is used by

[PATCH v3 4/4] ifcvt: Remove obsolete code for subreg handling in noce_convert_multiple_sets

This code used to handle register replacement issues with SUBREG before simplify_replace_rtx was introduced. This should not be needed anymore as new_val has the correct mode and that should be preserved by simplify_replace_rtx. gcc/ChangeLog: * ifcvt.cc (noce_convert_multiple_sets_1):

[PATCH v3 2/4] ifcvt: Allow more operations in multiple set if conversion

Currently the operations allowed for if conversion of a basic block with multiple sets are few, namely REG, SUBREG and CONST_INT (as controlled by bb_ok_for_noce_convert_multiple_sets). This commit allows more operations (arithmetic, compare, etc) to participate in if conversion. The target's

[PATCH v3 1/4] ifcvt: handle sequences that clobber flags in noce_convert_multiple_sets

This is an extension of what was done in PR106590. Currently if a sequence generated in noce_convert_multiple_sets clobbers the condition rtx (cc_cmp or rev_cc_cmp) then only seq1 is used afterwards (sequences that emit the comparison itself). Since this applies only from the next iteration it

[PATCH v3 0/4] ifcvt: Allow if conversion of arithmetic in basic blocks with multiple sets

noce_convert_multiple_sets has been introduced and extended over time to handle if conversion for blocks with multiple sets. Currently this is focused on register moves and rejects any sort of arithmetic operations. This series is an extension to allow more sequences to take part in if

Re: [PATCH 0/3] [RISC-V] support zcmp extension

Pass regression without introducing any new fail, push to trunk :) On Tue, Aug 29, 2023 at 4:39 PM Fei Gao wrote: > > Fei Gao (3): > [RISC-V] support cm.push cm.pop cm.popret in zcmp > [RISC-V] support cm.popretz in zcmp > [RISC-V] support cm.mva01s cm.mvsa01 in zcmp > >

Re: [PATCH v2 3/4] LoongArch: add new configure option --with-strict-align-lib

On Wed, Aug 30, 2023 at 04:22:13PM +0800, Xi Ruoyao wrote: > On Wed, 2023-08-30 at 14:51 +0800, Yujie Yang wrote: > > > > LoongArch processors may not support memory accesses without natural > > > > alignments.  Building libraries with -mstrict-align may help with > > > > toolchain binary

[PATCH] test: Fix XPASS of RVV

XPASS: gcc.dg/vect/vect-outer-4e.c -flto -ffat-lto-objects scan-tree-dump-times vect "OUTER LOOP VECTORIZED" 1 XPASS: gcc.dg/vect/vect-outer-4e.c scan-tree-dump-times vect "OUTER LOOP VECTORIZED" 1 XPASS: gcc.dg/vect/vect-outer-4f.c -flto -ffat-lto-objects scan-tree-dump-times vect "OUTER

[PATCH] RISC-V: Fix vsetvl pass ICE

This patch fix pr111234 (a vsetvl pass ICE) when fuse a mask any vlmax vsetvl_vtype_change_only insn with a mu vsetvl insn. PR target/111234 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Remove condition. gcc/testsuite/ChangeLog: *

RE: [PATCH] [tree-optimization/110279] swap operands in reassoc to reduce cross backedge FMA

Hello Richard, > -Original Message- > From: Richard Biener > Sent: Tuesday, August 29, 2023 7:11 PM > To: Di Zhao OS > Cc: Jeff Law ; Martin Jambor ; gcc- > patc...@gcc.gnu.org > Subject: Re: [PATCH] [tree-optimization/110279] swap operands in reassoc to > reduce cross backedge FMA > >

[PATCH 8/8] aarch64: Add SVE support for simd clones [PR 96342]

This patch finalizes adding support for the generation of SVE simd clones when no simdlen is provided, following the ABI rules where the widest data type determines the minimum amount of elements in a length agnostic vector. gcc/ChangeLog: * config/aarch64/aarch64-protos.h

[PATCH7/8] vect: Add TARGET_SIMD_CLONE_ADJUST_RET_OR_PARAM

This patch adds a new target hook to enable us to adapt the types of return and parameters of simd clones. We use this in two ways, the first one is to make sure we can create valid SVE types, including the SVE type attribute, when creating a SVE simd clone, even when the target options do

Re: [PATCH 6/8] vect: Add vector_mode paramater to simd_clone_usable

Forgot to CC this one to maintainers... On 30/08/2023 10:14, Andre Vieira (lists) via Gcc-patches wrote: This patch adds a machine_mode parameter to the TARGET_SIMD_CLONE_USABLE hook to enable rejecting SVE modes when the target architecture does not support SVE. gcc/ChangeLog: *

[PATCH 6/8] vect: Add vector_mode paramater to simd_clone_usable

This patch adds a machine_mode parameter to the TARGET_SIMD_CLONE_USABLE hook to enable rejecting SVE modes when the target architecture does not support SVE. gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_simd_clone_usable): Add mode parameter and use to to reject SVE

[PATCH 5/8] vect: Use inbranch simdclones in masked loops

This patch enables the compiler to use inbranch simdclones when generating masked loops in autovectorization. gcc/ChangeLog: * omp-simd-clone.cc (simd_clone_adjust_argument_types): Make function compatible with mask parameters in clone. * tree-vect-stmts.cc

[PATCH 4/8] vect: don't allow fully masked loops with non-masked simd clones [PR 110485]

When analyzing a loop and choosing a simdclone to use it is possible to choose a simdclone that cannot be used 'inbranch' for a loop that can use partial vectors. This may lead to the vectorizer deciding to use partial vectors which are not supported for notinbranch simd clones. This patch

[Patch 3/8] vect: Fix vect_get_smallest_scalar_type for simd clones

The vect_get_smallest_scalar_type helper function was using any argument to a simd clone call when trying to determine the smallest scalar type that would be vectorized. This included the function pointer type in a MASK_CALL for instance, and would result in the wrong type being selected.

[Patch 2/8] parloops: Allow poly nit and bound

Teach parloops how to handle a poly nit and bound e ahead of the changes to enable non-constant simdlen. gcc/ChangeLog: * tree-parloops.cc (try_to_transform_to_exit_first_loop_alt): Accept poly NIT and ALT_BOUND.diff --git a/gcc/tree-parloops.cc b/gcc/tree-parloops.cc index

Re: RFC: Introduce -fhardened to enable security-related flags

On Tue, 2023-08-29 at 15:42 -0400, Marek Polacek via Gcc-patches wrote: > + if (UNLIKELY (flag_hardened) > + && (opt->code == OPT_D || opt->code == OPT_U)) > +   { > + if (!fortify_seen_p) > +   fortify_seen_p = !strncmp (opt->arg,

[PATCH 1/8] parloops: Copy target and optimizations when creating a function clone

SVE simd clones require to be compiled with a SVE target enabled or the argument types will not be created properly. To achieve this we need to copy DECL_FUNCTION_SPECIFIC_TARGET from the original function declaration to the clones. I decided it was probably also a good idea to copy

aarch64, vect, omp: Add SVE support for simd clones [PR 96342]

Hi, This patch series aims to implement support for SVE simd clones when not specifying a 'simdlen' clause for AArch64. This patch depends on my earlier patch: '[PATCH] aarch64: enable mixed-types for aarch64 simdclones'. Bootstrapped and regression tested the series on

[PATCH] Refactor vector HF/BF mode iterators and patterns.

Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ready push to trunk. gcc/ChangeLog: * config/i386/sse.md (_blendm): Merge VF_AVX512HFBFVL into VI12HFBF_AVX512VL. (VF_AVX512HFBF16): Renamed to VHFBF. (VF_AVX512FP16VL): Renamed to VHF_AVX512VL.

Re: RFC: Introduce -fhardened to enable security-related flags

> Improving the security of software has been a major trend in the recent > years. Fortunately, GCC offers a wide variety of flags that enable extra > hardening. These flags aren't enabled by default, though. And since > there are a lot of hardening flags, with more to come, it's been difficult

Re: [PATCH] tree-ssa-strlen: Fix up handling of conditionally zero memcpy [PR110914]

On Wed, 30 Aug 2023, Jakub Jelinek wrote: > Hi! > > The following testcase is miscompiled since r279392 aka > r10-5451-gef29b12cfbb4979 > The strlen pass has adjust_last_stmt function, which performs mainly strcat > or strcat-like optimizations (say strcpy (x, "abcd"); strcat (x, p); > or

[PATCH] tree-ssa-strlen: Fix up handling of conditionally zero memcpy [PR110914]

Hi! The following testcase is miscompiled since r279392 aka r10-5451-gef29b12cfbb4979 The strlen pass has adjust_last_stmt function, which performs mainly strcat or strcat-like optimizations (say strcpy (x, "abcd"); strcat (x, p); or equivalent memcpy (x, "abcd", strlen ("abcd") + 1); char *q =

Re: [PATCH] test: Add xfail for riscv_vector

On Wed, 30 Aug 2023, Juzhe-Zhong wrote: > Like ARM SVE, when we enable scalable vectorization for RVV, > we can't do constant fold for these yet for both ARM SVE and RVV. > > > Ok for trunk ? OK. > gcc/testsuite/ChangeLog: > > * gcc.dg/vect/pr88598-1.c: Add riscv_vector. > *

[PATCH] test: Add xfail for riscv_vector

Like ARM SVE, when we enable scalable vectorization for RVV, we can't do constant fold for these yet for both ARM SVE and RVV. Ok for trunk ? gcc/testsuite/ChangeLog: * gcc.dg/vect/pr88598-1.c: Add riscv_vector. * gcc.dg/vect/pr88598-2.c: Ditto. *

Re: [PATCH] fortran: Restore interface to its previous state on error [PR48776]

Le 28/08/2023 à 21:17, Harald Anlauf via Fortran a écrit : Hi Mikael, On 8/27/23 21:22, Mikael Morin via Gcc-patches wrote: Hello, this fixes an old error-recovery bug. Tested on x86_64-pc-linux-gnu. OK for master? I have only a minor comment: +/* Free the leading members of the

Re: [PATCH v2 3/4] LoongArch: add new configure option --with-strict-align-lib

On Wed, 2023-08-30 at 14:51 +0800, Yujie Yang wrote: > > > LoongArch processors may not support memory accesses without natural > > > alignments.  Building libraries with -mstrict-align may help with > > > toolchain binary compatiblity and performance on these implementations > > > (e.g. Loongson

Re: [PATCH V2] Emit funcall external declarations only if actually used.

ping > [Differences from V1: > - Prototype for call_from_call_insn moved before comment block. > - Reuse the `call' flag for SYMBOL_REF_LIBCALL. > - Fallback to check REG_CALL_DECL in non-direct calls. > - New test to check correct behavior for non-direct calls.] > > There are many places in

Re: [PATCH] store-merging: Fix up >= 64 bit insertion [PR111015]

On Wed, 30 Aug 2023, Jakub Jelinek wrote: > Hi! > > The following testcase shows that we mishandle bit insertion for > info->bitsize >= 64. The problem is in using unsigned HOST_WIDE_INT > shift + subtraction + build_int_cst to compute mask, the shift invokes > UB at compile time for

[PATCH V5] RISC-V: Enable vec_int testsuite for RVV VLA vectorization

Add vect_strided and vect_widen so that we will remove these following failures: FAIL: gcc.dg/vect/vect-reduc-pattern-1c-big-array.c -flto -ffat-lto-objects scan-tree-dump-times vect "vectorized 1 loops" 0 FAIL: gcc.dg/vect/vect-reduc-pattern-1c-big-array.c scan-tree-dump-times vect "vectorized

[PATCH] store-merging: Fix up >= 64 bit insertion [PR111015]

Hi! The following testcase shows that we mishandle bit insertion for info->bitsize >= 64. The problem is in using unsigned HOST_WIDE_INT shift + subtraction + build_int_cst to compute mask, the shift invokes UB at compile time for info->bitsize 64 and larger and e.g. on the testcase with

[PATCH V4 2/2] rs6000: use mtvsrws to move sf from si p9

Hi, As mentioned in PR108338, on p9, we could use mtvsrws to implement the bitcast from SI to SF (or lowpart DI to SF). For code: *(long long*)buff = di; float f = *(float*)(buff); "sldi 9,3,32 ; mtvsrd 1,9 ; xscvspdpn 1,1" is generated. A better one would be "mtvsrws 1,3 ; xscvspdpn 1,1".

[PATCH V4 1/2] rs6000: optimize moving to sf from highpart di

Hi, Currently, we have the pattern "movsf_from_si2" which was trying to support moving high part DI to SF. The pattern looks like: XX:SF=bitcast:SF(subreg(YY:DI>>32),0) It only accepts the "ashiftrt" for ">>", but "lshiftrt" is also ok. And the offset of "subreg" is hard code 0, which only works

Re: [PATCH] middle-end: Apply MASK_LEN_LOAD_LANES/MASK_LEN_STORE_LANES to ivopts/alias

Committed, thanks Richard. On 2023/8/30 15:25, Richard Biener via Gcc-patches wrote: On Wed, 30 Aug 2023, Juzhe-Zhong wrote: Like MASK_LOAD_LANES/MASK_STORE_LANES, add MASK_LEN_ variant. Bootstrap and Regression on X86 passed. Ok for trunk? OK. gcc/ChangeLog: *

Re: [PATCH] middle-end: Apply MASK_LEN_LOAD_LANES/MASK_LEN_STORE_LANES to ivopts/alias

On Wed, 30 Aug 2023, Juzhe-Zhong wrote: > Like MASK_LOAD_LANES/MASK_STORE_LANES, add MASK_LEN_ variant. > > Bootstrap and Regression on X86 passed. > > Ok for trunk? OK. > gcc/ChangeLog: > > * tree-ssa-alias.cc (ref_maybe_used_by_call_p_1): Add MASK_LEN_ variant. >

Re: [PATCH v2 3/4] LoongArch: add new configure option --with-strict-align-lib

> > LoongArch processors may not support memory accesses without natural > > alignments.  Building libraries with -mstrict-align may help with > > toolchain binary compatiblity and performance on these implementations > > (e.g. Loongson 2K1000LA). > > > > No significant performance degredation is

  1   2   >