[PATCH] testsuite: Avoid uninit var in pr60510.f [PR111427]

Hi, The uninitialized variable a in pr60510.f can cause some random failures as exposed in PR111427, see the details there. This patch is to make it initialized accordingly. As verified, it can fix the reported -m32 failures on P7 and P8 BE. It's also tested well on powerpc64-linux-gnu P9 and

[PATCH] rs6000: Make 32 bit stack_protect support prefixed insn [PR111367]

Hi, As PR111367 shows, with prefixed insn supported, some of checkings consider it's able to leverage prefixed insn for stack protect related load/store, but since we don't actually change the emitted assembly for 32 bit, it can cause the assembler error as exposed. Mike's commit

Re: [PATCH] remove workaround for GCC 4.1-4.3

> Am 27.09.2023 um 06:43 schrieb Jakub Jelinek : > > Hi! > > While looking into vec.h, I've noticed we still have a workaround for > GCC 4.1-4.3 bugs. > As we now use C++11 and thus need to be built by GCC 4.8 or later, > I think this is now never used. > > Bootstrapped/regtested on

Re: [PATCH-2v3, rs6000] Implement 32bit inline lrint [PR88558]

Hi, on 2023/9/25 10:05, HAO CHEN GUI wrote: > Hi, > This patch implements 32bit inline lrint by "fctiw". It depends on > the patch1 to do SImode move from FP registers on P7. > > Compared to last version, the main change is to add some test cases. >

Re: [PATCH-1v2, rs6000] Enable SImode in FP registers on P7 [PR88558]

Hi, on 2023/9/25 09:57, HAO CHEN GUI wrote: > Hi Kewen, > > 在 2023/9/18 15:34, Kewen.Lin 写道: >> hanks for checking! So for P7, this patch looks neutral, but for P8 and >> later, it may cause some few differences in code gen. I'm curious that how >> many total object files and different object

[PATCH] vec.h: Make some ops work with non-trivially copy constructible and/or destructible types

Hi! We have some very limited support for non-POD types in vec.h (in particular grow_cleared will invoke default ctors on the cleared elements and vector copying invokes copy ctors. My pending work on wide_int/widest_int which makes those two non-trivially default/copy constructible, assignable

Re: [PATCH] remove workaround for GCC 4.1-4.3

On 27 September 2023 06:43:24 CEST, Jakub Jelinek wrote: >Hi! > >While looking into vec.h, I've noticed we still have a workaround for >GCC 4.1-4.3 bugs. This is https://gcc.gnu.org/PR105656 thanks, >As we now use C++11 and thus need to be built by GCC 4.8 or later, >I think this is now never

Re: [PATCH] [11/12/13/14 Regression] ABI break in _Hash_node_value_base since GCC 11 [PR 111050]

Still no chance to get feedback from TC ? Maybe I can commit the below then ? AFAICS on gcc mailing list several gcc releases were done recently, too late. On 14/09/2023 06:46, François Dumont wrote: Author: TC Date:   Wed Sep 6 19:31:55 2023 +0200     libstdc++: Force

[PATCH] remove workaround for GCC 4.1-4.3

Hi! While looking into vec.h, I've noticed we still have a workaround for GCC 4.1-4.3 bugs. As we now use C++11 and thus need to be built by GCC 4.8 or later, I think this is now never used. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2023-09-27 Jakub Jelinek

[PATCH, obvious] OpenMP: GIMPLE_OMP_STRUCTURED_BLOCK bug fix

I'm planning to push the attached 1-liner bug fix to mainline tomorrow, when testing has completed. I think this qualifies as "obvious". There's no test case because I discovered it while testing the updated loop transformation patches, which are still a work in progress; it fixed an ICE in

Re: [PATCH v1] RISC-V: Support FP trunc auto-vectorization

LGTM. juzhe.zh...@rivai.ai From: pan2.li Date: 2023-09-27 11:28 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Support FP trunc auto-vectorization From: Pan Li This patch would like to support auto-vectorization for the trunc API in math.h.

[PATCH v1] RISC-V: Support FP trunc auto-vectorization

From: Pan Li This patch would like to support auto-vectorization for the trunc API in math.h. It depends on the -ffast-math option. When we would like to call trunc/truncf like v2 = trunc (v1), we will convert it into below insns (reference the implementation of llvm). * vfcvt.rtz.x.f v3, v1 *

Re: [PATCH] RISC-V: Bugfix for RTL check[PR111533]

+ vid sequence. The elt (i) can be either const_int or + const_poly_int. */ + HOST_WIDE_INT diff = rtx_to_poly_int64 (builder.elt (i)).to_constant () - i; How about: poly_int64 diff = rtx_to_poly_int64 (builder.elt (i)) - i; rtx avl - = has_vl_op (insn->rtl ()) ? get_vl

[PATCH] RISC-V: Bugfix for RTL check[PR111533]

From: xuli Consider the flowing situation: BB5: local_dem(RVV Insn 1, AVL(reg zero)) RVV Insn 1: vmv.s.x, AVL (const_int 1) RVV Insn 2: vredsum.vs, AVL(reg zero) vmv.s.x has vl operand, the following code will get avl (cosnt_int) from RVV Insn 1. rtx avl = has_vl_op (insn->rtl ()) ? get_vl

RE: [PATCH]AArch64 Rewrite simd move immediate patterns to new syntax

> -Original Message- > From: Ramana Radhakrishnan > Sent: Wednesday, September 27, 2023 2:28 AM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw > ; Marcus Shawcroft > ; Kyrylo Tkachov ; > Richard Sandiford > Subject: Re: [PATCH]AArch64 Rewrite simd move

RE: [PATCH]middle-end match.pd: optimize fneg (fabs (x)) to x | (1 << signbit(x)) [PR109154]

> -Original Message- > From: Andrew Pinski > Sent: Wednesday, September 27, 2023 2:17 AM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd ; rguent...@suse.de; > j...@ventanamicro.com > Subject: Re: [PATCH]middle-end match.pd: optimize fneg (fabs (x)) to x | (1 << > signbit(x))

Re: [PATCH]AArch64 Add movi for 0 moves for scalar types [PR109154]

On Wed, Sep 27, 2023 at 1:51 AM Tamar Christina wrote: > > Hi All, > > Following the Neoverse N/V and Cortex-A optimization guides SIMD 0 immediates > should be created with a movi of 0. > > At the moment we generate an `fmov .., xzr` which is slower and requires a > GP -> FP transfer. > >

Re: [PATCH]AArch64 Rewrite simd move immediate patterns to new syntax

On Wed, Sep 27, 2023 at 1:53 AM Tamar Christina wrote: > > Hi All, > > This rewrites the simd MOV patterns to use the new compact syntax. > No change in semantics is expected. This will be needed in follow on patches. > > This also merges the splits into the define_insn which will also be needed

Re: [PATCH]middle-end match.pd: optimize fneg (fabs (x)) to x | (1 << signbit(x)) [PR109154]

On Tue, Sep 26, 2023 at 5:51 PM Tamar Christina wrote: > > Hi All, > > For targets that allow conversion between int and float modes this adds a new > optimization transforming fneg (fabs (x)) into x | (1 << signbit(x)). Such > sequences are common in scientific code working with gradients. > >

[PATCH]AArch64 Rewrite simd move immediate patterns to new syntax

Hi All, This rewrites the simd MOV patterns to use the new compact syntax. No change in semantics is expected. This will be needed in follow on patches. This also merges the splits into the define_insn which will also be needed soon. Bootstrapped Regtested on aarch64-none-linux-gnu and no

[PATCH]AArch64 Add special patterns for creating DI scalar and vector constant 1 << 63 [PR109154]

Hi All, This adds a way to generate special sequences for creation of constants for which we don't have single instructions sequences which would have normally lead to a GP -> FP transfer or a literal load. The patch starts out by adding support for creating 1 << 63 using fneg (mov 0).

[PATCH]AArch64: Use SVE unpredicated LOGICAL expressions when Advanced SIMD inefficient [PR109154]

Hi All, SVE has much bigger immediate encoding range for bitmasks than Advanced SIMD has and so on a system that is SVE capable if we need an Advanced SIMD Inclusive-OR by immediate and would require a reload then an unpredicated SVE ORR instead. This has both speed and size improvements.

[PATCH]AArch64 Add movi for 0 moves for scalar types [PR109154]

Hi All, Following the Neoverse N/V and Cortex-A optimization guides SIMD 0 immediates should be created with a movi of 0. At the moment we generate an `fmov .., xzr` which is slower and requires a GP -> FP transfer. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master?

[PATCH]middle-end match.pd: optimize fneg (fabs (x)) to x | (1 << signbit(x)) [PR109154]

Hi All, For targets that allow conversion between int and float modes this adds a new optimization transforming fneg (fabs (x)) into x | (1 << signbit(x)). Such sequences are common in scientific code working with gradients. The transformed instruction if the target has an inclusive-OR that

[PATCH]middle-end Fold vec_cond into conditional ternary or binary operation when sharing operand [PR109154]

Hi All, When we have a vector conditional on a masked target which is doing a selection on the result of a conditional operation where one of the operands of the conditional operation is the other operand of the select, then we can fold the vector conditional into the operation. Concretely this

RE: [PATCH] ifcvt/vect: Emit COND_ADD for conditional scalar reduction.

Hi, I can't approve but hope you don't mind the review, > +/* Return true if this CODE describes a conditional (masked) > +internal_fn. */ > + > +bool > +cond_fn_p (code_helper code) > +{ > + if (!code.is_fn_code ()) > +return false; > + > + if (!internal_fn_p ((combined_fn) code)) > +

Re: [PATCH 1/2] c++: remove NON_DEPENDENT_EXPR, part 1

On 9/25/23 16:43, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- This tree code dates all the way back to r69130[1] which implemented typing of non-dependent expressions. Its motivation was never clear (to me at least) since the

Re: Re: [Committed] RISC-V: Fix mem-to-mem VLS move pattern[PR111566]

Hi, Jeff. I removed mem-to-mem patterns as you suggested that means we don't have scalar move optimization for small size vector modes. Is it ok for trunk? Since it is a bug fix patch, I hope we can land it soon. We may will find another way to optimize small size vector mode mem-to-mem.

Re: [PATCH 1/5] OpenMP, NVPTX: memcpy[23]D bias correction

Hi Julian! On 2023-09-06T02:34:30-0700, Julian Brown wrote: > This patch works around behaviour of the 2D and 3D memcpy operations in > the CUDA driver runtime. Particularly in Fortran, the "base pointer" > of an array (used for either source or destination of a host/device copy) > may lie

Re: [PATCH] ARM: Block predication on atomics [PR111235]

Reviewed-by: Ramana Radhakrishnan A very initial review here . I think it largely looks ok based on the description but I've spotted a few obvious nits and things that come to mind on reviewing this. I've not done a very deep review but hope it helps you move forward. I'm happy to work with you

[PATCH] DSE: Fix ICE when the mode with access_size don't exist on the target[PR111590]

hen doing fortran test with 'V' extension enabled on RISC-V port. I saw multiple ICE: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111590 The root cause is on DSE: internal compiler error: in smallest_mode_for_size, at stor-layout.cc:356 0x1918f70 smallest_mode_for_size(poly_int<2u, unsigned

Re: [PATCH 1/3] librust: Add libproc_macro and build system

Hi! On 2023-09-26T13:40:40+0200, Richard Biener wrote: > On Wed, Sep 20, 2023 at 2:04 PM Arthur Cohen > wrote: >> >> From: Pierre-Emmanuel Patry >> >> This patch series adds the build system changes to allow the Rust >> frontend to develop and distribute its own libraries. The first library

Re: [PATCH 2/3] build: Add libgrust as compilation modules

Hi! On 2023-09-20T13:59:53+0200, Arthur Cohen wrote: > From: Pierre-Emmanuel Patry > > Define the libgrust directory as a host compilation module as well as > for targets. > --- a/Makefile.def > +++ b/Makefile.def > @@ -149,6 +149,7 @@ host_modules= { module= libcc1; >

Re: [PATCH] AArch64: Fix __sync_val_compare_and_swap [PR111404]

Hi Wilco, Thanks for your email. On Tue, Sep 26, 2023 at 12:07 AM Wilco Dijkstra wrote: > > Hi Ramana, > > >> __sync_val_compare_and_swap may be used on 128-bit types and either calls > >> the > >> outline atomic code or uses an inline loop. On AArch64 LDXP is only > >> atomic if > >> the

[COMMITTED] Fix pr111456-1.c for targets that use unsigned char by default

This fixes the testcase to use an explicit `signed char` instead of plain `char`. Committed as obvious after a test with a cross to powerpc64-linux-gnu and x86_64-linux-gnu. gcc/testsuite/ChangeLog: PR testsuite/111603 * gcc.dg/tree-ssa/pr111456-1.c: Use `signed char` instead

Re: [PATCH] vect, omp: inbranch simdclone dropping const

On 26 September 2023 23:02:10 CEST, "Andre Vieira (lists)" wrote: > > >On 26/09/2023 21:26, Bernhard Reutner-Fischer wrote: >> On 26 September 2023 18:46:11 CEST, Tobias Burnus >> wrote: >>> On 26.09.23 18:37, Andrew Stubbs wrote: If the fall-through is deliberate please add a /*

Re: [PATCH 0/2] RISC-V: Define not broken prefetch builtins

On 9/22/23 01:11, Tsukasa OI wrote: Hello, As I explained earlier: , the builtin function for RISC-V "__builtin_riscv_zicbop_cbo_prefetchi" is completely broken. Instead, this patch set (in PATCH 1/2) creates three new,

Re: [PATCH] vect, omp: inbranch simdclone dropping const

On 26/09/2023 21:26, Bernhard Reutner-Fischer wrote: On 26 September 2023 18:46:11 CEST, Tobias Burnus wrote: On 26.09.23 18:37, Andrew Stubbs wrote: If the fall-through is deliberate please add a /* FALLTHROUGH */ comment (or whatever spelling disables the warning). It's:

Re: [PATCH] vect, omp: inbranch simdclone dropping const

On 26/09/2023 17:48, Jakub Jelinek wrote: On Tue, Sep 26, 2023 at 05:24:26PM +0100, Andre Vieira (lists) wrote: @@ -5816,6 +5817,18 @@ get_references_in_stmt (gimple *stmt, vec *references) } case IFN_MASK_LOAD: case IFN_MASK_STORE: + case

Re: [PATCH] vect, omp: inbranch simdclone dropping const

On 26 September 2023 18:46:11 CEST, Tobias Burnus wrote: >On 26.09.23 18:37, Andrew Stubbs wrote: >> If the fall-through is deliberate please add a /* FALLTHROUGH */ >> comment (or whatever spelling disables the warning). > >It's: gcc_fallthrough (); > >Which gets converted to

Re: [PATCH] RISC-V: Add opaque integer modes to fix ICE on DSE[PR111590]

钟居哲 writes: > Thanks Richard. > > Is it correct as follows ? > > diff --git a/gcc/dse.cc b/gcc/dse.cc > index 8b07be17674..c58d3bf4e1b 100644 > --- a/gcc/dse.cc > +++ b/gcc/dse.cc > @@ -1733,7 +1733,7 @@ find_shift_sequence (poly_int64 access_size, >/* If a constant was stored into memory,

Re: RISC-V: Added support for CRC.

On Tue, 26 Sept 2023 at 14:18, Jeff Law wrote: > But the Coremark code is what it is. This isn't a whole lot > different than the work in the 90s which rewrote loops and compromised > some of the spec benchmarks, or the eqntott hack to simplify that one > key loop in eqntott. I think the

Re: [PATCH v3] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

On 8/1/23 19:38, Xiao Zeng wrote: This patch recognizes Zicond patterns when the select pattern with condition eq or neq to 0 (using eq as an example), namely: 1 rd = (rs2 == 0) ? non-imm : 0 2 rd = (rs2 == 0) ? non-imm : non-imm 3 rd = (rs2 == 0) ? reg : non-imm 4 rd = (rs2 == 0) ? reg :

Re: [PATCH] RISC-V: Use stdint-gcc.h in rvv testsuite

On 9/26/23 11:13, Andrew Pinski wrote: On Tue, Sep 26, 2023 at 10:59 AM Patrick O'Neill wrote: stdint.h can be replaced with stdint-gcc.h to resolve some missing system headers in non-multilib installations. Tested using glibc rv32gcv and rv64gcv on r14-4258-gc9837443075. gcc/ChangeLog:

[COMMITTED] PR tree-optimization/111599 - Ensure ssa_name is still valid.

When processing an equivalence list, I neglected to make sure the ssa-name is still valid.  This patch simply checks to make sure it non-null and not in the free-list. Bootstraps on x86_64-pc-linux-gnu with no regressions.   Pushed. Andrew From 9df0f6bd582ceee53bfed8769cf156329ae33bd0 Mon Sep

Re: [PATCH] RISC-V: Use stdint-gcc.h in rvv testsuite

On Tue, Sep 26, 2023 at 10:59 AM Patrick O'Neill wrote: > > stdint.h can be replaced with stdint-gcc.h to resolve some missing > system headers in non-multilib installations. > > Tested using glibc rv32gcv and rv64gcv on r14-4258-gc9837443075. > > gcc/ChangeLog: > > *

[COMMITTED][GCC13] PR tree-optimization/110315 - Reduce the initial size of int_range_max.

This patch adds the ability to resize ranges as needed, defaulting to no resizing.  int_range_max now defaults to 3 sub-ranges (instead of 255) and grows to 255 when the range being calculated does not fit. Bootstraps on x86_64-pc-linux-gnu with no regressions.   Pushed. Andrew From

[PATCH] RISC-V: Use stdint-gcc.h in rvv testsuite

stdint.h can be replaced with stdint-gcc.h to resolve some missing system headers in non-multilib installations. Tested using glibc rv32gcv and rv64gcv on r14-4258-gc9837443075. gcc/ChangeLog: * config/riscv/riscv_vector.h (__RISCV_VECTOR_H): Replace stdint.h with stdint-gcc.h

Re: [PATCH] vect, omp: inbranch simdclone dropping const

On Tue, Sep 26, 2023 at 05:24:26PM +0100, Andre Vieira (lists) wrote: > @@ -5816,6 +5817,18 @@ get_references_in_stmt (gimple *stmt, > vec *references) > } > case IFN_MASK_LOAD: > case IFN_MASK_STORE: > + case IFN_MASK_CALL: > + { > + tree

Re: [PATCH] vect, omp: inbranch simdclone dropping const

On 26.09.23 18:37, Andrew Stubbs wrote: If the fall-through is deliberate please add a /* FALLTHROUGH */ comment (or whatever spelling disables the warning). It's: gcc_fallthrough (); Which gets converted to "__attribute__((fallthrough))"; it could also expand to "[[fallthrough]]" but that's

Re: [PATCH] vect, omp: inbranch simdclone dropping const

I don't have authority to approve anything, but here's a review anyway. Thanks for working on this. On 26/09/2023 17:24, Andre Vieira (lists) wrote: The const attribute is ignored when simdclone's are used inbranch. This is due to the fact that when analyzing a MASK_CALL we were not looking

Re: [PATCH] fwprop: Allow UNARY_P and check register pressure.

Robin Dapp via Gcc-patches writes: > Thanks for looking at it in detail. > >> Yeah, I think this is potentially a blocker for propagating A into B >> when A is used elsewhere. Combine is able to combine A and B while >> keeping A in parallel with the result. I think either fwprop would >> need

[PATCH] vect, omp: inbranch simdclone dropping const

The const attribute is ignored when simdclone's are used inbranch. This is due to the fact that when analyzing a MASK_CALL we were not looking at the targeted function for flags, but instead only at the internal function call itself. This patch adds code to make sure we look at the target

Re: RISC-V: Added support for CRC.

On Tue, 26 Sep 2023, Jeff Law wrote: > What ultimately pushed us to keep moving forward on this effort was > discovering numerous CRC loop implementations out in the wild, including 4 > implementations (IIRC) in the kernel itself. The kernel employs bitwise CRC only in look-up table

[PATCH] RFC: Add late-combine pass [PR106594]

This patch adds a combine pass that runs late in the pipeline. There are two instances: one between combine and split1, and one after postreload. The pass currently has a single objective: remove definitions by substituting into all uses. The pre-RA version tries to restrict itself to cases that

Re: [PATCH 01/12] [contrib] validate_failures.py: Avoid testsuite aliasing

Hi Maxim! On Mon, 5 Jun 2023 18:06:25 +0400 Maxim Kuvyrkov via Gcc-patches wrote: > > On Jun 3, 2023, at 19:17, Jeff Law wrote: > > > > On 6/2/23 09:20, Maxim Kuvyrkov via Gcc-patches wrote: > >> This patch adds tracking of current testsuite "tool" and "exp" > >> to the processing of .sum

[PATCH 2/1] c++: more non-static memfn call dependence cleanup [PR106086]

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- This follow-up patch removes some more repetition of the type-dependent case of finish_call_expr, this time in of tsubst_copy_and_build. This allows us to easily fix PR106086 -- which is about us failing to

Re: Re: [Committed] RISC-V: Fix mem-to-mem VLS move pattern[PR111566]

OK。 Remove mem-to-mem pattern: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566] (gnu.org) juzhe.zh...@rivai.ai From: Jeff Law Date: 2023-09-26 23:15 To: 钟居哲; gcc-patches CC: kito.cheng; kito.cheng; rdapp.gcc Subject: Re: [Committed] RISC-V: Fix mem-to-mem VLS move

[PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]

PR target/111566 gcc/ChangeLog: * config/riscv/vector.md (*mov_mem_to_mem): Remove. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/mov-1.c: Adapt test. * gcc.target/riscv/rvv/autovec/vls/mov-10.c: Ditto. *

Re: [PATCH] __atomic_test_and_set: Fall back to library, not non-atomic code

On 9/26/23 08:34, Hans-Peter Nilsson wrote: Tested cris-elf, native x86_64-pc-linux-gnu and arm-eabi. For arm-eabi, notably lacking any atomic support for the default multilib, with --target_board=arm-sim it regressed 29_atomics/atomic_flag/cons/value_init.cc with the expected linker failure

Re: [PATCH] testsuite: Require thread-fence for 29_atomics/atomic_flag/cons/value_init.cc

On 9/26/23 08:40, Hans-Peter Nilsson wrote: Ok to commit? -- >8 -- A recent patch made __atomic_test_and_set no longer fall back to emitting non-atomic code, but instead will then emit a call to __atomic_test_and_set, thereby exposing the need to gate also this test on support for atomics,

Re: [Committed] RISC-V: Fix mem-to-mem VLS move pattern[PR111566]

On 9/26/23 08:51, 钟居哲 wrote: Thanks Jeff. Address comments: [PATCH V2] RISC-V: Fix mem-to-mem VLS move pattern[PR111566] (gnu.org) Actually, we only allow mem-to-mem move for VLS modes size <= MAX_BITS_PER_WORD.

Re: [PATCH] c++: non-static memfn call dependence cleanup

On Tue, Sep 26, 2023, 19:52 Patrick Palka wrote: > Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for > trunk? > > -- >8 -- > > In cp_parser_postfix_expression, we essentially repeat the > type-dependent and COMPONENT_REF callee cases of finish_call_expr. > This patch

Re: Re: [PATCH] RISC-V: Add opaque integer modes to fix ICE on DSE[PR111590]

Thanks Richard. Is it correct as follows ? diff --git a/gcc/dse.cc b/gcc/dse.cc index 8b07be17674..c58d3bf4e1b 100644 --- a/gcc/dse.cc +++ b/gcc/dse.cc @@ -1733,7 +1733,7 @@ find_shift_sequence (poly_int64 access_size, /* If a constant was stored into memory, try to simplify it here,

Re: Re: [Committed] RISC-V: Fix mem-to-mem VLS move pattern[PR111566]

Thanks Jeff. Address comments: [PATCH V2] RISC-V: Fix mem-to-mem VLS move pattern[PR111566] (gnu.org) Actually, we only allow mem-to-mem move for VLS modes size <= MAX_BITS_PER_WORD. Since we want to optimize this case: - typedef int8_t v2qi __attribute__ ((vector_size (2))); -

[PATCH V2] RISC-V: Fix mem-to-mem VLS move pattern[PR111566]

The mem-to-mem insn pattern is splitted from reg-to-mem/mem-to-reg/reg-to-reg causes ICE in RA since RA prefer they stay together. Now, we split mem-to-mem as a pure pre-RA split pattern and only allow define_insn match mem-to-mem VLS move in pre-RA stage (Forbid mem-to-mem move after RA).

[PATCH] testsuite: Require thread-fence for 29_atomics/atomic_flag/cons/value_init.cc

Ok to commit? -- >8 -- A recent patch made __atomic_test_and_set no longer fall back to emitting non-atomic code, but instead will then emit a call to __atomic_test_and_set, thereby exposing the need to gate also this test on support for atomics, similar to r14-3980-g62b29347c38394. libstdc++-v3:

[PATCH] __atomic_test_and_set: Fall back to library, not non-atomic code

Tested cris-elf, native x86_64-pc-linux-gnu and arm-eabi. For arm-eabi, notably lacking any atomic support for the default multilib, with --target_board=arm-sim it regressed 29_atomics/atomic_flag/cons/value_init.cc with the expected linker failure due to lack of __atomic_test_and_set - which is

Re: [PING] [PATCH] Harmonize headers between both dg-extract-results scripts

On 9/25/23 03:55, Paul Iannetta wrote: On Mon, Sep 18, 2023 at 08:39:34AM +0200, Paul Iannetta wrote: On Thu, Sep 14, 2023 at 04:24:33PM +0200, Paul Iannetta wrote: Hi, This is a small patch so that both dg-extract-results.py and dg-extract-results.sh share the same header. In particular,

[PATCH] c++: non-static memfn call dependence cleanup

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- In cp_parser_postfix_expression, we essentially repeat the type-dependent and COMPONENT_REF callee cases of finish_call_expr. This patch deduplicates this logic. gcc/cp/ChangeLog: * parser.cc

Re: [PATCH] AArch64: Remove BTI from outline atomics

On 26/09/2023 14:46, Wilco Dijkstra wrote: > > The outline atomic functions have hidden visibility and can only be called > directly.  Therefore we can remove the BTI at function entry.  This improves > security by reducing the number of indirect entry points in a binary. > The BTI markings on

[PATCH v4] aarch64: Fine-grained policies to control ldp-stp formation.

This patch implements the following TODO in gcc/config/aarch64/aarch64.cc to provide the requested behaviour for handling ldp and stp: /* Allow the tuning structure to disable LDP instruction formation from combining instructions (e.g., in peephole2). TODO: Implement fine-grained

Re: [PATCH] RISC-V: Add opaque integer modes to fix ICE on DSE[PR111590]

Juzhe-Zhong writes: > When doing fortran test with 'V' extension enabled on RISC-V port. > I saw multiple ICE: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111590 > > The root cause is on DSE: > > internal compiler error: in smallest_mode_for_size, at stor-layout.cc:356 > 0x1918f70

[PATCH] AArch64: Remove BTI from outline atomics

The outline atomic functions have hidden visibility and can only be called directly.  Therefore we can remove the BTI at function entry.  This improves security by reducing the number of indirect entry points in a binary. The BTI markings on the objects are still emitted. Passes regress, OK for

Re: [Committed] RISC-V: Fix mem-to-mem VLS move pattern[PR111566]

On 9/26/23 07:15, Juzhe-Zhong wrote: The mem-to-mem insn pattern is splitted from reg-to-mem/mem-to-reg/reg-to-reg causes ICE in RA since RA prefer they stay together. Now, we split mem-to-mem as a pure pre-RA split pattern and only allow define_insn match mem-to-mem VLS move in pre-RA stage

Re: RISC-V: Added support for CRC.

On 9/23/23 17:05, Joern Rennecke wrote: Mariam Harutyunyan: +++ b/gcc/ChangeLog @@ -1,3 +1,45 @@ +2023-08-03 Mariam Arutunian + It is common courtesy to include all authors in the list of authors for the ChangeLog; also, this may help people in the future understand the history of the

[Committed] RISC-V: Fix mem-to-mem VLS move pattern[PR111566]

The mem-to-mem insn pattern is splitted from reg-to-mem/mem-to-reg/reg-to-reg causes ICE in RA since RA prefer they stay together. Now, we split mem-to-mem as a pure pre-RA split pattern and only allow define_insn match mem-to-mem VLS move in pre-RA stage (Forbid mem-to-mem move after RA).

Re: RISC-V: Added support for CRC.

On Sun, 2023-09-24 at 00:05 +0100, Joern Rennecke wrote: > > Although maybe Oleg Endo's library, as mentioned in > https://gcc.gnu.org/pipermail/gcc-patches/2022-March/591748.html , > might be suitable? What is the license for that? > > I haven't published the library, but I think I could do

RE: [PATCH V3] MATCH: Optimize COND_ADD_LEN reduction pattern

Committed as passed x86 bootstrap and regression test, thanks Richard. Pan -Original Message- From: Richard Biener Sent: Tuesday, September 26, 2023 7:35 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; richard.sandif...@arm.com Subject: Re: [PATCH V3] MATCH: Optimize COND_ADD_LEN

RE: [PATCH V2] MATCH: Optimize COND_ADD_LEN reduction pattern

Committed as passed x86 bootstrap and regression test, thanks Richard. Pan -Original Message- From: Richard Biener Sent: Tuesday, September 26, 2023 7:35 PM To: Juzhe-Zhong Cc: gcc-patches@gcc.gnu.org; richard.sandif...@arm.com Subject: Re: [PATCH V2] MATCH: Optimize COND_ADD_LEN

Re: [PATCH v2 0/2] Update target-supports.exp for LoongArch SX/ASX.

Correction: vect.exp will be set to run when target is capable of running LASX instructions, otherwise it will be compiled only. On Tue, 2023-09-26 at 19:56 +0800, Chenghui Pan wrote: > This is an update of: > https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630953.html > > This version

[PATCH v2 0/2] Update target-supports.exp for LoongArch SX/ASX.

This is an update of: https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630953.html This version of patch set contains code that enable vect.exp for LoongArch target when target environment is capable of running LASX instructions. After some attemptions, we still need

[PATCH v2 2/2] Add LoongArch in check_effective_target_vect_int_mod according to ISA capabilities.

gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add LoongArch in check_effective_target_vect_int_mod according to ISA capabilities. --- gcc/testsuite/lib/target-supports.exp | 18 ++ 1 file changed, 18 insertions(+) diff --git

[PATCH v2 1/2] Enable vect.exp for LoongArch.

gcc/testsuite/ChangeLog: * lib/target-supports.exp: Enable vect.exp for LoongArch. --- gcc/testsuite/lib/target-supports.exp | 31 +++ 1 file changed, 31 insertions(+) diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp

Re: [PATCH] MATCH: Simplify `(A ==/!= B) &/| (((cast)A) CMP C)`

On Thu, Sep 21, 2023 at 4:43 AM Andrew Pinski wrote: > > This patch adds support to the pattern for `(A == B) &/| (A CMP C)` > where the second A could be casted to a different type. > Some were handled correctly if using seperate `if` statements > but not if combined with BIT_AND/BIT_IOR. > In

[COMMITTED] ada: Fix unnesting generated loops with nested finalization procedure

The compiler can generate loops for creating array aggregates, for example used during the initialization of variable. If the component type of the array element requires finalization, the compiler also creates a block and a nested procedure that need to be correctly unnested if unnesting is

[COMMITTED] ada: Fix deferred constant wrongly rejected

From: Eric Botcazou This recent regression occurs when the nominal subtype of the constant is a discriminated record type with default discriminants. gcc/ada/ PR ada/110488 * sem_ch3.adb (Analyze_Object_Declaration): Do not build a default subtype for a deferred constant

[COMMITTED] ada: Crash processing the accessibility level of an actual parameter

From: Javier Miranda gcc/ada/ * exp_ch6.adb (Expand_Call_Helper): When computing the accessibility level of an actual parameter based on the expresssion of a constant declaration, add missing support for deferred constants Tested on x86_64-pc-linux-gnu,

[COMMITTED] ada: Update personality function for CHERI purecap

From: Daniel King This makes two changes to the GNAT personality function to reflect differences for pure capability CHERI/Morello. The first is to use __builtin_code_address_from_pointer to drop the LSB from Morello code pointers when searching through call-site tables (without this we would

[COMMITTED] ada: Fix missing call to Finalize_Protection for simple protected objects

From: Eric Botcazou There is a glitch in Exp_Ch7.Build_Finalizer causing the finalizer to do nothing for simple protected objects. The change also removes redundant calls to the Is_Simple_Protected_Type predicate and fixes a minor inconsistency between Requires_Cleanup_Actions and

[COMMITTED] ada: Add CHERI variant of System.Stream_Attributes

From: Daniel King Reading and writing System.Address to a stream on CHERI targets does not preserve the capability tag; it will always be invalid since a valid capability cannot be created out of thin air. Reading an Address from a stream would therefore never yield a capability that can be

[COMMITTED] ada: Fix missing finalization of extended return object on abnormal completion

From: Eric Botcazou This happens in the case of a nonlimited return type and is a fallout of the optimization recently implemented for them. gcc/ada/ * einfo.ads (Status_Flag_Or_Transient_Decl): Remove ??? comment. * exp_ch6.adb (Expand_N_Extended_Return_Statement): Extend the

[COMMITTED] ada: Dimensional analysis when used with elementary functions

From: Derek Schacht gcc/ada/ * doc/gnat_ugn/gnat_and_program_execution.rst: Add more details on using Generic Elementary Functions with dimensional analysis. * gnat_ugn.texi: Regenerate. Tested on x86_64-pc-linux-gnu, committed on master. ---

[COMMITTED] ada: Fix conversions between addresses and integers

From: Daniel King On CHERI targets the size of System.Address and Integer_Address (or similar) are not the same. The operations in System.Storage_Elements should be used to convert between integers and addresses. gcc/ada/ * libgnat/a-tags.adb (To_Tag): Use System.Storage_Elements for

[COMMITTED] ada: Define CHERI exception types

From: Daniel King These exception types map to the CHERI hardware exceptions that are triggered due to misuse of capabilities. gcc/ada/ * libgnat/i-cheri.ads (Capability_Bound_Error) (Capability_Permission_Error, Capability_Sealed_Error) (Capability_Tag_Error): New,

[COMMITTED] ada: Make minor corrections to CUDA-related comments

From: Ronan Desplanques gcc/ada/ * exp_prag.adb: Make minor corrections in comments. * rtsfind.ads: Remove unused element from RTU_Id definition. Tested on x86_64-pc-linux-gnu, committed on master. --- gcc/ada/exp_prag.adb | 8 gcc/ada/rtsfind.ads | 1 - 2 files

[COMMITTED] ada: Clarify RM references that justify a constraint check

From: Yannick Moy gcc/ada/ * exp_ch5.adb (Expand_N_Case_Statement): Reference both sections of the Ada RM that deal with case statements and case expressions to justify the insertion of a runtime check. Tested on x86_64-pc-linux-gnu, committed on master. ---

Re: [PATCH 2/3] build: Add libgrust as compilation modules

On Wed, Sep 20, 2023 at 2:04 PM Arthur Cohen wrote: > > From: Pierre-Emmanuel Patry > > Define the libgrust directory as a host compilation module as well as > for targets. OK if you tested this doesn't break build when rust is enabled on trunk (and doesn't build libgrust if not). Richard. >

Re: [PATCH 1/3] librust: Add libproc_macro and build system

On Wed, Sep 20, 2023 at 2:04 PM Arthur Cohen wrote: > > From: Pierre-Emmanuel Patry > > This patch series adds the build system changes to allow the Rust > frontend to develop and distribute its own libraries. The first library > we have been working on is the `proc_macro` library, comprised of

Re: [PATCH] PHIOPT: Fix minmax_replacement for three way

On Thu, Sep 21, 2023 at 10:10 AM Andrew Pinski wrote: > > So when diamond bb support was added to minmax_replacement in > r13-1950-g9bb19e143cfe, > the code was not expecting the alt_middle_bb not to exist if it was empty > (for threeway_p). > So when factor_out_conditional_conversion was used

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