On Thu, 5 Oct 2023, Jakub Jelinek wrote:
> Hi!
>
> The following patch removes ipa_bits struct pointer/vector from ipa
> jump functions and ipa cp transformations.
>
> The reason is because the struct uses widest_int to represent
> mask/value pair, which in the RFC patches to allow larger
Committed, thanks!
Patrick
On 10/5/23 17:51, Kito Cheng wrote:
LGTM
Patrick O'Neill 於 2023年10月6日 週五 07:46 寫道：
stdint.h can be replaced with stdint-gcc.h to resolve some missing
system headers in non-multilib installations.
Tested using glibc rv32gcv and rv64gcv on
Am Donnerstag, dem 05.10.2023 um 15:35 -0700 schrieb Kees Cook:
> On Thu, Oct 05, 2023 at 04:08:52PM -0400, Siddhesh Poyarekar wrote:
> > 2. How would you handle signedness of the size field? The size gets
> > converted to sizetype everywhere it is used and overflows/underflows may
> > produce
Committed, thanks Kito.
Pan
From: Kito Cheng
Sent: Friday, October 6, 2023 11:09 AM
To: Li, Pan2
Cc: GCC Patches ; 钟居哲 ; Wang,
Yanzhang
Subject: Re: [PATCH v1] RISC-V: Update comments for FP rounding related autovec
LGTM
mailto:pan2...@intel.com>> 於 2023年10月6日 週五 10:39 寫道：
From: Pan Li
LGTM
於 2023年10月6日 週五 10:39 寫道：
> From: Pan Li
>
> Some comment is out of date, this patch would like to fix it.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Update comments.
>
> Signed-off-by: Pan Li
> ---
> gcc/config/riscv/autovec.md | 6 +-
> 1 file changed, 5
From: Pan Li
Some comment is out of date, this patch would like to fix it.
gcc/ChangeLog:
* config/riscv/autovec.md: Update comments.
Signed-off-by: Pan Li
---
gcc/config/riscv/autovec.md | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git
>
> On Thu, Oct 05, 2023 at 02:01:40PM +, Tamar Christina wrote:
> > gcc/ChangeLog:
> >
> > * tree-if-conv.cc (INCLUDE_ALGORITHM): Remove.
> > (typedef struct ifcvt_arg_entry): New.
> > (cmp_arg_entry): New.
> > (gen_phi_arg_condition, gen_phi_nest_statement,
> >
LGTM
Patrick O'Neill 於 2023年10月6日 週五 07:46 寫道：
> stdint.h can be replaced with stdint-gcc.h to resolve some missing
> system headers in non-multilib installations.
>
> Tested using glibc rv32gcv and rv64gcv on r14-4381-g7eb5ce7f58e.
>
> gcc/testsuite/ChangeLog:
>
> *
stdint.h can be replaced with stdint-gcc.h to resolve some missing
system headers in non-multilib installations.
Tested using glibc rv32gcv and rv64gcv on r14-4381-g7eb5ce7f58e.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h:
Replace
On 05-Oct-2023 18:35, Kees Cook wrote:On Thu, Oct 05, 2023 at 04:08:52PM -0400, Siddhesh Poyarekar wrote:
> 2. How would you handle signedness of the size field? The size gets
> converted to sizetype everywhere it is used and overflows/underflows may
> produce interesting results. Do you
Match has a pattern which converts `vec_cond(vec_cond(a,b,0), c, d)`
into `vec_cond(a & b, c, d)` but since in this case a is a comparison
fold will change `a & b` back into `vec_cond(a,b,0)` which causes an
infinite loop.
The best way to fix this is to enable the patterns for
On 10/3/23 14:58, Patrick O'Neill wrote:
On 10/2/23 06:57, Kito Cheng wrote:
On Tue, Sep 26, 2023 at 10:59 AM Patrick O'Neill wrote:
stdint.h can be replaced with stdint-gcc.h to resolve some missing
system headers in non-multilib installations.
Tested using glibc rv32gcv and rv64gcv on
On 10/5/23 16:17, Richard Sandiford wrote:
"Jose E. Marchesi" writes:
ping
I don't know this code very well, and have AFAIR haven't worked
with an assembler that requires external declarations, but since
it's at a second ping :)
ping
[Differences from V1:
- Prototype for
On Thu, Oct 05, 2023 at 04:08:52PM -0400, Siddhesh Poyarekar wrote:
> 2. How would you handle signedness of the size field? The size gets
> converted to sizetype everywhere it is used and overflows/underflows may
> produce interesting results. Do you want to limit the types to unsigned or
> do
On 10/5/23 15:14, Jeff Law wrote:
On 10/4/23 16:55, Patrick O'Neill wrote:
Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to
perform a memcpy. We no longer expect memcpy for riscv_v targets.
gcc/testsuite/ChangeLog:
* gcc.dg/pr90263.c: Skip riscv_v targets.
*
"Jose E. Marchesi" writes:
> ping
I don't know this code very well, and have AFAIR haven't worked
with an assembler that requires external declarations, but since
it's at a second ping :)
>
>> ping
>>
>>> [Differences from V1:
>>> - Prototype for call_from_call_insn moved before comment block.
On 10/4/23 16:55, Patrick O'Neill wrote:
Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to
perform a memcpy. We no longer expect memcpy for riscv_v targets.
gcc/testsuite/ChangeLog:
* gcc.dg/pr90263.c: Skip riscv_v targets.
*
On Wednesday, 26 July 2023 06:33:41 MDT Richard Biener wrote:
> Btw, how the experimental SIMD C++ standard library handles
> these issue might be also interesting to research (author CCed)
I only skimmed over this thread now. FWIW, I would really like better
support for AVX-512 bitmasks for the
> -Original Message-
> From: Richard Sandiford
> Sent: Thursday, October 5, 2023 9:26 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw
> ; Marcus Shawcroft
> ; Kyrylo Tkachov
> Subject: Re: [PATCH]AArch64 Add SVE implementation for cond_copysign.
>
> Tamar
On Thu, Oct 5, 2023 at 12:48 PM Tamar Christina wrote:
>
> > -Original Message-
> > From: Richard Sandiford
> > Sent: Thursday, October 5, 2023 8:29 PM
> > To: Tamar Christina
> > Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw
> > ; Marcus Shawcroft
> > ; Kyrylo Tkachov
> >
Tamar Christina writes:
>> -Original Message-
>> From: Richard Sandiford
>> Sent: Thursday, October 5, 2023 8:29 PM
>> To: Tamar Christina
>> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw
>> ; Marcus Shawcroft
>> ; Kyrylo Tkachov
>> Subject: Re: [PATCH]AArch64 Add SVE
In spite of what the comment says, the MALLOC_ALIGNMENT in glibc
for 32-bit hppa-linux has always been 8, not 16. There is no
reason to increase it as the old linux threads implementation
has been removed. So, we can use default in pa.h.
Dave
---
Delete MALLOC_ABI_ALIGNMENT define from
On 2023-08-25 11:24, Qing Zhao wrote:
This is the 3rd version of the patch, per our discussion based on the
review comments for the 1st and 2nd version, the major changes in this
version are:
Hi Qing,
I hope the review was helpful. Overall, a couple of things to consider:
1. How would you
On 2023-08-25 11:24, Qing Zhao wrote:
Use the counted_by atribute info in builtin object size to compute the
subobject size for flexible array members.
gcc/ChangeLog:
PR C/108896
* tree-object-size.cc (addr_object_size): Use the counted_by
attribute info.
*
> -Original Message-
> From: Richard Sandiford
> Sent: Thursday, October 5, 2023 8:29 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw
> ; Marcus Shawcroft
> ; Kyrylo Tkachov
> Subject: Re: [PATCH]AArch64 Add SVE implementation for cond_copysign.
>
> Tamar
Tamar Christina writes:
> Hi,
>
>> The lowpart_subreg should simplify this back into CONST0_RTX (mode),
>> making it no different from:
>>
>> emti_move_insn (target, CONST0_RTX (mode));
>>
>> If the intention is to share zeros between modes (sounds good!), then I think
>> the subreg needs
On 2023-10-05 14:51, Siddhesh Poyarekar wrote:
On 2023-08-25 11:24, Qing Zhao wrote:
Provide a new counted_by attribute to flexible array member field.
The obligatory "I can't ack the patch but here's a review" disclaimer :)
'counted_by (COUNT)'
The 'counted_by' attribute may be
Tamar Christina writes:
> Hi All,
>
> This adds an implementation for masked copysign along with an optimized
> pattern for masked copysign (x, -1).
It feels like we're ending up with a lot of AArch64-specific code that
just hard-codes the observation that changing the sign is equivalent to
the following set of 3 patches provide the infrastructure for a fast vrp
pass.
The pass is currently not invoked anywhere, but I wanted to get the
infrastructure bits in place now... just in case we want to use it
somewhere.
It clearly bootstraps with no regressions since it isn't being
This patch adds a fast VRP pass. It is not invoked from anywhere, so
should cause no issues.
If you want to utilize it, simply add a new pass, ie:
--- a/gcc/passes.def
+++ b/gcc/passes.def
@@ -92,6 +92,7 @@ along with GCC; see the file COPYING3. If not see
NEXT_PASS (pass_phiprop);
This patch adds 2 routine that can be called to generate GORI information.
The primar API is:
bool gori_on_edge (class ssa_cache , edge e, range_query *query =
NULL, gimple_outgoing_range *ogr = NULL);
This will populate an ssa-cache R with any ranges that are generated by
edge E. It will
This patch adds a DOM based ranger that is intended to be used by a dom
walk pass and provides basic ranges.
It utilizes the new GORI edge API to find outgoing ranges on edges, and
combines these with any ranges calculated during the walk up to this
point. When a query is made for a range
On 2023-08-25 11:24, Qing Zhao wrote:
Provide a new counted_by attribute to flexible array member field.
The obligatory "I can't ack the patch but here's a review" disclaimer :)
'counted_by (COUNT)'
The 'counted_by' attribute may be attached to the flexible array
member of a
On Thu, Oct 5, 2023 at 11:22 AM Tamar Christina wrote:
>
> Hi All,
>
> copysign (x, -1) is effectively fneg (abs (x)) which on AArch64 can be
> most efficiently done by doing an OR of the signbit.
>
> The middle-end will optimize fneg (abs (x)) now to copysign as the
> canonical form and so this
Hi All,
This adds an implementation for masked copysign along with an optimized
pattern for masked copysign (x, -1).
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
PR tree-optimization/109154
*
Hi All,
This adds a masked variant of copysign. Nothing very exciting just the
general machinery to define and use a new masked IFN.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Note: This patch is part of a testseries and tests for it are added in the
AArch64 patch that
Hi All,
copysign (x, -1) is effectively fneg (abs (x)) which on AArch64 can be
most efficiently done by doing an OR of the signbit.
The middle-end will optimize fneg (abs (x)) now to copysign as the
canonical form and so this optimizes the expansion.
If the target has an inclusive-OR that takes
Hi All,
When ifcvt was initially added masking was not a thing and as such it was
rather conservative in what it supported.
For builtins it only allowed C99 builtin functions which it knew it can fold
away.
These days the vectorizer is able to deal with needing to mask IFNs itself.
Hi,
> The lowpart_subreg should simplify this back into CONST0_RTX (mode),
> making it no different from:
>
> emti_move_insn (target, CONST0_RTX (mode));
>
> If the intention is to share zeros between modes (sounds good!), then I think
> the subreg needs to be on the lhs instead.
>
> > +
> >>
> >> The WIP SME patches add a %Z modifier for 'z' register prefixes,
> >> similarly to b/h/s/d for scalar FP. With that I think the alternative can
> >> be:
> >>
> >> [w , 0 , ; * , sve ] \t%Z0., %Z0., #%2
> >>
> >> although it would be nice to keep the hex constant.
> >
> >
> I suppose the idea is that -abs(x) might be easier to optimize with other
> patterns (consider a - copysign(x,...), optimizing to a + abs(x)).
>
> For abs vs copysign it's a canonicalization, but (negate (abs @0)) is less
> canonical than copysign.
>
> > Should I try removing this?
>
> I'd
> > b17e1136600a 100644
> > --- a/gcc/match.pd
> > +++ b/gcc/match.pd
> > @@ -9476,3 +9476,57 @@ and,
> > }
> > (if (full_perm_p)
> > (vec_perm (op@3 @0 @1) @3 @2))
> > +
> > +/* Transform fneg (fabs (X)) -> X | 1 << signbit (X). */
> > +
> > +(simplify
> > + (negate (abs
I was checking one of those functions - and now ended up documenting
some of them. Still to be documented are omp_target_{is_accessible,memcpy*}.
I did run into some possibly questionable code for corner cases and have
filed https://gcc.gnu.org/PR111707 for those. The documentation matches
the
On Thu, 5 Oct 2023 at 18:04, François Dumont wrote:
>
> Here is a patch to fix following test case in gcc:
>
> gcc/testsuite/g++.dg/cpp23/ext-floating13.C
>
> libstdc++: [_GLIBCXX_INLINE_VERSION] Add missing float symbols
>
> libstdc++-v3/ChangeLog:
>
> *
Here is a patch to fix following test case in gcc:
gcc/testsuite/g++.dg/cpp23/ext-floating13.C
libstdc++: [_GLIBCXX_INLINE_VERSION] Add missing float symbols
libstdc++-v3/ChangeLog:
* config/abi/pre/gnu-versioned-namespace.ver: Add missing
symbols
for
On Thu, Oct 5, 2023 at 12:14 AM Jiufu Guo wrote:
> Hi,
>
> As mentioned in PR108338, on p9, we could use mtvsrws to implement
> the bitcast from SI to SF (or lowpart DI to SF).
>
> For example:
> *(long long*)buff = di;
> float f = *(float*)(buff);
>
> "sldi 9,3,32 ; mtvsrd 1,9 ; xscvspdpn
On Thu, Oct 5, 2023 at 12:50 AM Jiufu Guo wrote:
> Hi,
>
> Currently, we have the pattern "movsf_from_si2" which was trying
> to support moving high part DI to SF.
>
> But current pattern only accepts "ashiftrt":
> XX:SF=bitcast:SF(subreg(YY:DI>>32),0), but actually "lshiftrt" should
> also be
On 10/4/23 15:29, Jeff Law wrote:
On 10/4/23 16:21, Patrick O'Neill wrote:
On 10/4/23 15:14, Jeff Law wrote:
On 10/4/23 15:57, Patrick O'Neill wrote:
Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to
perform a memcpy. We no longer expect memcpy for riscv_v targets.
On 10/5/23 07:33, Robin Dapp wrote:
So I think Kenner's code is trying to prevent having a value in a
SUBREG that is inconsistent with the SUBREG_PROMOTED* flag bits. But
I think it's been unnecessary since Matz's rewrite in 2009.
I couldn't really tell what the rewrite does entirely so I
On 10/3/23 10:07, Surya Kumari Jangala wrote:
ira: Scale save/restore costs of callee save registers with block frequency
In assign_hard_reg(), when computing the costs of the hard registers, the
cost of saving/restoring a callee-save hard register in prolog/epilog is
taken into
On 28/09/2023 12:55, Siddhesh Poyarekar wrote:
> +Security features implemented in GCC
> +
> +
[...]
> +
> +Similarly, GCC may transform code in a way that the correctness of
> +the expressed algorithm is preserved, but supplementary properties
> +
Committed some trivial comma and indentation fixups that Jan shared with
me off-list.
Jan Engelhardt (2):
secpol: add grammatically missing commas / remove one excess instance
secpol: consistent indentation
SECURITY.txt | 48
1 file changed,
From: Jan Engelhardt
86% of the document have 4 spaces; adjust the remaining 14%.
Signed-off-by: Jan Engelhardt
ChangeLog:
* SECURITY.txt: Fix up indentation.
---
SECURITY.txt | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git
From: Jan Engelhardt
Signed-off-by: Jan Engelhardt
ChangeLog:
* SECURITY.txt: Fix up commas.
---
SECURITY.txt | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/SECURITY.txt b/SECURITY.txt
index b65f24cfc2a..93792923583 100644
--- a/SECURITY.txt
+++
Hello all,
this patch checks in mdcompact, the tool written in elisp that I used
to mass convert all the multi choice pattern in the aarch64 back-end to
the new compact syntax.
I tested it on Emacs 29 (might run on older versions as well not
sure), also I verified it runs cleanly on a few other
The stringop strategy selection algorithm falls back to a libcall strategy
when it exhausts its pool of available strategies. The memory area copy
function (memcpy) is not available from the system library for non-default
address spaces, so the compiler emits the most trivial byte-at-a-time
copy
> Your suggested code seems work fine, let me run more test and send
> v2, I guess I just don’t know how to explain why it work in comment
> :p
If it's too convoluted maybe we should rather not use it :D
The idea is for
factor % (vlenb / potential_div) == 0
we're actually looking for the
On 05/10/2023 21:59, Jan Hubicka wrote:
Like Wahlen et al this implementation records coverage in fixed-size
bitsets which gcov knows how to interpret. This is very fast, but
introduces a limit on the number of terms in a single boolean
expression, the number of bits in a gcov_unsigned_type
On 10/5/23 08:56, Richard Kenner wrote:
At that particular time I think Kenner was mostly focused on the alpha
and ppc ports, but I think he was also still poking around with romp and
a29k. I think romp is an unlikely target for this because it didn't
promote modes and it wasn't even
On Thu, Oct 05, 2023 at 04:42:42PM +0200, Jan Hubicka wrote:
> It does look like a nice cleanup to me.
> I wonder if you did some compare of the bit information propagated with
> new code and old code? Theoretically they should be equivalent?
Beyond testsuite, I've tried
__attribute__((noinline,
> At that particular time I think Kenner was mostly focused on the alpha
> and ppc ports, but I think he was also still poking around with romp and
> a29k. I think romp is an unlikely target for this because it didn't
> promote modes and it wasn't even building for several months
>
On 10/3/23 05:45, Manolis Tsamis wrote:
This is a new RTL pass that tries to optimize memory offset calculations
+
+/* If INSN is a root memory instruction then compute a potentially new offset
+ for it and test if the resulting instruction is valid. */
+static void
+do_check_validity
> Hi!
>
> The following patch removes ipa_bits struct pointer/vector from ipa
> jump functions and ipa cp transformations.
>
> The reason is because the struct uses widest_int to represent
> mask/value pair, which in the RFC patches to allow larger precisions
> for wide_int/widest_int is GC
> On 05/10/2023 22:39, Jørgen Kvalsvik wrote:
> > On 05/10/2023 21:59, Jan Hubicka wrote:
> > > >
> > > > Like Wahlen et al this implementation records coverage in fixed-size
> > > > bitsets which gcov knows how to interpret. This is very fast, but
> > > > introduces a limit on the number of
On Thu, Oct 5, 2023, 8:26 a.m. Jakub Jelinek wrote:
> Hi!
>
> The following patch removes ipa_bits struct pointer/vector from ipa
> jump functions and ipa cp transformations.
>
> The reason is because the struct uses widest_int to represent
> mask/value pair, which in the RFC patches to allow
On 05/10/2023 22:39, Jørgen Kvalsvik wrote:
On 05/10/2023 21:59, Jan Hubicka wrote:
Like Wahlen et al this implementation records coverage in fixed-size
bitsets which gcov knows how to interpret. This is very fast, but
introduces a limit on the number of terms in a single boolean
expression,
Hi Robin,
> -Original Message-
> From: Robin Dapp
> Sent: Thursday, October 5, 2023 3:06 PM
> To: Tamar Christina ; gcc-patches patc...@gcc.gnu.org>; Richard Biener
> Cc: rdapp@gmail.com
> Subject: Re: [PATCH] ifcvt/vect: Emit COND_ADD for conditional scalar
> reduction.
>
> Hi
On Thu, Oct 05, 2023 at 02:01:40PM +, Tamar Christina wrote:
> gcc/ChangeLog:
>
> * tree-if-conv.cc (INCLUDE_ALGORITHM): Remove.
> (typedef struct ifcvt_arg_entry): New.
> (cmp_arg_entry): New.
> (gen_phi_arg_condition, gen_phi_nest_statement,
>
This patch adds support in gcc+gcov for modified condition/decision
coverage (MC/DC) with the -fprofile-conditions flag. MC/DC is a type of
test/code coverage and it is particularly important in the avation and
automotive industries for safety-critical applications. MC/DC it is
required for or
Hi Tamar,
> The only comment I have is whether you actually need this helper
> function? It looks like all the uses of it are in cases you have, or
> will call conditional_internal_fn_code directly.
removed the cond_fn_p entirely in the attached v3.
Bootstrapped and regtested on x86_64, aarch64
> On Tue, Oct 03, 2023 at 11:41:01AM +, Tamar Christina wrote:
> > > We have stablesort method instead of qsort but that would require
> > > consistent ordering in the vector (std::sort doesn't ensure stable
> > > sorting either).
> > >
> > > If it is a non-issue, the patch is ok with the
Hi Robin:
Your suggested code seems work fine, let me run more test and send v2, I
guess I just don’t know how to explain why it work in comment :p
Robin Dapp 於 2023年10月5日 週四，03:57寫道：
> >> I think the "max poly value" is the LMUL 1 mode coeffs[1]
> >>
> >> See int vlenb =
On 05/10/2023 21:59, Jan Hubicka wrote:
Like Wahlen et al this implementation records coverage in fixed-size
bitsets which gcov knows how to interpret. This is very fast, but
introduces a limit on the number of terms in a single boolean
expression, the number of bits in a gcov_unsigned_type
> So I think Kenner's code is trying to prevent having a value in a
> SUBREG that is inconsistent with the SUBREG_PROMOTED* flag bits. But
> I think it's been unnecessary since Matz's rewrite in 2009.
I couldn't really tell what the rewrite does entirely so I tried creating
a case where we would
Applied the following patch.
Johann
LibF7: Remove uses of attribute pure.
libgcc/config/avr/libf7/
* libf7.h (F7_PURE): Remove all occurrences.
* libf7.c: Same.
diff --git a/libgcc/config/avr/libf7/libf7.c
b/libgcc/config/avr/libf7/libf7.c
index 373a8a55d90..0d9e4c325b2
> On Thu, Oct 05, 2023 at 03:04:55PM +0200, Jan Hubicka wrote:
> > > diff --git a/gcc/ipa-utils.cc b/gcc/ipa-utils.cc
> > > index 956c6294fd7..1355ccac6f0 100644
> > > --- a/gcc/ipa-utils.cc
> > > +++ b/gcc/ipa-utils.cc
> > > @@ -651,13 +651,16 @@ ipa_merge_profiles (struct cgraph_node *dst,
> > >
> gcc/ChangeLog:
>
> 2023-09-19 Martin Jambor
>
> PR ipa/57
> * ipa-prop.h (struct ipa_argagg_value): Newf flag killed.
> * ipa-modref.cc (ipcp_argagg_and_kill_overlap_p): New function.
> (update_signature): Mark any any IPA-CP aggregate constants at
>
On Thu, Oct 05, 2023 at 03:04:55PM +0200, Jan Hubicka wrote:
> > diff --git a/gcc/ipa-utils.cc b/gcc/ipa-utils.cc
> > index 956c6294fd7..1355ccac6f0 100644
> > --- a/gcc/ipa-utils.cc
> > +++ b/gcc/ipa-utils.cc
> > @@ -651,13 +651,16 @@ ipa_merge_profiles (struct cgraph_node *dst,
> > {
> PR 57 points to another place where IPA-CP collected aggregate
> compile-time constants need to be filtered, in addition to the one
> place that already does this in ipa-sra. In order to re-use code,
> this patch turns the common bit into a template.
>
> The functionality is still covered
This is a small tweak in LibF7 to save one multiplication in computation
of denominator polynomials. The polynomials are monic now, and
f7_horner needs one multiplication less.
Johann
--
LibF7: Use monic denominator polynomials to save a multiplication.
libgcc/config/avr/libf7/
*
On 10/5/23 12:42, Richard Earnshaw wrote:
On 03/10/2023 16:18, Victor Do Nascimento wrote:
This patch adds the `aarch64-sys-regs.def' file to GCC, teaching
the compiler about system registers known to the assembler and how
these can be used.
The macros used to hold system register
> diff --git a/gcc/ipa-utils.cc b/gcc/ipa-utils.cc
> index 956c6294fd7..1355ccac6f0 100644
> --- a/gcc/ipa-utils.cc
> +++ b/gcc/ipa-utils.cc
> @@ -651,13 +651,16 @@ ipa_merge_profiles (struct cgraph_node *dst,
> {
> edge srce = EDGE_SUCC (srcbb, i);
>
Hi,
can you please also squash those changes which fixes patch #1
so it is easier to review?
Honza
> From: Jørgen Kvalsvik
>
> ---
> gcc/gcov.cc | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/gcov.cc b/gcc/gcov.cc
> index 274f2fc5d9f..35be97cf5ac 100644
> ---
>
> Like Wahlen et al this implementation records coverage in fixed-size
> bitsets which gcov knows how to interpret. This is very fast, but
> introduces a limit on the number of terms in a single boolean
> expression, the number of bits in a gcov_unsigned_type (which is
> typedef'd to uint64_t),
On 05/10/2023 13:26, Richard Earnshaw wrote:
On 03/10/2023 16:18, Victor Do Nascimento wrote:
Motivated by the need to print system register names in output
assembly, this patch adds the required logic to
`aarch64_print_operand' to accept rtxs of type CONST_STRING and
process these
On 03/10/2023 16:18, Victor Do Nascimento wrote:
In implementing the ACLE read/write system register builtins it was
observed that leaving argument type checking to be done at expand-time
meant that poorly-formed function calls were being "fixed" by certain
optimization passes, meaning bad
On 10/5/23 13:26, Richard Earnshaw wrote:
On 03/10/2023 16:18, Victor Do Nascimento wrote:
Motivated by the need to print system register names in output
assembly, this patch adds the required logic to
`aarch64_print_operand' to accept rtxs of type CONST_STRING and
process these accordingly.
On Thu, Oct 05, 2023 at 01:52:30PM +0200, Jan Hubicka wrote:
> > From: Sergei Trofimovich
> >
> > r14-3459-g0c78240fd7d519 "Check that passes do not forget to define profile"
> > exposed check failures in cases when gcc produces uninitialized profile
> > probabilities. In case of PR/111559
On 03/10/2023 16:18, Victor Do Nascimento wrote:
Implement the aarch64 intrinsics for reading and writing system
registers with the following signatures:
uint32_t __arm_rsr(const char *special_register);
uint64_t __arm_rsr64(const char *special_register);
void*
Hi!
My earlier version of the ipa_bits removal patch resulted in self-test
failures in sreal. When debugging it, I was really confused that I couldn't
find verify_arithmetics function in the source. Turns out it had bad
spelling...
Bootstrapped/regtested on x86_64-linux and i686-linux,
On 03/10/2023 16:18, Victor Do Nascimento wrote:
Motivated by the need to print system register names in output
assembly, this patch adds the required logic to
`aarch64_print_operand' to accept rtxs of type CONST_STRING and
process these accordingly.
Consequently, an rtx such as:
(set
Hi!
The following patch removes ipa_bits struct pointer/vector from ipa
jump functions and ipa cp transformations.
The reason is because the struct uses widest_int to represent
mask/value pair, which in the RFC patches to allow larger precisions
for wide_int/widest_int is GC unfriendly because
On 03/10/2023 16:18, Victor Do Nascimento wrote:
Given the implementation of a mechanism of encoding system registers
into GCC, this patch provides the mechanism of validating their use by
the compiler. In particular, this involves:
1. Ensuring a supplied string corresponds to a known
PR 57 shows that IPA-modref and IPA-CP (when plugged into value
numbering) can optimize out a store both before a call (because the
call will overwrite it) and in the call (because the store is of the
same value) and by eliminating both create miscompilation.
This patch fixes that by pruning
This patch makes the previous one less conservative by looking whether
there are known ipa-modref loads from areas covered by the IPA-CP
aggregate constant entry in question. Because ipa-modref relies on
alias information which IPA-CP does not have (yet), the test is much
more crude and only
PR 57 points to another place where IPA-CP collected aggregate
compile-time constants need to be filtered, in addition to the one
place that already does this in ipa-sra. In order to re-use code,
this patch turns the common bit into a template.
The functionality is still covered by testcase
Hi Uros,
Very many thanks for the speedy reviews.
Uros Bizjak wrote:
> On Thu, Oct 5, 2023 at 11:06 AM Roger Sayle
> wrote:
> >
> >
> > This patch avoids long lea instructions for performing x<<2 and x<<3
> > by splitting them into shorter sal and move (or xchg instructions).
> > Because this
On Thu, Oct 5, 2023 at 1:45 PM Roger Sayle wrote:
>
> Doh! ENOPATCH.
>
> > -Original Message-
> > From: Roger Sayle
> > Sent: 05 October 2023 12:44
> > To: 'gcc-patches@gcc.gnu.org'
> > Cc: 'Uros Bizjak'
> > Subject: [X86 PATCH] Implement doubleword shift left by 1 bit using
> add+adc.
On 03/10/2023 16:18, Victor Do Nascimento wrote:
This patch defines the structure of a new .def file used for
representing the aarch64 system registers, what information it should
hold and the basic framework in GCC to process this file.
Entries in the aarch64-system-regs.def file should be
Committed, thanks Jeff and Robin.
Pan
-Original Message-
From: Jeff Law
Sent: Wednesday, October 4, 2023 11:40 PM
To: Robin Dapp ; Juzhe-Zhong ;
gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; kito.ch...@sifive.com
Subject: Re: [PATCH] RISC-V: Remove @ of vec_series
On 10/4/23
1 - 100 of 120 matches
Mail list logo
