Pushed to r14-9743.
在 2024/4/2 上午9:20, Yang Yujie 写道:
gcc/ChangeLog:
* config/loongarch/t-loongarch: Add loongarch-def-arrays.h
to OPTION_H_EXTRA.
---
gcc/config/loongarch/t-loongarch | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
Pushed to r14-9742.
Rebase to the latest, and modify invoke.texi to add a description of the
TLS DESC compilation option.
在 2024/3/19 上午9:54, mengqinggang 写道:
Add support for TLS descriptors on normal code model and extreme code model.
Normal code model instruction sequence:
Pushed to r14-9741.
在 2024/4/1 上午11:08, Lulu Cheng 写道:
Fixes: d28ea8e5a704 ("LoongArch: Split loongarch_option_override_internal
into smaller procedures")
gcc/ChangeLog:
* config/loongarch/loongarch.opt.urls: Regenerate.
---
在 2024/4/1 下午7:24, Mark Wielaard 写道:
Hi,
On Mon, Apr 01, 2024 at 11:08:08AM +0800, Lulu Cheng wrote:
Fixes: d28ea8e5a704 ("LoongArch: Split loongarch_option_override_internal
into smaller procedures")
gcc/ChangeLog:
* config/loongarch/loongarch.opt.urls:
在 2024/4/1 下午9:51, Xi Ruoyao 写道:
Is this patch targeting GCC 14 or 15? If 14 I guess we'd commit now...
Generally we don't add features in stage 4, but if we keep trad as the
default I think it'd be OK. And RISC-V guys plan to push their TLS desc
implementation this week too.
I've rebase
Pushed to r12-10303.
在 2024/3/17 上午10:02, Lulu Cheng 写道:
LTO option streaming and target attributes both require per-function
target configuration, which is achieved via option save/restore.
We implement TARGET_OPTION_{SAVE,RESTORE} to switch the la_target
context in addition to other
Pushed to r13-8545.
在 2024/3/17 上午10:02, Lulu Cheng 写道:
LTO option streaming and target attributes both require per-function
target configuration, which is achieved via option save/restore.
We implement TARGET_OPTION_{SAVE,RESTORE} to switch the la_target
context in addition to other
在 2024/4/1 上午9:29, Xi Ruoyao 写道:
On Fri, 2024-03-29 at 09:23 +0800, chenglulu wrote:
I tested spec2006. In the floating-point program, the test items with large
fluctuations are removed, and the rest is basically unchanged.
The fixed-point 464.h264ref (10,10) was 6.7% higher than (5,5
Pushed to r14-9737.
在 2024/3/30 下午4:43, Yang Yujie 写道:
gcc/ChangeLog:
* config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]recip as
aliases to -mrecip={all,none}, respectively.
* config/loongarch/loongarch.opt: Regenerate.
* config/loongarch/loongarch-def.h
Pushed to r14-9736.
在 2024/3/30 下午3:58, Lulu Cheng 写道:
Add descriptions for the compilation options '-mfrecipe' '-mdiv32'
'-mlam-bh' '-mlamcas' and '-mld-seq-sa'.
gcc/ChangeLog:
* doc/invoke.texi: Add descriptions for the compilation
options.
---
gcc/doc/invoke.texi | 45
在 2024/3/27 下午8:42, Xi Ruoyao 写道:
On Wed, 2024-03-27 at 18:39 +0800, Xi Ruoyao wrote:
On Wed, 2024-03-27 at 10:38 +0800, chenglulu wrote:
在 2024/3/26 下午5:48, Xi Ruoyao 写道:
The latency of LA464 and LA664 division instructions depends on the
input. When I updated the costs in r14-6642, I
在 2024/3/27 下午8:42, Xi Ruoyao 写道:
On Wed, 2024-03-27 at 18:39 +0800, Xi Ruoyao wrote:
On Wed, 2024-03-27 at 10:38 +0800, chenglulu wrote:
在 2024/3/26 下午5:48, Xi Ruoyao 写道:
The latency of LA464 and LA664 division instructions depends on the
input. When I updated the costs in r14-6642, I
在 2024/3/26 下午5:48, Xi Ruoyao 写道:
The latency of LA464 and LA664 division instructions depends on the
input. When I updated the costs in r14-6642, I unintentionally set the
division costs to the best-case latency (when the first operand is 0).
Per a recent discussion [1] we should use
Pushed to r14-9562...r14-9564.
在 2024/3/15 上午9:30, Chenghui Pan 写道:
Changes from v1: Some correction about ChangeLog format.
There's some unused/redundant definitions inside LoongArch target support
codes, these patches make a simple cleanup. Regression test passed.
Chenghui Pan (3):
在 2024/3/18 下午5:34, Xi Ruoyao 写道:
We were assuming TYPE_NO_NAMED_ARGS_STDARG_P don't have any named
arguments and there is nothing to advance, but that is not the case
for (...) functions returning by hidden reference which have one such
artificial argument. This is causing
Pushed to r14-9486.
在 2024/3/14 上午9:26, Chenghui Pan 写道:
The behavior of non-zero unused bits in xvpermi.q instruction's
third operand is undefined on LoongArch, according to our
discussion (https://github.com/llvm/llvm-project/pull/83540),
we think that keeping original insn operand as
在 2024/3/13 下午9:03, Xi Ruoyao 写道:
If this insn is really used, we'll have something like
slti $r4,$r0,$r5
in the code. The assembler will reject it because slti wants 2
register operands and 1 immediate operand. But we've not got any bug
report for this, indicating this define_insn is
在 2024/3/9 上午9:48, chenglulu 写道:
Pushed to r14-9407.
Cherry picked to r13-8413 and r12-10200.
在 2024/3/7 上午9:12, Lulu Cheng 写道:
If the hardware does not support LAMCAS, atomic_compare_and_swapsi
needs to be
implemented through "ll.w+sc.w". In the implementation of the
instructio
Pushed to r14-9407.
在 2024/3/7 上午9:12, Lulu Cheng 写道:
If the hardware does not support LAMCAS, atomic_compare_and_swapsi needs to be
implemented through "ll.w+sc.w". In the implementation of the instruction
sequence,
it is necessary to determine whether the two registers are equal.
Since
Pushed to r14-9408.
在 2024/3/7 上午9:50, Lulu Cheng 写道:
When the value of the macro DEFAULT_CFLAGS is set to '-ansi -pedantic-errors',
regname-s9-fp.c will test to fail. To solve this problem, add the compilation
option '-Wno-pedantic -std=gnu90' to this test case.
gcc/testsuite/ChangeLog:
在 2024/3/8 下午2:22, Xi Ruoyao 写道:
On Thu, 2024-03-07 at 21:07 +0800, chenglulu wrote:
在 2024/3/7 下午8:52, Xi Ruoyao 写道:
It should be better to extend the expected value before the ll/sc loop
(like what LLVM does), instead of repeating the extending in each
iteration. Something like:
I wanted
在 2024/3/7 下午8:52, Xi Ruoyao 写道:
It should be better to extend the expected value before the ll/sc loop
(like what LLVM does), instead of repeating the extending in each
iteration. Something like:
I wanted to do this at first, but it didn't work out.
But then I thought about it, and there
Pushed to r14-9352.
在 2024/3/6 下午4:54, chenxiaolong 写道:
In simd_correctness_check.h, the role of the macro ASSERTEQ_64 is to check the
result of the passed vector values for the 64-bit data of each array element.
It turns out that it uses the abs() function to check only the lower 32 bits
of
Pushed to r14-9351.
在 2024/3/6 上午9:19, Yang Yujie 写道:
gcc/ChangeLog:
* config.gcc: Add a case for loongarch*-*-linux-musl*.
* config/loongarch/linux.h: Disable the multilib-compatible
treatment for *musl* targets.
* config/loongarch/musl.h: New file.
---
在 2024/3/1 下午5:39, mengqinggang 写道:
Thanks, I try to send a new version patch next week.
在 2024/2/29 下午2:08, Xi Ruoyao 写道:
On Thu, 2024-02-29 at 09:42 +0800, mengqinggang wrote:
Generate la.tls.desc macro instruction for TLS descriptors model.
la.tls.desc expand to
pcalau12i $a0,
在 2024/3/7 下午12:05, mengqinggang 写道:
Hi,
Thanks, this patch is LGTM.
I don't have a problem either.
Thanks.
在 2024/3/7 上午10:56, Xi Ruoyao 写道:
On Thu, 2024-03-07 at 10:43 +0800, mengqinggang wrote:
Hi,
Whether to add an option to control the generation of R_LARCH_RELAX,
similar to as
This test case is so cleverly designed!
I have no problem. Thank you!
在 2024/3/5 下午9:00, Xi Ruoyao 写道:
Loops on named vector register are not vectorized (see comment 11 of
PR113622), so the these test cases have been failing for a while.
Rewrite them using check-function-bodies to remove hard
在 2024/3/5 下午7:50, Xi Ruoyao 写道:
The psABI allows using s9 as an alias of r22.
gcc/ChangeLog:
* config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add
s9 as an alias of r22.
---
v1 -> v2: Add a test case.
Ok for trunk?
Ok. Thanks!
在 2024/2/29 下午3:14, Xi Ruoyao 写道:
The psABI allows using s9 as an alias of r22.
gcc/ChangeLog:
* config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add
s9 as an alias of r22.
---
Bootstrapped and regtested on loongarch64-linux-gnu. Ok for trunk?
I think a test is
LGTM!
Thanks!
在 2024/2/26 下午12:28, Xi Ruoyao 写道:
Introduce an iterator for UNSPEC_CRC and UNSPEC_CRCC to make the next
change easier.
gcc/ChangeLog:
* config/loongarch/loongarch.md (CRC): New define_int_iterator.
(crc): New define_int_attr.
(loongarch_crc_w__w,
在 2024/2/23 上午11:27, Xi Ruoyao 写道:
On Fri, 2024-02-23 at 11:16 +0800, chenglulu wrote:
在 2024/2/22 下午5:17, Xi Ruoyao 写道:
The gold linker has never been ported to LoongArch (and it seems
unlikely to be ported in the future as the new architectures are
focusing on lld and/or mold for fast
Pushed to r14-9142.
在 2024/2/21 上午11:30, Lulu Cheng 写道:
In binutils 2.40 and earlier versions, only a warning will be reported
when a relocation immediate value is out of bounds. As a result,
the value of the macro HAVE_AS_COND_BRANCH_RELAXATION will also be
defined as 1 when the assembler does
在 2024/2/22 下午5:17, Xi Ruoyao 写道:
The gold linker has never been ported to LoongArch (and it seems
unlikely to be ported in the future as the new architectures are
focusing on lld and/or mold for fast linkers).
ChangeLog:
* configure.ac (ENABLE_GOLD): Remove loongarch*-*-* from
在 2024/2/22 下午6:20, Xi Ruoyao 写道:
To improve Binutils compatibility we've had to backported relaxation
support. But if a user just updates to GCC 13.3 and sticks with
Binutils 2.41, there is no reason to use -mno-explicit-relocs as the
default because we are turning off relaxation for
)
(unspec:SF [
(reg/v:SF 82 [ b ])
] UNSPEC_RECIPE)) "recip.c":4:12 -1
(nil))
during RTL pass: vregs
recip.c:5:1: 编译器内部错误：在 extract_insn 中，于 recog.cc:2812
0x135d1d4 _fatal_insn(char const*, rtx_def const*, char const*, int,
char const*)
/home/chenglulu/wor
Pushed to r13-8349...r13-8352.
在 2024/2/21 上午11:04, Lulu Cheng 写道:
Because binutils2.42 corrects the implementation of
".align [abs-expr,[abs-expr[,abs-expr]]]".
The macro ASM_OUTPUT_ALIGN_WITH_NOP in GCC uses this assembler directive,
and an error occurs. See link below for detailed
Pushed to r12-10169...r12-10172.
在 2024/2/21 上午11:10, Lulu Cheng 写道:
Because binutils2.42 corrects the implementation of
".align [abs-expr,[abs-expr[,abs-expr]]]".
The macro ASM_OUTPUT_ALIGN_WITH_NOP in GCC uses this assembler directive,
and an error occurs. See link below for detailed
Sorry, this title is incomplete and has been resent.
在 2024/2/21 上午11:08, Lulu Cheng 写道:
Because binutils2.42 corrects the implementation of
".align [abs-expr,[abs-expr[,abs-expr]]]".
The macro ASM_OUTPUT_ALIGN_WITH_NOP in GCC uses this assembler directive,
and an error occurs. See link below
在 2024/2/20 下午7:54, Xi Ruoyao 写道:
On Tue, 2024-02-20 at 19:50 +0800, chenglulu wrote:
在 2024/2/20 下午7:31, Xi Ruoyao 写道:
On Tue, 2024-02-20 at 19:25 +0800, Xi Ruoyao wrote:
On Tue, 2024-02-20 at 10:07 +0800, chenglulu wrote:
So I think that without worrying about performance and ensuring
在 2024/2/20 下午7:31, Xi Ruoyao 写道:
On Tue, 2024-02-20 at 19:25 +0800, Xi Ruoyao wrote:
On Tue, 2024-02-20 at 10:07 +0800, chenglulu wrote:
So I think that without worrying about performance and ensuring that
there is no problem
with binutils, I think we can make the following modifications
在 2024/2/9 下午4:08, Xi Ruoyao 写道:
On Fri, 2024-02-09 at 00:02 +0800, chenglulu wrote:
在 2024/2/7 上午12:23, Xi Ruoyao 写道:
Hi Lulu,
I'm proposing to backport r14-4674 "LoongArch: Delete macro definition
ASM_OUTPUT_ALIGN_WITH_NOP." to releases/gcc-12 and releases/gcc-13. The
r
Pushed to r14-9054.
在 2024/2/6 上午10:10, Lulu Cheng 写道:
gcc/ChangeLog:
* config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
symbol type conversions.
(__cacop_d): Likewise.
(__cpucfg): Likewise.
(__asrtle_d): Likewise.
(__asrtgt_d):
Pushed to r14-9053.
在 2024/2/6 上午10:10, Lulu Cheng 写道:
gcc/ChangeLog:
* config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
function return value type to unsigned short.
---
gcc/config/loongarch/larchintrin.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
在 2024/2/7 上午12:23, Xi Ruoyao 写道:
Hi Lulu,
I'm proposing to backport r14-4674 "LoongArch: Delete macro definition
ASM_OUTPUT_ALIGN_WITH_NOP." to releases/gcc-12 and releases/gcc-13. The
reasons:
1. Strictly speaking, the old ASM_OUTPUT_ALIGN_WITH_NOP macro may cause
a correctness issue.
在 2024/2/5 上午1:01, Xi Ruoyao 写道:
I have a question. I see that you often add compilation options in
BOOT_CFLAGS.
I also want to test it. Do you have a recommended set of compilation
options?
When I build a compiler for my system I use
{BOOT_{C,CXX,LD}FLAGS,{C,CXX,LD}FLAGS_FOR_TARGET}="-O3
在 2024/2/2 下午6:01, Jakub Jelinek 写道:
On Tue, Jan 30, 2024 at 10:09:51AM +0800, Lulu Cheng wrote:
From: chenguoqi
libsanitizer/ChangeLog:
* configure.tgt: Enable tsan and lsan for loongarch64.
* tsan/Makefile.am: Add tsan_rtl_loongarch64.S to
EXTRA_libtsan_la_SOURCES.
This
Pushed to r14-8784.
在 2024/2/2 上午9:42, Li Wei 写道:
This FAIL was introduced from r14-6908. The reason is that when merging
constant vector permutation implementations, the 128-bit matching situation
was not fully considered. In fact, the expansion of 128-bit vectors after
merging only supports
在 2024/2/3 下午4:58, Xi Ruoyao 写道:
We expanded (neg x) to (minus const0 x) for LSX FP vectors, this is
wrong because -0.0 is not 0 - 0.0. This causes some Python tests to
fail when Python is built with LSX enabled.
Use the vbitrevi.{d/w} instructions to simply reverse the sign bit
instead. We
在 2024/2/2 下午5:55, Xi Ruoyao 写道:
We call loongarch_symbol_insns with mode = MAX_MACHINE_MODE sometimes.
But in loongarch_symbol_insns:
if (LSX_SUPPORTED_MODE_P (mode) || LASX_SUPPORTED_MODE_P (mode))
return 0;
And LSX_SUPPORTED_MODE_P is defined as:
#define
在 2024/2/2 下午6:01, Jakub Jelinek 写道:
On Tue, Jan 30, 2024 at 10:09:51AM +0800, Lulu Cheng wrote:
From: chenguoqi
libsanitizer/ChangeLog:
* configure.tgt: Enable tsan and lsan for loongarch64.
* tsan/Makefile.am: Add tsan_rtl_loongarch64.S to
EXTRA_libtsan_la_SOURCES.
This
LGTM!
Thanks!
在 2024/2/2 上午5:54, Xi Ruoyao 写道:
When bootstrapping GCC 14 --with-build-config=bootstrap-lto, an ODR
violation is detected:
../../gcc/config/loongarch/loongarch-opts.cc:57: warning:
'abi_minimal_isa' violates the C++ One Definition Rule [-Wodr]
57 |
Pushed to r14-8723.
在 2024/1/24 下午5:19, Jiahao Xu 写道:
gcc/ChangeLog:
* config/loongarch/larchintrin.h
(__frecipe_s): Update function return type.
(__frecipe_d): Ditto.
(__frsqrte_s): Ditto.
(__frsqrte_d): Ditto.
gcc/testsuite/ChangeLog:
*
Ping?
在 2024/1/30 上午10:09, Lulu Cheng 写道:
From: chenguoqi
libsanitizer/ChangeLog:
* configure.tgt: Enable tsan and lsan for loongarch64.
* tsan/Makefile.am: Add tsan_rtl_loongarch64.S to
EXTRA_libtsan_la_SOURCES.
* tsan/Makefile.in: Regenerate.
---
Pushed to r14-8722.
在 2024/1/26 下午4:41, Li Wei 写道:
We found that when only 128-bit vectorization was enabled, 549.fotonik3d_r
failed to vectorize effectively. For this reason, we adjust the cost of
128-bit vector_stmt that match the multiply-add pattern to facilitate 128-bit
vectorization.
The
Pushed to r14-8717...r14-8721.
在 2024/1/29 下午4:21, Lulu Cheng 写道:
When cmodel=extreme, since the symbol address is obtained through four
instructions,
errors may occur in some cases during linking. Xi Ruoyao fixes this problem.
Pushed to r14-8716.
在 2024/1/30 下午3:55, Lulu Cheng 写道:
Modify address calculation logic from (((a x C) + fp) + offset) to ((fp +
offset) + a x C).
Thereby modifying the register dependencies and optimizing the code.
The value of C is 2 4 or 8.
The following is the assembly code before and
在 2024/1/27 下午10:03, chenglulu 写道:
在 2024/1/27 下午7:11, Xi Ruoyao 写道:
On Sat, 2024-01-27 at 18:02 +0800, Xi Ruoyao wrote:
On Sat, 2024-01-27 at 11:15 +0800, chenglulu wrote:
在 2024/1/26 下午6:57, Xi Ruoyao 写道:
On Fri, 2024-01-26 at 16:59 +0800, chenglulu wrote:
在 2024/1/26 下午4:49, Xi Ruoyao
在 2024/1/27 下午7:11, Xi Ruoyao 写道:
On Sat, 2024-01-27 at 18:02 +0800, Xi Ruoyao wrote:
On Sat, 2024-01-27 at 11:15 +0800, chenglulu wrote:
在 2024/1/26 下午6:57, Xi Ruoyao 写道:
On Fri, 2024-01-26 at 16:59 +0800, chenglulu wrote:
在 2024/1/26 下午4:49, Xi Ruoyao 写道:
On Fri, 2024-01-26 at 15:37
在 2024/1/26 下午6:57, Xi Ruoyao 写道:
On Fri, 2024-01-26 at 16:59 +0800, chenglulu wrote:
在 2024/1/26 下午4:49, Xi Ruoyao 写道:
On Fri, 2024-01-26 at 15:37 +0800, Lulu Cheng wrote:
v3 -> v4:
1. Add macro support for TLS symbols
2. Added support for loading __get_tls_addr symbol addr
在 2024/1/26 下午6:57, Xi Ruoyao 写道:
On Fri, 2024-01-26 at 16:59 +0800, chenglulu wrote:
在 2024/1/26 下午4:49, Xi Ruoyao 写道:
On Fri, 2024-01-26 at 15:37 +0800, Lulu Cheng wrote:
v3 -> v4:
1. Add macro support for TLS symbols
2. Added support for loading __get_tls_addr symbol addr
在 2024/1/26 下午4:59, chenglulu 写道:
在 2024/1/26 下午4:52, Xi Ruoyao 写道:
On Fri, 2024-01-26 at 15:37 +0800, Lulu Cheng wrote:
+(define_insn "@load_tls"
[(set (match_operand:P 0 "register_operand" "=r")
(unspec:P
[(match
在 2024/1/26 下午4:49, Xi Ruoyao 写道:
On Fri, 2024-01-26 at 15:37 +0800, Lulu Cheng wrote:
v3 -> v4:
1. Add macro support for TLS symbols
2. Added support for loading __get_tls_addr symbol address using call36.
3. Merge template got_load_tls_{ld/gd/le/ie}.
4. Enable explicit reloc for
在 2024/1/26 下午4:52, Xi Ruoyao 写道:
On Fri, 2024-01-26 at 15:37 +0800, Lulu Cheng wrote:
+(define_insn "@load_tls"
[(set (match_operand:P 0 "register_operand" "=r")
(unspec:P
[(match_operand:P 1 "symbolic_operand" "")]
- UNSPEC_TLS_GD))]
+
Pushed to r14-8447.
在 2024/1/16 上午10:23, Jiahao Xu 写道:
For below pattern, can be treated as a simple move because floating point
and vector share a common register on loongarch64.
(set (reg/v:SF 32 $f0 [orig:93 res ] [93])
(vec_select:SF (reg:V8SF 32 $f0 [115])
(parallel [
Pushed to r14-8444.
在 2024/1/24 下午5:44, Li Wei 写道:
We found that in the spec17 521.wrf program, some loop invariant code generated
from single-precision floating-point approximate division calculation failed to
propose a loop. This is because the pseudo-register that stores the
intermediate
在 2024/1/26 下午3:32, Richard Biener 写道:
On Fri, Jan 26, 2024 at 7:23 AM chenxiaolong wrote:
gcc/testsuite/ChangeLog:
OK
Pushed to r14-8445.
Thank you everyone for your review!
* gcc.dg/signbit-2.c: Added additional "-mlsx" compilation options.
*
Pushed to r14-8446.
在 2024/1/16 上午10:32, Jiahao Xu 写道:
Define LOGICAL_OP_NON_SHORT_CIRCUIT as 0, for a short-circuit branch, use the
short-circuit operation instead of the non-short-circuit operation.
SPEC2017 performance evaluation shows 1% performance improvement for fprate
GEOMEAN and no
在 2024/1/24 下午5:36, Li Wei 写道:
We found that when only 128-bit vectorization was enabled, 549.fotonik3d_r
failed to vectorize effectively. For this reason, we adjust the cost of
128-bit vector_stmt that match the multiply-add pattern to facilitate 128-bit
vectorization.
The experimental
Pushed to r14-8414.
在 2024/1/24 下午5:19, Jiahao Xu 写道:
It is incorrect to use vld/vori to implement the vec_concatz because when
the LSX
instruction is used to update the value of the vector register, the upper 128
bits of
the vector register will not be zeroed.
gcc/ChangeLog:
*
Jiahao:
Note that the LoongArch 'a' in the title needs to be capitalized.
I modified this patch and incorporated it first.
在 2024/1/24 下午5:19, Jiahao Xu 写道:
It is incorrect to use vld/vori to implement the vec_concatz because when
the LSX
instruction is used to update the value of the
Pushed to r14-8412.
在 2024/1/23 上午11:54, Lulu Cheng 写道:
TLS gd ld and ie type symbols will generate corresponding GOT entries,
so non-zero offsets cannot be generated.
The address of TLS le type symbol+addend is not implemented in binutils,
so non-zero offset is not generated here for the time
在 2024/1/24 下午5:58, Jiahao Xu 写道:
在 2024/1/24 下午5:48, Xi Ruoyao 写道:
On Wed, 2024-01-24 at 17:19 +0800, Jiahao Xu wrote:
gcc/ChangeLog:
* config/loongarch/larchintrin.h
(__frecipe_s): Update function return type.
(__frecipe_d): Ditto.
(__frsqrte_s): Ditto.
(__frsqrte_d):
在 2024/1/24 上午3:36, Xi Ruoyao 写道:
On Mon, 2024-01-22 at 15:27 +0800, chenglulu wrote:
The failure of this test case was because the compiler believes that two
(UNSPEC_PCREL_64_PART2 [(symbol)]) instances would always produce the
same result, but this isn't true because the result depends
LGTM!
Thanks!
在 2024/1/23 下午7:35, Xi Ruoyao 写道:
When building GCC with --enable-default-ssp, the stack protector is
enabled for got-load.C, causing additional GOT loads for
__stack_chk_guard. So mem/u will be matched more than 2 times and the
test will fail.
Disable stack protector to fix
在 2024/1/23 下午4:04, Xi Ruoyao 写道:
On Tue, 2024-01-23 at 10:37 +0800, chenglulu wrote:
LGTM!
Thanks!
Pushed v2 as attached. The only change is in the comment: Qinggang told
me TLE LE relaxation actually *requires* explicit relocs.
I think one of the reasons is also because we cannot
Pushed to r14-8344.
在 2024/1/17 上午9:24, chenxiaolong 写道:
gcc/ChangeLog:
* doc/sourcebuild.texi: Add attributes for keywords.
---
gcc/doc/sourcebuild.texi | 20
1 file changed, 20 insertions(+)
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
LGTM!
Thanks!
在 2024/1/23 上午2:42, Xi Ruoyao 写道:
Binutils 2.42 supports TLS LD/GD relaxation which requires the assembler
macro.
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
在 2024/1/19 下午4:51, chenglulu 写道:
在 2024/1/19 下午1:46, Xi Ruoyao 写道:
On Wed, 2024-01-17 at 17:57 +0800, chenglulu wrote:
Virtual register 1479 will be used in insn 2744, but register 1479
was
assigned the REG_UNUSED attribute in the previous instruction.
The attached file is the wrong file
Hi, Jiahao:
This patch will introduce redundant FAIL, and the reason needs to be explained.
+FAIL: gcc.dg/tree-ssa/copy-headers-8.c scan-tree-dump-times ch2 "Conditional
combines static and invariant" 1
+FAIL: gcc.dg/tree-ssa/copy-headers-8.c scan-tree-dump-times ch2 "Will duplicate
bb" 2
在 2024/1/19 下午1:46, Xi Ruoyao 写道:
On Wed, 2024-01-17 at 17:57 +0800, chenglulu wrote:
Virtual register 1479 will be used in insn 2744, but register 1479 was
assigned the REG_UNUSED attribute in the previous instruction.
The attached file is the wrong file.
The compilation command
在 2024/1/18 下午4:49, chenglulu 写道:
在 2024/1/18 下午3:44, Xi Ruoyao 写道:
On Thu, 2024-01-18 at 15:15 +0800, chenglulu wrote:
gcc.dg/tree-ssa/scev-16.c is OK to move
gcc.dg/pr104992.c should simply add -fno-tree-vectorize to the used
options and remove the vect_* stuff
Hi Richard:
I have
在 2024/1/18 下午3:44, Xi Ruoyao 写道:
On Thu, 2024-01-18 at 15:15 +0800, chenglulu wrote:
gcc.dg/tree-ssa/scev-16.c is OK to move
gcc.dg/pr104992.c should simply add -fno-tree-vectorize to the used
options and remove the vect_* stuff
Hi Richard:
I have a question. I don't understand
Pushed to r14-8204.
在 2024/1/13 下午3:28, chenxiaolong 写道:
1.Added dg-do compile on LoongArch.
When binutils does not support vector instruction sets, an error occurs
because the assembler does not recognize vector instructions.
2.Added "-mlsx" option for vectorization on LoongArch.
Pushed to r14-8203.
在 2024/1/13 下午2:37, Lulu Cheng 写道:
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_split_symbol):
Assign the '/u' attribute to the mem.
gcc/testsuite/ChangeLog:
* g++.target/loongarch/got-load.C: New test.
---
gcc.dg/tree-ssa/scev-16.c is OK to move
gcc.dg/pr104992.c should simply add -fno-tree-vectorize to the used
options and remove the vect_* stuff
Hi Richard:
I have a question. I don't understand the purpose of adding
'-fno-tree-vectorize' here.
Thanks!
在 2024/1/17 下午5:50, Xi Ruoyao 写道:
On Wed, 2024-01-17 at 17:38 +0800, chenglulu wrote:
在 2024/1/13 下午9:05, Xi Ruoyao 写道:
在 2024-01-13星期六的 15:01 +0800，chenglulu写道：
在 2024/1/12 下午7:42, Xi Ruoyao 写道:
在 2024-01-12星期五的 09:46 +0800，chenglulu写道：
I found an issue bootstrapping GCC with -mcmodel
在 2024/1/16 下午2:20, Xi Ruoyao 写道:
On Tue, 2024-01-16 at 14:16 +0800, chenglulu wrote:
在 2024/1/16 下午1:34, Xi Ruoyao 写道:
Ping.
On Fri, 2023-12-15 at 20:56 +0800, Xi Ruoyao wrote:
We don't allow SImode in FCC, so constraint z is never really used
here.
gcc/ChangeLog:
* config
在 2024/1/16 下午1:34, Xi Ruoyao 写道:
Ping.
On Fri, 2023-12-15 at 20:56 +0800, Xi Ruoyao wrote:
We don't allow SImode in FCC, so constraint z is never really used
here.
gcc/ChangeLog:
* config/loongarch/loongarch.md (movsi_internal): Remove
constraint z.
---
Bootstrapped and
在 2024/1/15 下午2:42, Xi Ruoyao 写道:
On Mon, 2024-01-15 at 14:32 +0800, YunQiang Su wrote:
Xi Ruoyao 于2024年1月15日周一 12:11写道：
On Mon, 2024-01-15 at 09:29 +0800, chenxiaolong wrote:
At 21:13 +0800 on Saturday, 2024-01-13, Xi Ruoyao wrote：
At 15:28 +0800 on Saturday 2024-01-13, chenxiaolong
在 2024/1/13 下午9:05, Xi Ruoyao 写道:
在 2024-01-13星期六的 15:01 +0800，chenglulu写道：
在 2024/1/12 下午7:42, Xi Ruoyao 写道:
在 2024-01-12星期五的 09:46 +0800，chenglulu写道：
I found an issue bootstrapping GCC with -mcmodel=extreme in BOOT_CFLAGS:
we need a target hook to tell the generic code
在 2024/1/12 下午7:42, Xi Ruoyao 写道:
在 2024-01-12星期五的 09:46 +0800，chenglulu写道：
I found an issue bootstrapping GCC with -mcmodel=extreme in BOOT_CFLAGS:
we need a target hook to tell the generic code
UNSPEC_LA_PCREL_64_PART{1,2} are just a wrapper around symbols, or we'll
see millions lines
Pushed to r14-7160 and r14-7161.
在 2024/1/11 下午7:36, Li Wei 写道:
We found that the current combine optimization pass in gcc cannot handle
the following redundant sign extension situations:
(insn 77 76 78 5 (set (reg:SI 143)
(plus:SI (subreg/s/u:SI (reg/v:DI 104 [ len ]) 0)
I found an issue bootstrapping GCC with -mcmodel=extreme in BOOT_CFLAGS:
we need a target hook to tell the generic code
UNSPEC_LA_PCREL_64_PART{1,2} are just a wrapper around symbols, or we'll
see millions lines of messages like
../../gcc/gcc/tree.h:4171:1: note: non-delegitimized UNSPEC
Pushed to r14-7134.
在 2024/1/11 上午9:07, Yang Yujie 写道:
LTO option streaming and target attributes both require per-function
target configuration, which is achieved via option save/restore.
We implement TARGET_OPTION_{SAVE,RESTORE} to switch the la_target
context in addition to other
Pushed to r14-7125.
在 2024/1/6 下午4:54, Lulu Cheng 写道:
There are two mode iterators defined in the loongarch.md:
(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
and
(define_mode_iterator X [(SI "!TARGET_64BIT") (DI "TARGET_64BIT")])
Replace the mode in the bit arithmetic
Pushed to r14-7097.
在 2024/1/10 下午3:25, chenxiaolong 写道:
The function of this test is to check that the compiler supports vectorization
using SLP and vec_{load/store/*}_lanes. However, vec_{load/store/*}_lanes are
not supported on LoongArch, such as the corresponding "st4/ld4" directives on
Pushed to r14-7096.
在 2024/1/10 下午3:24, chenxiaolong 写道:
After the code is committed in r14-6948, GCC regression testing on some
architectures will produce the following error:
"error executing dg-final: unknown effective target keyword `loongarch*-*-*'"
gcc/testsuite/ChangeLog:
*
Pushed to r14-7085...r14-7088
在 2024/1/8 上午9:14, Yang Yujie 写道:
This patchset performs some code cleanup, and is bootstrapped and regtested
on loongarch64-linux-gnu.
Changes from v1 -> v2:
* Replaced all TARGET_ macros from .opt.
* Fixed definition of ISA_HAS_LAMCAS.
Yang Yujie (4):
在 2024/1/10 上午3:51, Andreas Schwab 写道:
gcc: gcc.dg/vect/vect-outer-4a-big-array.c -flto -ffat-lto-objects: error
executing dg-final: unknown effective target keyword `loongarch*-*-*'
gcc: gcc.dg/vect/vect-outer-4a-big-array.c: error executing dg-final: unknown
effective target keyword
Pushed to r14-7022.
在 2024/1/5 下午3:38, Jiahao Xu 写道:
This patch implenments more vec_init optabs that can handle two LSX vectors
producing a LASX
vector by concatenating them. When an lsx vector is concatenated with an LSX
const_vector of
zeroes, the vec_concatz pattern can be used
1 - 100 of 322 matches
Mail list logo
