CC Robin who knows better than me in case of scheduling model in RISC-V
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-05-20 15:59
To: gcc-patches
CC: kito.cheng; palmer; tamar.christina; richard.guenther; Richard.Sandiford;
juzhe.zhong; zhengyu; pan2.li; xuli
Subject: [PATCH] RISC-V: Enable
LGTM.
juzhe.zh...@rivai.ai
RISC-V part LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-05-16 12:05
To: gcc-patches
CC: juzhe.zhong; kito.cheng; tamar.christina; richard.guenther;
Richard.Sandiford; Pan Li
Subject: [PATCH v2 3/3] RISC-V: Enable vectorizable early exit testsuite
From: Pan Li
After we supported
RISC-V part LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-05-16 12:05
To: gcc-patches
CC: juzhe.zhong; kito.cheng; tamar.christina; richard.guenther;
Richard.Sandiford; Pan Li
Subject: [PATCH v2 2/3] RISC-V: Implement vectorizable early exit with
vcond_mask_len
From: Pan Li
After
LGTM from my side. Wait for kito chime in.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-05-11 15:54
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar
From: Pan Li
For the vfw vx format RVV intrinsic
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-05-09 11:05
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Make full-vec-move1.c test robust for optimization
From: Pan Li
During investigate the support of early break autovec, we notice
the test full-vec
LGTM。
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2024-05-07 09:17
To: gcc-patches; kito.cheng; palmer; jeffreyalaw; rdapp; juzhe.zhong; pan2.li
CC: Kito Cheng
Subject: [PATCH][GCC 13] RISC-V: Fix vsetvli local eliminate [PR114747]
vsetvli local eliminate is only consider the current demand
Hi, Han.
GCC 14 is branch out. You can commit it to trunk (GCC 15).
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-04-02 16:30
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw; rdapp.gcc
Subject: [PATCH v2] RISC-V: Refine the condition for add additional vars in RVV
cost
LGTM from my side. But give kito more time chime in.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-28 11:53
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Fix ICE for legitimize move on subreg
const_poly_move
From: Pan Li
When we build with isl
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-04-25 19:23
To: gcc-patches
CC: rdapp.gcc; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw; Patrick
O'Neill
Subject: [PATCH] RISC-V: Add testcase for PR114749.
Hi,
this adds a test case for PR114749.
Going to commit as obvious
LGTM. THANKS
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-25 17:25
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li; Kito Cheng
Subject: [PATCH v1] RISC-V: Add test cases for insn does not satisfy its
constraints [PR114714]
From: Pan Li
We have one ICE when RVV register
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-25 09:25
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for highpart register overlap
of vwcvt
From: Pan Li
We reverted below patch for register group overlap, add
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-25 09:25
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll
From: Pan Li
We missed the existing early clobber for the dest operand of vwsll
pattern when
lgtm.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2024-04-24 18:09
To: gcc-patches; kito.cheng; rdapp; juzhe.zhong
CC: Kito Cheng
Subject: [PATCH][GCC 13] RISC-V: Fix recursive vsetvli checking [PR114172]
extract_single_source will recursive checking the sources to
make sure if it's single
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-24 10:48
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for highpart overlap of vext.vf
From: Pan Li
We reverted below patch for register group overlap, add the related
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-22 16:27
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for highpart overlap
floating-point widen insn
From: Pan Li
We reverted below patch for register group overlap, add
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-22 15:43
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v2] RISC-V: Add xfail test case for indexed load overlap with
SRC EEW < DEST EEW
From: Pan Li
Update in v2:
* Add change log to pr112431-3
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-22 14:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for highest-number regno
ternary overlap
From: Pan Li
We reverted below patch for register group overlap, add
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-22 11:19
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for widening register overlap
of vf4/vf8
From: Pan Li
We reverted below patch for register group overlap, add
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-20 09:04
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for wv insn register overlap
From: Pan Li
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr112431-42.c: New
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-12 14:08
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Bugfix ICE non-vector in
TARGET_FUNCTION_VALUE_REGNO_P
From: Pan Li
This patch would like to fix one ICE when vector is not enabled
in hook
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-11 11:51
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Remove -Wno-psabi for test build option [NFC]
From: Pan Li
Just notice there are some test case still have -Wno-psabi option,
which is deprecated
Thanks for fixing it. LGTM from my side.
I prefer wait kito for another ACK.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-11 10:16
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Bugfix ICE for the vector return arg in mode switch
From: Pan Li
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-08 16:09
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Refine the error msg for RVV intrinisc required ext
From: Pan Li
The RVV intrinisc API has sorts of required extension from both
the march
It's obvious fix to previous incorrect typo.
So LGTM to trunk (GCC-14).
Thanks.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-04-02 16:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw; rdapp.gcc
Subject: [PATCH] RISC-V: Minor fix for max_point
The program points start
Thanks for fixing it. LGTM to GCC-15 as Jeff suggested.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-04-02 16:30
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw; rdapp.gcc
Subject: [PATCH v2] RISC-V: Refine the condition for add additional vars in RVV
cost model
OK. It's an obvious fix but it seems to be unrelated to the PR.
Could you split it 2 separate patches ?
Thanks.
juzhe.zh...@rivai.ai
发件人： Demin Han
发送时间： 2024-03-28 19:06
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： kito.cheng; pan2.li; jeffreyalaw; Robin Dapp
主题： RE: [PATCH] RISC-V: Refine
Thanks a lot for trying to optimize the dynamic LMUL cost model.
The need_additional_vector_vars_p looks good to me.
But
- = (*program_points_per_bb.get (bb)).length () - 1;
+ = (*program_points_per_bb.get (bb)).length ();
I wonder why you remove - 1?
juzhe.zh
I think it's harmless to let this patch in GCC-14.
So LGTM from my side to land this path in GCC-14..
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-03-26 01:07
To: Jeff Law; 钟居哲; gcc-patches; palmer; kito.cheng
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: Add initial cost handling
LGTM.
juzhe.zh...@rivai.ai
From: Christoph Müllner
Date: 2024-03-22 07:45
To: gcc-patches; Kito Cheng; Palmer Dabbelt; Andrew Waterman; Philipp Tomsich;
Camel Coder; Bruce Hoult; Juzhe-Zhong; Jun Sha; Xianmiao Qu; Jin Ma
CC: Christoph Müllner
Subject: [PATCH] RISC-V: Don't add fractional
I can't review this stuff. Let kito review this.
Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-03-18 14:05
To: gcc-patches
CC: juzhe.zhong; kito.cheng; yanzhang.wang; Pan Li
Subject: [PATCH v1] RISC-V: Bugfix ICE for __attribute__((target("arch=+v"))
From: Pan Li
This p
ould it really be called autovec-max-lmul? We also use TARGET_MAX_LMUL
>>for builtins etc. Or are we just following LLVM's naming here?
>>Isn't -mrvv-max-lmul sufficient?
The original option is kito's recommandation. Both -mrvv-max-lmul and
-mrvv-autovec-max-lmul are ok for me.
juz
LGTM except a nit comment:
PR 114264 -> PR target/114264
No need to send V3, just commit it with this change.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-03-07 16:32
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw
Subject: [PATCH v2] RISC-V: Fix ICE in riscv vec
I suggest open an PR with a PR id.
juzhe.zh...@rivai.ai
发件人： Demin Han
发送时间： 2024-03-07 15:39
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： kito.cheng; pan2.li; jeffreyalaw
主题： RE: [PATCH] RISC-V: Fix ICE in riscv vector costs
OK.
Which is better for testcase name?
1. ice-biggestmode.c or
2
Could you plz add testcase ? I just noticed you didn't append a testcase (jpeg)
in this patch.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-03-07 13:54
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw
Subject: [PATCH] RISC-V: Fix ICE in riscv vector costs
The following
LGTM.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-03-07 13:54
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw
Subject: [PATCH] RISC-V: Fix ICE in riscv vector costs
The following code can result in ICE:
-march=rv64gcv_zba_zbb --param riscv-autovec-lmul=dynamic -O3
char
Thanks for support it.
I leave this patch review to kito who is much more familiar with it than me.
CCing more folks who may be interested at this stuff.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-03-06 14:38
To: gcc-patches
CC: juzhe.zhong; kito.cheng; yanzhang.wang; Pan Li
Subject
Hi, han.
I think you can commit this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2024-March/646931.html
RISC-V: Refactor expand_vec_cmp
It's an NFC patch that I approved.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-03-04 14:51
To: gcc-patches
CC: juzhe.zhong; kito.cheng
Subject
LGTM. Thanks for clean up.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-03-05 16:59
To: gcc-patches
CC: juzhe.zhong; kito.cheng; yanzhang.wang; Pan Li
Subject: [PATCH v1] RISC-V: Cleanup unused code in riscv_v_adjust_bytesize [NFC]
From: Pan Li
Cleanup mode_size related code which
: (vec_duplicate) (reg)))
juzhe.zh...@rivai.ai
From: Demin Han
Date: 2024-03-05 16:40
To: 钟居哲; gcc-patches
CC: kito.cheng; Li, Pan2; jeffreyalaw; Robin Dapp; richard.sandiford
Subject: RE: Re:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of
vec and imm
Hi,
I applied
Could you rebase to the trunk ? I don't think segment load store cost depends
on previous patch you sent.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-03-01 23:07
To: 钟居哲; gcc-patches; palmer; kito.cheng
CC: rdapp.gcc; Jeff Law
Subject: Re: [PATCH] RISC-V: Add initial cost handling
should remove them.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2024-02-28 22:55
To: 钟居哲
CC: pan2.li; gcc-patches; yanzhang.wang; rdapp.gcc; Jeff Law
Subject: Re: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for
RVV
Hmm, maybe only keep --param=riscv-autovec-preference=none
I suggest specify -fno-schedule-insns to force tests assembler never change for
any scheduling model.
juzhe.zh...@rivai.ai
From: Palmer Dabbelt
Date: 2024-02-28 08:55
To: jeffreyalaw
CC: juzhe.zhong; Robin Dapp; ewlu; gcc-patches; gnu-toolchain; pan2.li
Subject: Re: [PATCH] RISC-V: Update
Thanks for supporting this.
I'd rather leave this patch review to kito's since it's kito's proposal.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-02-27 09:17
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; zhengyu; xuli
Subject: [PATCH] RISC-V: Add riscv_vector_cc function attribute
From
If the scheduling model increases the vsetvls, we shouldn't set it as default
scheduling model
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-02-26 21:29
To: Edwin Lu; gcc-patches
CC: rdapp.gcc; gnu-toolchain; pan2.li; juzhe.zh...@rivai.ai
Subject: Re: [PATCH] RISC-V: Update test
(kind, stmt_info))
{
case 2:
stmt_cost += simd_costs->ld2_st2_permute_cost;
break;
case 3:
stmt_cost += simd_costs->ld3_st3_permute_cost;
break;
case 4:
stmt_cost += simd_costs->ld4_st4_permute_cost;
break;
}
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-02-26 23:54
To: gc
eturn DR_GROUP_SIZE (stmt_info);
}
return 0;
}
juzhe.zh...@rivai.ai
.
But I'd like to CC more RISC-V GCC folks to see the votes.
If most of the people don't want this in GCC-14 and defer it to GCC-15, I won't
insist on it.
Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2024-02-23 16:29
To: Kito Cheng; pan2.li
CC: gcc-patches; juzhe.zhong; yanzhang.wang
Sorry, I missed review the testcase:
+/* { dg-final { scan-assembler-times "vmv\.v\.i\tv\[0-9\],0" 0 } } */
I think you should use "scan-assembler-not"
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-02-23 04:02
To: gcc-patches; palmer; Kito Cheng; juzhe.zh...@ri
lgtm.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-02-23 04:02
To: gcc-patches; palmer; Kito Cheng; juzhe.zh...@rivai.ai
CC: rdapp.gcc; jeffreyalaw
Subject: [PATCH] RISC-V: Fix vec_init for simple sequences [PR114028].
Hi,
for a vec_init (_a, _a, _a, _a) with _a of mode DImode we try
Ping this patch which is simple fix on VSETVL PASS.
Ok for trunk ?
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2024-02-01 17:02
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH v2] RISC-V: Suppress the vsetvl fusion for conflict successors
Hi, Robin. Could you continue on this LICM issue ?
I am not sure whether my fix is correct, or you may find another way to make
LICM works ?
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-02-06 21:14
To: juzhe.zh...@rivai.ai; kito.cheng
CC: rdapp.gcc; gcc-patches; Kito.cheng; jeffreyalaw
Why is it 2 not 1 or other value ?
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-02-07 17:27
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinsic ICE in function
checker
From: Pan Li
There is another corn case
Did you run the C compiler compile C++ intrinsic test ?
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-02-06 16:09
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Bugfix for RVV overloaded intrinisc ICE when empty
args
From: Pan Li
I think it just trigger a latent bug that we didn't encounter.
Hi, Robin. Would you mind give me preprocessed file to reproduce the issue ?
I suspect it triggers latent bug in VSETVL PASS.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2024-02-05 12:36
To: Juzhe-Zhong; gcc-patches
CC: kito.cheng
a/gcc/loop-iv.cc b/gcc/loop-iv.cc
index eb7e923a38b..09750951845 100644
--- a/gcc/loop-iv.cc
+++ b/gcc/loop-iv.cc
@@ -646,10 +646,10 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode,
rtx reg,
if (!set)
return false;
- rhs = find_reg_equal_equiv_note (insn);
- if (rhs)
-rhs
Thanks. I wonder whether p600 will enable dynamic lmul by default ?
Does dynamic LMUL help with sifive p600 chip ?
juzhe.zh...@rivai.ai
From: Monk Chiang
Date: 2024-02-01 16:10
To: juzhe.zh...@rivai.ai
CC: gcc-patches; kito.cheng
Subject: Re: [PATCH v2] RISC-V: Support scheduling for sifive
/riscv-avlprop.cc:200
0x1fe3b05 pass_avlprop::execute(function*)
../../../../gcc/gcc/config/riscv/riscv-avlprop.cc:506
Would you mind taking a look at it ?
juzhe.zh...@rivai.ai
From: Edwin Lu
Date: 2024-02-01 14:13
To: juzhe.zh...@rivai.ai; gcc-patches
CC: Robin Dapp; kito.cheng
for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c (test for excess errors)
Your patch is good.
Thanks for the help.
juzhe.zh...@rivai.ai
From: Edwin Lu
Date: 2024-02-01 14:13
To: juzhe.zh...@rivai.ai; gcc-patches
CC: Robin Dapp; kito.cheng; jeffreyalaw; palmer; vineetg
Maybe I do the wrong testing. Let me use a clean linux environment and try
again.
juzhe.zh...@rivai.ai
From: Edwin Lu
Date: 2024-02-01 14:13
To: juzhe.zh...@rivai.ai; gcc-patches
CC: Robin Dapp; kito.cheng; jeffreyalaw; palmer; vineetg; Patrick O'Neill
Subject: Re: [COMMITTED V3 1/4] RISC-V
Hi, Monk.
This model doesn't include vector. Will you add vector pipeline in the
followup patches ?
juzhe.zh...@rivai.ai
ad_64-12.c (internal
compiler error: in validate_change_or_fail, at config/riscv/riscv-v.cc:4972)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12.c (test for
excess errors)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-3.c
(internal compiler error: in validate_change_or_fail, at
config/riscv/riscv-v.cc:4972)
juzhe.zh...@rivai.ai
ok
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2024-01-27 10:50
To: gcc-patches
CC: juzhe.zhong; Patrick O'Neill
Subject: [PATCH] RISC-V: Add require-effective-target to pr113429 testcase
The pr113429 testcase fails with newlib spike runs. Adding
require-effective-target rv64
It's fixed by this commit:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=d40b3c1e439db05c835b6bd4fd5bba58fda71dd6
juzhe.zh...@rivai.ai
From: Edwin Lu
Date: 2024-01-17 09:45
To: juzhe.zh...@rivai.ai; gcc-patches
CC: Patrick O'Neill
Subject: Re: [Committed V2] RISC-V: Fix regression (GCC-14
rv64 } */
/* { dg-require-effective-target riscv_v } */
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2024-01-24 09:20
To: juzhe.zh...@rivai.ai; gcc-patches
CC: kito.cheng; law; rdapp; vineetg
Subject: [Committed] RISC-V: Add regression test for vsetvl bug pr113429
The reduced testcase
-final { scan-assembler-not {csrr} } } */
This needs a XFAIL, I am not sure whether the spiling is reasonable, so XFAIL
this case.
We will analyze this case whether it is reasonable.
juzhe.zh...@rivai.ai
From: yanzhang.wang
Date: 2024-01-25 15:30
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2
ok
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2024-01-24 08:50
To: gcc-patches
CC: juzhe.zhong; kito.cheng; law; rdapp; vineetg; Patrick O'Neill
Subject: [PATCH] RISC-V: Add regression test for vsetvl bug pr113429
The reduced testcase for pr113429 (cam4 failure) needed additional
No, we didn't undo the optimization.
We just disallow move pattern for (set (reg) (VL_REGNUM)).
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-22 19:25
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Fix regressions due
OK I guess change register_operand into REG_P should fix those ICEs.
I will have a try and send a patch.
Thanks.
juzhe.zh...@rivai.ai
From: Andrew Pinski
Date: 2024-01-22 15:14
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng; kito.cheng; jeffreyalaw; vineetg; Robin Dapp;
palmer
-O3 -g (test for excess errors)
FAIL: gcc.dg/torture/pr48124-4.c -Os (internal compiler error: in
reg_or_subregno, at jump.cc:1895)
FAIL: gcc.dg/torture/pr48124-4.c -Os (test for excess errors)
juzhe.zh...@rivai.ai
LGTM.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-01-22 12:11
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH v2] RISC-V: Bugfix for resolve_overloaded_builtin[PR113420]
From: xuli
v2:
Avoid internal ICE for the case below.
vint8mf8_t test_vle8_v_i8mf8_m(vbool64_t
Ok.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2024-01-19 18:08
To: rep.dot.nop; jeffreyalaw; rdapp.gcc; juzhe.zhong; gcc-patches
CC: Kito Cheng
Subject: [committed] RISC-V: Update testcase due to message update
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-27.c: Update scan message
and zvl_unimplemented-2.c should also be fixed.
juzhe.zh...@rivai.ai
From: rep.dot.nop
Date: 2024-01-19 17:40
To: Kito Cheng; juzhe.zh...@rivai.ai
CC: Kito.cheng; jeffreyalaw; Robin Dapp; gcc-patches
Subject: Re: [PATCH] RISC-V: Tweak the wording for the sorry message
On 19 January 2024 03:41:57
LGTM.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2024-01-19 17:40
To: gcc-patches; kito.cheng; jim.wilson.gcc; palmer; andrew; jeffreyalaw;
christoph.muellner; juzhe.zhong; rep.dot.nop
CC: Kito Cheng
Subject: [PATCH v2] RISC-V: Documnet the list of supported extensions
Try to list all
(test for errors, line )
FAIL: gcc.target/riscv/attribute-10.c -Os (test for excess errors)
Could you take a look at it ?
I am not sure whether they are caused by this patch. But I find only this
patch looks related.
juzhe.zh...@rivai.ai
Thanks. I will commit V2 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/643420.html
after I finishing testing.
V2 no difference from V1 in codes except adding:
PR target/113495
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2024-01-19 16:19
To: Juzhe-Zhong
CC: gcc-patches
Could you show me the ICE message ?
Is it in front-end ? If yes, it's ok.
I wonder whether it is "internal compiler error".
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-01-19 16:04
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer; zhengyu; pan2.li
Subject: Re: Re: [PATCH] RISC
int8_t *...)
2. __riscv_vle8 (const uint8_t *...)
3. __riscv_vle8 (const int32_t *...) ---> I worry this will cause ICE since
pointer type doesn't match the expecting type,
I wonder whether it will cause ICE while resolving API.
Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-01-19
OK
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2024-01-19 10:34
To: rep.dot.nop; jeffreyalaw; rdapp.gcc; juzhe.zhong; gcc-patches
CC: Kito Cheng
Subject: [PATCH] RISC-V: Tweak the wording for the sorry message
Use "does not" rather than "cannot", because it's impleme
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-01-17 17:00
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Fix asm checks regression due to recent middle-end
change
From: Pan Li
The recent middle-end change result in some asm check
Are you saying using glibc lib ? I do the testing with newlib, I didn't
anything wrong.
It seems that this patch triggers latent bug of VSETVL PASS (Even though this
patch doesn't change anything related to VSETVL PASS).
I will investigate it.
Thanks.
juzhe.zh...@rivai.ai
From: Edwin Lu
, 4 };
_1 = b[0];
_5 = b[2];
MEM [(int *)] = vect__2.6_25;
_11 = b[4];
_13 = b[6];
_27 = {_1, _5, _11, _13};
vect__9.9_28 = _27 * { 3, 4, 5, 7 };
MEM [(int *) + 16B] = vect__9.9_28;
We can confirm it here: https://godbolt.org/z/6jGrEoz9s
juzhe.zh...@rivai.ai
From: Richard
mp; mask__4.12_197;
vect_patt_158.14_199 = .VCOND_MASK (mask_patt_157.13_198, { 1, 1, 1, 1, 1, 1,
1, 1 }, { 0, 0, 0, 0, 0, 0, 0, 0 });
vect_patt_159.15_200 = [vec_unpack_lo_expr] vect_patt_158.14_199;
vect_patt_159.15_201 = [vec_unpack_hi_expr] vect_patt_158.14_199;
juzhe.zh...@rivai.ai
From: R
LGTM. I think removing riscv_vector_abi can be another separate followup patch.
But plz make sure you have passed the regression before committed.
Thanks.
juzhe.zh...@rivai.ai
From: yanzhang.wang
Date: 2024-01-15 14:00
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; lehua.ding
I think you should also remove riscv_vector_abi
since vector ABI is ratified and we should by default enable vector calling
convention by default.
juzhe.zh...@rivai.ai
From: yanzhang.wang
Date: 2024-01-15 14:00
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; lehua.ding; yanzhang.wang
. */
if (!loop_vinfo)
record_stmt_cost (cost_vec, 1, vec_to_scalar, stmt_info, NULL_TREE,
0, vect_epilogue);
Since it's stage 4, I guess we can't change this now.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2024-01-11 17:57
To: Robin Dapp
CC: juzhe.zh
ok.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-12 11:24
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v5] RISC-V: Rewrite some instructions using ASM
ok.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-12 11:23
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v6] RISC-V: Fix register overlap issue for some
ok
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-12 11:22
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v6] RISC-V: Handle differences between XTheadvector
OK.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-12 11:21
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v5] RISC-V: Adds the prefix &qu
This patch needs kito review. I can't approve that.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-12 11:20
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; kito.cheng; Jun Sha (Joshua); Jin Ma; Xianmiao
Qu
Subject
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-01-12 10:52
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Update the comments of riscv_v_ext_mode_p [NFC]
From: Pan Li
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_v_ext_mode_p): Update
Good catch. LGTM.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-12 09:35
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH] RISC-V: Modify ABI-name length of vfloat16m8_t
The length of vfloat16m8_t ABI-name should be 17.
gcc/ChangeLog:
* config/riscv
ocal count: 359464610]:
goto ; [100.00%]
}
Final ASM:
main:
lui a5,%hi(a)
li a4,19
sb a4,%lo(a)(a5)
li a0,0
ret
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 20:56
To: juzhe.zh...@rivai.ai; Richard Biener
CC: rdapp.gcc; gcc-patches; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: [PATCH
e later pass failed
to CSE it...
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 19:15
To: juzhe.zh...@rivai.ai; Richard Biener
CC: rdapp.gcc; gcc-patches; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Increase scalar_to_vec_cost from 1 to 3
> I think we sho
for this test.
Is it reasonable ? IMHO, scalar move (vmv.v.x or vfmv.v.f) should be more
costly than normal vadd.vv since it is transferring data between different
pipeline/register class.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 19:15
To: juzhe.zh...@rivai.ai; Richard Biener
CC
times scalar_to_vec costs 3 in prologue
32872 spends 2 scalar instructions + 1 scalar_to_vec cost:
li a4,-32768
addiw a4,a4,104
vmv.v.x v16,a4
It seems reasonable but only can fix test with -march=rv64gcv_zvl256b but
failed on -march=rv64gcv_zvl4096b.
juzhe.zh...@rivai.ai
From: Robin Dapp
Da
.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 19:15
To: juzhe.zh...@rivai.ai; Richard Biener
CC: rdapp.gcc; gcc-patches; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Increase scalar_to_vec_cost from 1 to 3
> I think we shouldn't vectorize it with any vlen, since the
b, RVV Clang also doesn't vectorize it.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-01-11 18:40
To: juzhe.zh...@rivai.ai; Richard Biener
CC: rdapp.gcc; gcc-patches; kito.cheng; Kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Increase scalar_to_vec_cost from 1 to 3
On 1/11/24 11:
t_26 1 times scalar_to_vec costs 1 in prologue
This cost should be higher since it cost 3 instructions:
li a4,-32768
addiw a4,a4,104
vmv.v.x v16,a4
Am I correct ?
I guess if we cost 1 case as 1 cost and 2 case as 3 cost. Then we will be good.
juzhe.zh...@rivai.ai
From: Robi
1 - 100 of 1012 matches
Mail list logo
