From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai> gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsext_vf4-1.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4-2.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4-3.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_m-1.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_m-2.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_m-3.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_mu-1.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_mu-2.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_mu-3.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_tu-1.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_tu-2.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_tu-3.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_tum-1.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_tum-2.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_tum-3.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vsext_vf4_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vsext_vf4-1.c | 69 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf4-2.c | 69 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf4-3.c | 69 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_m-1.c | 69 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_m-2.c | 69 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsext_vf4_m-3.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_mu-1.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_mu-2.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_mu-3.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_tu-1.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_tu-2.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_tu-3.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_tum-1.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_tum-2.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_tum-3.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_tumu-1.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_tumu-2.c | 69 +++++++++++++++++++ .../riscv/rvv/base/vsext_vf4_tumu-3.c | 69 +++++++++++++++++++ 18 files changed, 1242 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-1.c new file mode 100644 index 00000000000..f853ceafce9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2(vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2(op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1(vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1(op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2(vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2(op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4(vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4(op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8(vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8(op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1(vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1(op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2(vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2(op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4(vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4(op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8(vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8(op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-2.c new file mode 100644 index 00000000000..0f7c664bfab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-2.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2(vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2(op1,31); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1(vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1(op1,31); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2(vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2(op1,31); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4(vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4(op1,31); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8(vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8(op1,31); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1(vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1(op1,31); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2(vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2(op1,31); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4(vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4(op1,31); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8(vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8(op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-3.c new file mode 100644 index 00000000000..4741663e749 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-3.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2(vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2(op1,32); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1(vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1(op1,32); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2(vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2(op1,32); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4(vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4(op1,32); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8(vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8(op1,32); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1(vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1(op1,32); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2(vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2(op1,32); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4(vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4(op1,32); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8(vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8(op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-1.c new file mode 100644 index 00000000000..53720508183 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_m(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_m(mask,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_m(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_m(mask,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_m(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_m(mask,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_m(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_m(mask,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_m(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_m(mask,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_m(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_m(mask,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_m(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_m(mask,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_m(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_m(mask,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_m(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_m(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-2.c new file mode 100644 index 00000000000..cb993f8cea2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-2.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_m(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_m(mask,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_m(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_m(mask,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_m(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_m(mask,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_m(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_m(mask,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_m(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_m(mask,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_m(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_m(mask,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_m(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_m(mask,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_m(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_m(mask,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_m(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_m(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-3.c new file mode 100644 index 00000000000..69077cb00a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-3.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_m(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_m(mask,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_m(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_m(mask,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_m(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_m(mask,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_m(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_m(mask,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_m(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_m(mask,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_m(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_m(mask,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_m(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_m(mask,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_m(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_m(mask,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_m(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_m(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-1.c new file mode 100644 index 00000000000..59ccaa7483b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_mu(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_mu(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_mu(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_mu(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_mu(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_mu(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_mu(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_mu(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_mu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-2.c new file mode 100644 index 00000000000..13766dfded7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-2.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_mu(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_mu(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_mu(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_mu(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_mu(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_mu(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_mu(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_mu(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_mu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-3.c new file mode 100644 index 00000000000..adccce339b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-3.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_mu(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_mu(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_mu(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_mu(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_mu(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_mu(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_mu(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_mu(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_mu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-1.c new file mode 100644 index 00000000000..5b65b33661f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_tu(vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_tu(merge,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_tu(vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_tu(merge,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_tu(vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_tu(merge,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_tu(vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_tu(merge,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_tu(vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_tu(merge,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_tu(vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_tu(merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_tu(vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_tu(merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_tu(vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_tu(merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_tu(vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_tu(merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-2.c new file mode 100644 index 00000000000..975b9e23389 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-2.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_tu(vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_tu(merge,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_tu(vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_tu(merge,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_tu(vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_tu(merge,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_tu(vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_tu(merge,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_tu(vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_tu(merge,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_tu(vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_tu(merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_tu(vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_tu(merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_tu(vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_tu(merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_tu(vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_tu(merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-3.c new file mode 100644 index 00000000000..173725af839 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-3.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_tu(vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_tu(merge,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_tu(vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_tu(merge,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_tu(vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_tu(merge,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_tu(vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_tu(merge,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_tu(vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_tu(merge,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_tu(vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_tu(merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_tu(vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_tu(merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_tu(vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_tu(merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_tu(vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_tu(merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-1.c new file mode 100644 index 00000000000..5f54036eef5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_tum(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_tum(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_tum(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_tum(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_tum(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_tum(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_tum(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_tum(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_tum(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-2.c new file mode 100644 index 00000000000..5b48fcbda92 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-2.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_tum(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_tum(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_tum(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_tum(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_tum(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_tum(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_tum(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_tum(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_tum(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-3.c new file mode 100644 index 00000000000..0a620e4a1ea --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-3.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_tum(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_tum(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_tum(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_tum(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_tum(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_tum(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_tum(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_tum(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_tum(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-1.c new file mode 100644 index 00000000000..0419de80927 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_tumu(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_tumu(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_tumu(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_tumu(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_tumu(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_tumu(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_tumu(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_tumu(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_tumu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-2.c new file mode 100644 index 00000000000..4451144077c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-2.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_tumu(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_tumu(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_tumu(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_tumu(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_tumu(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_tumu(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_tumu(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_tumu(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_tumu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-3.c new file mode 100644 index 00000000000..71bd40dcae7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-3.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint32mf2_t test___riscv_vsext_vf4_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32mf2_tumu(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vsext_vf4_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m1_tumu(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vsext_vf4_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m2_tumu(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vsext_vf4_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m4_tumu(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vsext_vf4_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i32m8_tumu(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vsext_vf4_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m1_tumu(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vsext_vf4_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m2_tumu(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vsext_vf4_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m4_tumu(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vsext_vf4_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vsext_vf4_i64m8_tumu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ -- 2.36.1